if_xi.c revision 1.86
1 /* $NetBSD: if_xi.c,v 1.86 2019/02/05 06:17:03 msaitoh Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.86 2019/02/05 06:17:03 msaitoh Exp $"); 59 60 #include "opt_inet.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/socket.h> 69 #include <sys/kernel.h> 70 #include <sys/proc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_ether.h> 77 #include <net/bpf.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 /* 88 * Maximum number of bytes to read per interrupt. Linux recommends 89 * somewhere between 2000-22000. 90 * XXX This is currently a hard maximum. 91 */ 92 #define MAX_BYTES_INTR 12000 93 94 #include <dev/mii/mii.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/pcmcia/pcmciareg.h> 98 #include <dev/pcmcia/pcmciavar.h> 99 #include <dev/pcmcia/pcmciadevs.h> 100 101 #include <dev/pcmcia/if_xireg.h> 102 #include <dev/pcmcia/if_xivar.h> 103 104 #ifdef __GNUC__ 105 #define INLINE inline 106 #else 107 #define INLINE 108 #endif /* __GNUC__ */ 109 110 #define XIDEBUG 111 #define XIDEBUG_VALUE 0 112 113 #ifdef XIDEBUG 114 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 115 116 #define XID_CONFIG 0x01 117 #define XID_MII 0x02 118 #define XID_INTR 0x04 119 #define XID_FIFO 0x08 120 #define XID_MCAST 0x10 121 122 #ifdef XIDEBUG_VALUE 123 int xidebug = XIDEBUG_VALUE; 124 #else 125 int xidebug = 0; 126 #endif 127 #else 128 #define DPRINTF(cat, x) (void)0 129 #endif 130 131 #define STATIC 132 133 STATIC int xi_enable(struct xi_softc *); 134 STATIC void xi_disable(struct xi_softc *); 135 STATIC void xi_cycle_power(struct xi_softc *); 136 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 137 STATIC void xi_full_reset(struct xi_softc *); 138 STATIC void xi_init(struct xi_softc *); 139 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 140 STATIC int xi_mdi_read(device_t, int, int, uint16_t *); 141 STATIC int xi_mdi_write(device_t, int, int, uint16_t); 142 STATIC int xi_mediachange(struct ifnet *); 143 STATIC uint16_t xi_get(struct xi_softc *); 144 STATIC void xi_reset(struct xi_softc *); 145 STATIC void xi_set_address(struct xi_softc *); 146 STATIC void xi_start(struct ifnet *); 147 STATIC void xi_statchg(struct ifnet *); 148 STATIC void xi_stop(struct xi_softc *); 149 STATIC void xi_watchdog(struct ifnet *); 150 151 void 152 xi_attach(struct xi_softc *sc, uint8_t *myea) 153 { 154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 155 #ifdef XIDEBUG 156 uint16_t bmsr; 157 #endif 158 #if 0 159 /* 160 * Configuration as advised by DINGO documentation. 161 * Dingo has some extra configuration registers in the CCR space. 162 */ 163 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 164 struct pcmcia_mem_handle pcmh; 165 int ccr_window; 166 bus_size_t ccr_offset; 167 168 /* get access to the DINGO CCR space */ 169 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 170 &pcmh)) { 171 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 172 goto fail; 173 } 174 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 175 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 176 &pcmh, &ccr_offset, &ccr_window)) { 177 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 178 pcmcia_mem_free(psc->sc_pf, &pcmh); 179 goto fail; 180 } 181 182 /* enable the second function - usually modem */ 183 bus_space_write_1(pcmh.memt, pcmh.memh, 184 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 185 bus_space_write_1(pcmh.memt, pcmh.memh, 186 ccr_offset + PCMCIA_CCR_DCOR1, 187 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 188 bus_space_write_1(pcmh.memt, pcmh.memh, 189 ccr_offset + PCMCIA_CCR_DCOR2, 0); 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR3, 0); 192 bus_space_write_1(pcmh.memt, pcmh.memh, 193 ccr_offset + PCMCIA_CCR_DCOR4, 0); 194 195 /* We don't need them anymore and can free them (I think). */ 196 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 197 pcmcia_mem_free(psc->sc_pf, &pcmh); 198 } 199 #endif 200 201 /* Reset and initialize the card. */ 202 xi_full_reset(sc); 203 204 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 205 206 ifp = &sc->sc_ethercom.ec_if; 207 /* Initialize the ifnet structure. */ 208 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 209 ifp->if_softc = sc; 210 ifp->if_start = xi_start; 211 ifp->if_ioctl = xi_ioctl; 212 ifp->if_watchdog = xi_watchdog; 213 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 214 IFQ_SET_READY(&ifp->if_snd); 215 216 /* 802.1q capability */ 217 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 218 219 /* Attach the interface. */ 220 if_attach(ifp); 221 if_deferred_start_init(ifp, NULL); 222 ether_ifattach(ifp, myea); 223 224 /* 225 * Initialize our media structures and probe the MII. 226 */ 227 sc->sc_mii.mii_ifp = ifp; 228 sc->sc_mii.mii_readreg = xi_mdi_read; 229 sc->sc_mii.mii_writereg = xi_mdi_write; 230 sc->sc_mii.mii_statchg = xi_statchg; 231 sc->sc_ethercom.ec_mii = &sc->sc_mii; 232 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 233 ether_mediastatus); 234 #ifdef XIDEBUG 235 xi_mdi_read(sc->sc_dev, 0, 1, &bmsr); 236 DPRINTF(XID_MII | XID_CONFIG, ("xi: bmsr %x\n", bmsr)); 237 #endif 238 239 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 240 MII_OFFSET_ANY, 0); 241 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 242 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 243 NULL); 244 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 245 246 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 247 RND_TYPE_NET, RND_FLAG_DEFAULT); 248 } 249 250 int 251 xi_detach(device_t self, int flags) 252 { 253 struct xi_softc *sc = device_private(self); 254 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 255 256 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 257 258 xi_disable(sc); 259 260 rnd_detach_source(&sc->sc_rnd_source); 261 262 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 263 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 264 ether_ifdetach(ifp); 265 if_detach(ifp); 266 267 return 0; 268 } 269 270 int 271 xi_intr(void *arg) 272 { 273 struct xi_softc *sc = arg; 274 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 275 uint8_t esr, rsr, isr, rx_status; 276 uint16_t tx_status, recvcount = 0, tempint; 277 278 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 279 280 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 281 return (0); 282 283 ifp->if_timer = 0; /* turn watchdog timer off */ 284 285 PAGE(sc, 0); 286 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 287 /* Disable interrupt (Linux does it). */ 288 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 289 } 290 291 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 292 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 293 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 294 295 /* Check to see if card has been ejected. */ 296 if (isr == 0xff) { 297 #ifdef DIAGNOSTIC 298 printf("%s: interrupt for dead card\n", 299 device_xname(sc->sc_dev)); 300 #endif 301 goto end; 302 } 303 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 304 305 PAGE(sc, 0x40); 306 rx_status = 307 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 308 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 309 tx_status = 310 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 311 tx_status |= 312 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 313 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 314 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 315 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 316 tx_status)); 317 318 PAGE(sc, 0); 319 while (esr & FULL_PKT_RCV) { 320 if (!(rsr & RSR_RX_OK)) 321 break; 322 323 /* Compare bytes read this interrupt to hard maximum. */ 324 if (recvcount > MAX_BYTES_INTR) { 325 DPRINTF(XID_INTR, 326 ("xi: too many bytes this interrupt\n")); 327 ifp->if_iqdrops++; 328 /* Drop packet. */ 329 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 330 DO_SKIP_RX_PKT); 331 } 332 tempint = xi_get(sc); /* XXX doesn't check the error! */ 333 recvcount += tempint; 334 ifp->if_ibytes += tempint; 335 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 336 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 337 } 338 339 /* Packet too long? */ 340 if (rsr & RSR_TOO_LONG) { 341 ifp->if_ierrors++; 342 DPRINTF(XID_INTR, ("xi: packet too long\n")); 343 } 344 345 /* CRC error? */ 346 if (rsr & RSR_CRCERR) { 347 ifp->if_ierrors++; 348 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 349 } 350 351 /* Alignment error? */ 352 if (rsr & RSR_ALIGNERR) { 353 ifp->if_ierrors++; 354 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 355 } 356 357 /* Check for rx overrun. */ 358 if (rx_status & RX_OVERRUN) { 359 ifp->if_ierrors++; 360 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 361 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 362 } 363 364 /* Try to start more packets transmitting. */ 365 if_schedule_deferred_start(ifp); 366 367 /* Detected excessive collisions? */ 368 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 369 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 370 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 371 ifp->if_oerrors++; 372 } 373 374 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 375 ifp->if_oerrors++; 376 377 /* have handled the interrupt */ 378 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 379 380 end: 381 /* Reenable interrupts. */ 382 PAGE(sc, 0); 383 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 384 385 return (1); 386 } 387 388 /* 389 * Pull a packet from the card into an mbuf chain. 390 */ 391 STATIC uint16_t 392 xi_get(struct xi_softc *sc) 393 { 394 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 395 struct mbuf *top, **mp, *m; 396 uint16_t pktlen, len, recvcount = 0; 397 uint8_t *data; 398 399 DPRINTF(XID_CONFIG, ("xi_get()\n")); 400 401 PAGE(sc, 0); 402 pktlen = 403 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 404 405 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 406 407 if (pktlen == 0) { 408 /* 409 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 410 * when MPE is set. It is not known why. 411 */ 412 return (0); 413 } 414 415 /* XXX should this be incremented now ? */ 416 recvcount += pktlen; 417 418 MGETHDR(m, M_DONTWAIT, MT_DATA); 419 if (m == NULL) 420 return (recvcount); 421 m_set_rcvif(m, ifp); 422 m->m_pkthdr.len = pktlen; 423 len = MHLEN; 424 top = NULL; 425 mp = ⊤ 426 427 while (pktlen > 0) { 428 if (top) { 429 MGET(m, M_DONTWAIT, MT_DATA); 430 if (m == NULL) { 431 m_freem(top); 432 return (recvcount); 433 } 434 len = MLEN; 435 } 436 if (pktlen >= MINCLSIZE) { 437 MCLGET(m, M_DONTWAIT); 438 if (!(m->m_flags & M_EXT)) { 439 m_freem(m); 440 m_freem(top); 441 return (recvcount); 442 } 443 len = MCLBYTES; 444 } 445 if (top == NULL) { 446 char *newdata = (char *)ALIGN(m->m_data + 447 sizeof(struct ether_header)) - 448 sizeof(struct ether_header); 449 len -= newdata - m->m_data; 450 m->m_data = newdata; 451 } 452 len = uimin(pktlen, len); 453 data = mtod(m, uint8_t *); 454 if (len > 1) { 455 len &= ~1; 456 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 457 (uint16_t *)data, len>>1); 458 } else 459 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 460 m->m_len = len; 461 pktlen -= len; 462 *mp = m; 463 mp = &m->m_next; 464 } 465 466 /* Skip Rx packet. */ 467 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 468 469 if (top == NULL) 470 return recvcount; 471 472 /* Trim the CRC off the end of the packet. */ 473 m_adj(top, -ETHER_CRC_LEN); 474 475 if_percpuq_enqueue(ifp->if_percpuq, top); 476 return (recvcount); 477 } 478 479 /* 480 * Serial management for the MII. 481 * The DELAY's below stem from the fact that the maximum frequency 482 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 483 * go much faster than that. 484 */ 485 486 /* Let the MII serial management be idle for one period. */ 487 static INLINE void xi_mdi_idle(struct xi_softc *); 488 static INLINE void 489 xi_mdi_idle(struct xi_softc *sc) 490 { 491 bus_space_tag_t bst = sc->sc_bst; 492 bus_space_handle_t bsh = sc->sc_bsh; 493 494 /* Drive MDC low... */ 495 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 496 DELAY(1); 497 498 /* and high again. */ 499 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 500 DELAY(1); 501 } 502 503 /* Pulse out one bit of data. */ 504 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 505 static INLINE void 506 xi_mdi_pulse(struct xi_softc *sc, int data) 507 { 508 bus_space_tag_t bst = sc->sc_bst; 509 bus_space_handle_t bsh = sc->sc_bsh; 510 uint8_t bit = data ? MDIO_HIGH : MDIO_LOW; 511 512 /* First latch the data bit MDIO with clock bit MDC low...*/ 513 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 514 DELAY(1); 515 516 /* then raise the clock again, preserving the data bit. */ 517 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 518 DELAY(1); 519 } 520 521 /* Probe one bit of data. */ 522 static INLINE int xi_mdi_probe(struct xi_softc *sc); 523 static INLINE int 524 xi_mdi_probe(struct xi_softc *sc) 525 { 526 bus_space_tag_t bst = sc->sc_bst; 527 bus_space_handle_t bsh = sc->sc_bsh; 528 uint8_t x; 529 530 /* Pull clock bit MDCK low... */ 531 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 532 DELAY(1); 533 534 /* Read data and drive clock high again. */ 535 x = bus_space_read_1(bst, bsh, GP2); 536 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 537 DELAY(1); 538 539 return (x & MDIO); 540 } 541 542 /* Pulse out a sequence of data bits. */ 543 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, uint32_t, int); 544 static INLINE void 545 xi_mdi_pulse_bits(struct xi_softc *sc, uint32_t data, int len) 546 { 547 uint32_t mask; 548 549 for (mask = 1 << (len - 1); mask; mask >>= 1) 550 xi_mdi_pulse(sc, data & mask); 551 } 552 553 /* Read a PHY register. */ 554 STATIC int 555 xi_mdi_read(device_t self, int phy, int reg, uint16_t *val) 556 { 557 struct xi_softc *sc = device_private(self); 558 int i; 559 uint32_t mask; 560 uint16_t data = 0; 561 562 PAGE(sc, 2); 563 for (i = 0; i < 32; i++) /* Synchronize. */ 564 xi_mdi_pulse(sc, 1); 565 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 566 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 567 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 568 xi_mdi_idle(sc); /* Turn around. */ 569 xi_mdi_probe(sc); /* Drop initial zero bit. */ 570 571 for (mask = 1 << 15; mask; mask >>= 1) { 572 if (xi_mdi_probe(sc)) 573 data |= mask; 574 } 575 xi_mdi_idle(sc); 576 577 DPRINTF(XID_MII, 578 ("xi_mdi_read: phy %d reg %d -> %04hx\n", phy, reg, data)); 579 580 *val = data; 581 return 0; 582 } 583 584 /* Write a PHY register. */ 585 STATIC int 586 xi_mdi_write(device_t self, int phy, int reg, uint16_t val) 587 { 588 struct xi_softc *sc = device_private(self); 589 int i; 590 591 PAGE(sc, 2); 592 for (i = 0; i < 32; i++) /* Synchronize. */ 593 xi_mdi_pulse(sc, 1); 594 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 595 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 596 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 597 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 598 xi_mdi_pulse_bits(sc, val, 16); /* Write the data */ 599 xi_mdi_idle(sc); /* Idle away. */ 600 601 DPRINTF(XID_MII, 602 ("xi_mdi_write: phy %d reg %d val %04hx\n", phy, reg, val)); 603 604 return 0; 605 } 606 607 STATIC void 608 xi_statchg(struct ifnet *ifp) 609 { 610 /* XXX Update ifp->if_baudrate */ 611 } 612 613 /* 614 * Change media according to request. 615 */ 616 STATIC int 617 xi_mediachange(struct ifnet *ifp) 618 { 619 int s; 620 621 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 622 623 if (ifp->if_flags & IFF_UP) { 624 s = splnet(); 625 xi_init(ifp->if_softc); 626 splx(s); 627 } 628 return (0); 629 } 630 631 STATIC void 632 xi_reset(struct xi_softc *sc) 633 { 634 int s; 635 636 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 637 638 s = splnet(); 639 xi_stop(sc); 640 xi_init(sc); 641 splx(s); 642 } 643 644 STATIC void 645 xi_watchdog(struct ifnet *ifp) 646 { 647 struct xi_softc *sc = ifp->if_softc; 648 649 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 650 ++ifp->if_oerrors; 651 652 xi_reset(sc); 653 } 654 655 STATIC void 656 xi_stop(register struct xi_softc *sc) 657 { 658 bus_space_tag_t bst = sc->sc_bst; 659 bus_space_handle_t bsh = sc->sc_bsh; 660 661 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 662 663 PAGE(sc, 0x40); 664 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 665 666 /* Disable interrupts. */ 667 PAGE(sc, 0); 668 bus_space_write_1(bst, bsh, CR, 0); 669 670 PAGE(sc, 1); 671 bus_space_write_1(bst, bsh, IMR0, 0); 672 673 /* Cancel watchdog timer. */ 674 sc->sc_ethercom.ec_if.if_timer = 0; 675 } 676 677 STATIC int 678 xi_enable(struct xi_softc *sc) 679 { 680 int error; 681 682 if (!sc->sc_enabled) { 683 error = (*sc->sc_enable)(sc); 684 if (error) 685 return (error); 686 sc->sc_enabled = 1; 687 xi_full_reset(sc); 688 } 689 return (0); 690 } 691 692 STATIC void 693 xi_disable(struct xi_softc *sc) 694 { 695 696 if (sc->sc_enabled) { 697 sc->sc_enabled = 0; 698 (*sc->sc_disable)(sc); 699 } 700 } 701 702 STATIC void 703 xi_init(struct xi_softc *sc) 704 { 705 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 706 bus_space_tag_t bst = sc->sc_bst; 707 bus_space_handle_t bsh = sc->sc_bsh; 708 709 DPRINTF(XID_CONFIG, ("xi_init()\n")); 710 711 /* Setup the ethernet interrupt mask. */ 712 PAGE(sc, 1); 713 bus_space_write_1(bst, bsh, IMR0, 714 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 715 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 716 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 717 /* XXX What is this? Not for Dingo at least. */ 718 /* Unmask TX underrun detection */ 719 bus_space_write_1(bst, bsh, IMR1, 1); 720 } 721 722 /* Enable interrupts. */ 723 PAGE(sc, 0); 724 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 725 726 xi_set_address(sc); 727 728 PAGE(sc, 0x40); 729 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 730 731 PAGE(sc, 0); 732 733 /* Set current media. */ 734 mii_mediachg(&sc->sc_mii); 735 736 ifp->if_flags |= IFF_RUNNING; 737 ifp->if_flags &= ~IFF_OACTIVE; 738 739 xi_start(ifp); 740 } 741 742 /* 743 * Start outputting on the interface. 744 * Always called as splnet(). 745 */ 746 STATIC void 747 xi_start(struct ifnet *ifp) 748 { 749 struct xi_softc *sc = ifp->if_softc; 750 bus_space_tag_t bst = sc->sc_bst; 751 bus_space_handle_t bsh = sc->sc_bsh; 752 unsigned int s, len, pad = 0; 753 struct mbuf *m0, *m; 754 uint16_t space; 755 756 DPRINTF(XID_CONFIG, ("xi_start()\n")); 757 758 /* Don't transmit if interface is busy or not running. */ 759 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 760 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 761 return; 762 } 763 764 /* Peek at the next packet. */ 765 IFQ_POLL(&ifp->if_snd, m0); 766 if (m0 == 0) 767 return; 768 769 /* We need to use m->m_pkthdr.len, so require the header. */ 770 if (!(m0->m_flags & M_PKTHDR)) 771 panic("xi_start: no header mbuf"); 772 773 len = m0->m_pkthdr.len; 774 775 #if 1 776 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 777 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 778 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 779 #else 780 pad = 0; 781 #endif 782 783 PAGE(sc, 0); 784 785 bus_space_write_2(bst, bsh, TRS, (uint16_t)len + pad + 2); 786 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 787 if (len + pad + 2 > space) { 788 DPRINTF(XID_FIFO, 789 ("xi: not enough space in output FIFO (%d > %d)\n", 790 len + pad + 2, space)); 791 return; 792 } 793 794 IFQ_DEQUEUE(&ifp->if_snd, m0); 795 796 bpf_mtap(ifp, m0, BPF_D_OUT); 797 798 /* 799 * Do the output at splhigh() so that an interrupt from another device 800 * won't cause a FIFO underrun. 801 */ 802 s = splhigh(); 803 804 bus_space_write_2(bst, bsh, EDP, (uint16_t)len + pad); 805 for (m = m0; m; ) { 806 if (m->m_len > 1) 807 bus_space_write_multi_2(bst, bsh, EDP, 808 mtod(m, uint16_t *), m->m_len>>1); 809 if (m->m_len & 1) { 810 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 811 bus_space_write_1(bst, bsh, EDP, 812 *(mtod(m, uint8_t *) + m->m_len - 1)); 813 } 814 m = m0 = m_free(m); 815 } 816 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 817 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 818 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 819 else { 820 for (; pad > 1; pad -= 2) 821 bus_space_write_2(bst, bsh, EDP, 0); 822 if (pad == 1) 823 bus_space_write_1(bst, bsh, EDP, 0); 824 } 825 826 splx(s); 827 828 ifp->if_timer = 5; 829 ++ifp->if_opackets; 830 } 831 832 STATIC int 833 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 834 { 835 struct ifaddr *ifa = (struct ifaddr *)data; 836 struct xi_softc *sc = ifp->if_softc; 837 int error; 838 839 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 840 841 switch (cmd) { 842 case SIOCINITIFADDR: 843 if ((error = xi_enable(sc)) != 0) 844 break; 845 846 ifp->if_flags |= IFF_UP; 847 848 xi_init(sc); 849 switch (ifa->ifa_addr->sa_family) { 850 #ifdef INET 851 case AF_INET: 852 arp_ifinit(ifp, ifa); 853 break; 854 #endif /* INET */ 855 856 857 default: 858 break; 859 } 860 break; 861 862 default: 863 return (EINVAL); 864 } 865 866 return (0); 867 } 868 869 STATIC int 870 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 871 { 872 struct xi_softc *sc = ifp->if_softc; 873 int s, error = 0; 874 875 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 876 877 s = splnet(); 878 879 switch (cmd) { 880 case SIOCINITIFADDR: 881 error = xi_ether_ioctl(ifp, cmd, data); 882 break; 883 884 case SIOCSIFFLAGS: 885 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 886 break; 887 /* XXX re-use ether_ioctl() */ 888 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 889 case IFF_RUNNING: 890 /* 891 * If interface is marked down and it is running, 892 * stop it. 893 */ 894 xi_stop(sc); 895 ifp->if_flags &= ~IFF_RUNNING; 896 xi_disable(sc); 897 break; 898 case IFF_UP: 899 /* 900 * If interface is marked up and it is stopped, 901 * start it. 902 */ 903 if ((error = xi_enable(sc)) != 0) 904 break; 905 xi_init(sc); 906 break; 907 case IFF_UP|IFF_RUNNING: 908 /* 909 * Reset the interface to pick up changes in any 910 * other flags that affect hardware registers. 911 */ 912 xi_set_address(sc); 913 break; 914 case 0: 915 break; 916 } 917 break; 918 919 case SIOCADDMULTI: 920 case SIOCDELMULTI: 921 if (sc->sc_enabled == 0) { 922 error = EIO; 923 break; 924 } 925 /*FALLTHROUGH*/ 926 case SIOCSIFMEDIA: 927 case SIOCGIFMEDIA: 928 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 929 /* 930 * Multicast list has changed; set the hardware 931 * filter accordingly. 932 */ 933 if (ifp->if_flags & IFF_RUNNING) 934 xi_set_address(sc); 935 error = 0; 936 } 937 break; 938 939 default: 940 error = ether_ioctl(ifp, cmd, data); 941 break; 942 } 943 944 splx(s); 945 return (error); 946 } 947 948 STATIC void 949 xi_set_address(struct xi_softc *sc) 950 { 951 bus_space_tag_t bst = sc->sc_bst; 952 bus_space_handle_t bsh = sc->sc_bsh; 953 struct ethercom *ether = &sc->sc_ethercom; 954 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 955 struct ether_multistep step; 956 struct ether_multi *enm; 957 int page, num; 958 int i; 959 uint8_t x; 960 const uint8_t *enaddr; 961 uint8_t indaddr[64]; 962 963 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 964 965 enaddr = (const uint8_t *)CLLADDR(ifp->if_sadl); 966 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 967 for (i = 0; i < 6; i++) 968 indaddr[i] = enaddr[5 - i]; 969 else 970 for (i = 0; i < 6; i++) 971 indaddr[i] = enaddr[i]; 972 num = 1; 973 974 if (ether->ec_multicnt > 9) { 975 ifp->if_flags |= IFF_ALLMULTI; 976 goto done; 977 } 978 979 ETHER_FIRST_MULTI(step, ether, enm); 980 for (; enm; num++) { 981 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 982 sizeof(enm->enm_addrlo)) != 0) { 983 /* 984 * The multicast address is really a range; 985 * it's easier just to accept all multicasts. 986 * XXX should we be setting IFF_ALLMULTI here? 987 */ 988 ifp->if_flags |= IFF_ALLMULTI; 989 goto done; 990 } 991 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 992 for (i = 0; i < 6; i++) 993 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 994 else 995 for (i = 0; i < 6; i++) 996 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 997 ETHER_NEXT_MULTI(step, enm); 998 } 999 ifp->if_flags &= ~IFF_ALLMULTI; 1000 1001 done: 1002 if (num < 10) 1003 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1004 1005 for (page = 0; page < 8; page++) { 1006 #ifdef XIDEBUG 1007 if (xidebug & XID_MCAST) { 1008 printf("page %d before:", page); 1009 for (i = 0; i < 8; i++) 1010 printf(" %02x", indaddr[page * 8 + i]); 1011 printf("\n"); 1012 } 1013 #endif 1014 1015 PAGE(sc, 0x50 + page); 1016 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1017 page == 7 ? 4 : 8); 1018 /* 1019 * XXX 1020 * Without this delay, the address registers on my CE2 get 1021 * trashed the first and I have to cycle it. I have no idea 1022 * why. - mycroft, 2004/08/09 1023 */ 1024 DELAY(50); 1025 1026 #ifdef XIDEBUG 1027 if (xidebug & XID_MCAST) { 1028 bus_space_read_region_1(bst, bsh, IA, 1029 &indaddr[page * 8], page == 7 ? 4 : 8); 1030 printf("page %d after: ", page); 1031 for (i = 0; i < 8; i++) 1032 printf(" %02x", indaddr[page * 8 + i]); 1033 printf("\n"); 1034 } 1035 #endif 1036 } 1037 1038 PAGE(sc, 0x42); 1039 x = SWC1_IND_ADDR; 1040 if (ifp->if_flags & IFF_PROMISC) 1041 x |= SWC1_PROMISC; 1042 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1043 x |= SWC1_MCAST_PROM; 1044 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1045 x |= SWC1_AUTO_MEDIA; 1046 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1047 } 1048 1049 STATIC void 1050 xi_cycle_power(struct xi_softc *sc) 1051 { 1052 bus_space_tag_t bst = sc->sc_bst; 1053 bus_space_handle_t bsh = sc->sc_bsh; 1054 1055 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1056 1057 PAGE(sc, 4); 1058 DELAY(1); 1059 bus_space_write_1(bst, bsh, GP1, 0); 1060 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1061 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1062 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1063 else 1064 /* XXX What is bit 2 (aka AIC)? */ 1065 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1066 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1067 } 1068 1069 STATIC void 1070 xi_full_reset(struct xi_softc *sc) 1071 { 1072 bus_space_tag_t bst = sc->sc_bst; 1073 bus_space_handle_t bsh = sc->sc_bsh; 1074 uint8_t x; 1075 1076 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1077 1078 /* Do an as extensive reset as possible on all functions. */ 1079 xi_cycle_power(sc); 1080 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1081 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1082 bus_space_write_1(bst, bsh, CR, 0); 1083 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1084 PAGE(sc, 4); 1085 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1086 /* 1087 * Drive GP1 low to power up ML6692 and GP2 high to power up 1088 * the 10MHz chip. XXX What chip is that? The phy? 1089 */ 1090 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1091 } 1092 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1093 1094 /* Get revision information. XXX Symbolic constants. */ 1095 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1096 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1097 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1098 1099 /* Media selection. XXX Maybe manual overriding too? */ 1100 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1101 /* 1102 * XXX I have no idea what this really does, it is from the 1103 * Linux driver. 1104 */ 1105 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1106 } 1107 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1108 1109 /* 1110 * Disable source insertion. 1111 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1112 */ 1113 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1114 PAGE(sc, 0x42); 1115 bus_space_write_1(bst, bsh, SWC0, 0x20); 1116 } 1117 1118 /* Set the local memory dividing line. */ 1119 if (sc->sc_rev != 1) { 1120 PAGE(sc, 2); 1121 /* XXX Symbolic constant preferrable. */ 1122 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1123 } 1124 1125 /* 1126 * Apparently the receive byte pointer can be bad after a reset, so 1127 * we hardwire it correctly. 1128 */ 1129 PAGE(sc, 0); 1130 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1131 1132 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1133 PAGE(sc, 0x40); 1134 bus_space_write_1(bst, bsh, RX0MSK, 1135 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1136 bus_space_write_1(bst, bsh, TX0MSK, 1137 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1138 SQE | TX_ABORT | TX_OK); 1139 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1140 /* XXX From Linux, dunno what 0xb0 means. */ 1141 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1142 bus_space_write_1(bst, bsh, RXST0, 0); 1143 bus_space_write_1(bst, bsh, TXST0, 0); 1144 bus_space_write_1(bst, bsh, TXST1, 0); 1145 1146 PAGE(sc, 2); 1147 1148 /* Enable MII function if available. */ 1149 x = 0; 1150 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1151 x |= SELECT_MII; 1152 bus_space_write_1(bst, bsh, MSR, x); 1153 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1154 1155 /* Configure the LED registers. */ 1156 /* XXX This is not good for 10base2. */ 1157 bus_space_write_1(bst, bsh, LED, 1158 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1159 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1160 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1161 1162 /* 1163 * The Linux driver says this: 1164 * We should switch back to page 0 to avoid a bug in revision 0 1165 * where regs with offset below 8 can't be read after an access 1166 * to the MAC registers. 1167 */ 1168 PAGE(sc, 0); 1169 } 1170
Indexes created Tue Sep 30 17:09:57 GMT 2025