if_xi.c revision 1.94
1 /* $NetBSD: if_xi.c,v 1.94 2020/02/02 05:56:42 thorpej Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.94 2020/02/02 05:56:42 thorpej Exp $"); 59 60 #include "opt_inet.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/socket.h> 69 #include <sys/kernel.h> 70 #include <sys/proc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_ether.h> 77 #include <net/bpf.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 /* 88 * Maximum number of bytes to read per interrupt. Linux recommends 89 * somewhere between 2000-22000. 90 * XXX This is currently a hard maximum. 91 */ 92 #define MAX_BYTES_INTR 12000 93 94 #include <dev/mii/mii.h> 95 #include <dev/mii/miivar.h> 96 97 #include <dev/pcmcia/pcmciareg.h> 98 #include <dev/pcmcia/pcmciavar.h> 99 #include <dev/pcmcia/pcmciadevs.h> 100 101 #include <dev/pcmcia/if_xireg.h> 102 #include <dev/pcmcia/if_xivar.h> 103 104 #ifdef __GNUC__ 105 #define INLINE inline 106 #else 107 #define INLINE 108 #endif /* __GNUC__ */ 109 110 #define XIDEBUG 111 #define XIDEBUG_VALUE 0 112 113 #ifdef XIDEBUG 114 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 115 116 #define XID_CONFIG 0x01 117 #define XID_MII 0x02 118 #define XID_INTR 0x04 119 #define XID_FIFO 0x08 120 #define XID_MCAST 0x10 121 122 #ifdef XIDEBUG_VALUE 123 int xidebug = XIDEBUG_VALUE; 124 #else 125 int xidebug = 0; 126 #endif 127 #else 128 #define DPRINTF(cat, x) (void)0 129 #endif 130 131 #define STATIC static 132 133 STATIC int xi_enable(struct xi_softc *); 134 STATIC void xi_disable(struct xi_softc *); 135 STATIC void xi_cycle_power(struct xi_softc *); 136 STATIC int xi_ether_ioctl(struct ifnet *, u_long, void *); 137 STATIC void xi_full_reset(struct xi_softc *); 138 STATIC void xi_init(struct xi_softc *); 139 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 140 STATIC int xi_mdi_read(device_t, int, int, uint16_t *); 141 STATIC int xi_mdi_write(device_t, int, int, uint16_t); 142 STATIC int xi_mediachange(struct ifnet *); 143 STATIC uint16_t xi_get(struct xi_softc *); 144 STATIC void xi_reset(struct xi_softc *); 145 STATIC void xi_set_address(struct xi_softc *); 146 STATIC void xi_start(struct ifnet *); 147 STATIC void xi_statchg(struct ifnet *); 148 STATIC void xi_stop(struct xi_softc *); 149 STATIC void xi_watchdog(struct ifnet *); 150 151 void 152 xi_attach(struct xi_softc *sc, uint8_t *myea) 153 { 154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 155 struct mii_data * const mii = &sc->sc_mii; 156 #ifdef XIDEBUG 157 uint16_t bmsr; 158 #endif 159 #if 0 160 /* 161 * Configuration as advised by DINGO documentation. 162 * Dingo has some extra configuration registers in the CCR space. 163 */ 164 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 165 struct pcmcia_mem_handle pcmh; 166 int ccr_window; 167 bus_size_t ccr_offset; 168 169 /* get access to the DINGO CCR space */ 170 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 171 &pcmh)) { 172 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 173 goto fail; 174 } 175 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 176 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 177 &pcmh, &ccr_offset, &ccr_window)) { 178 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 179 pcmcia_mem_free(psc->sc_pf, &pcmh); 180 goto fail; 181 } 182 183 /* enable the second function - usually modem */ 184 bus_space_write_1(pcmh.memt, pcmh.memh, 185 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 186 bus_space_write_1(pcmh.memt, pcmh.memh, 187 ccr_offset + PCMCIA_CCR_DCOR1, 188 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 189 bus_space_write_1(pcmh.memt, pcmh.memh, 190 ccr_offset + PCMCIA_CCR_DCOR2, 0); 191 bus_space_write_1(pcmh.memt, pcmh.memh, 192 ccr_offset + PCMCIA_CCR_DCOR3, 0); 193 bus_space_write_1(pcmh.memt, pcmh.memh, 194 ccr_offset + PCMCIA_CCR_DCOR4, 0); 195 196 /* We don't need them anymore and can free them (I think). */ 197 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 198 pcmcia_mem_free(psc->sc_pf, &pcmh); 199 } 200 #endif 201 202 /* Reset and initialize the card. */ 203 xi_full_reset(sc); 204 205 device_printf(sc->sc_dev, "MAC address %s\n", ether_sprintf(myea)); 206 207 ifp = &sc->sc_ethercom.ec_if; 208 /* Initialize the ifnet structure. */ 209 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 210 ifp->if_softc = sc; 211 ifp->if_start = xi_start; 212 ifp->if_ioctl = xi_ioctl; 213 ifp->if_watchdog = xi_watchdog; 214 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 215 IFQ_SET_READY(&ifp->if_snd); 216 217 /* 802.1q capability */ 218 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 219 220 /* Attach the interface. */ 221 if_attach(ifp); 222 if_deferred_start_init(ifp, NULL); 223 ether_ifattach(ifp, myea); 224 225 /* 226 * Initialize our media structures and probe the MII. 227 */ 228 mii->mii_ifp = ifp; 229 mii->mii_readreg = xi_mdi_read; 230 mii->mii_writereg = xi_mdi_write; 231 mii->mii_statchg = xi_statchg; 232 sc->sc_ethercom.ec_mii = mii; 233 ifmedia_init(&mii->mii_media, 0, xi_mediachange, ether_mediastatus); 234 #ifdef XIDEBUG 235 xi_mdi_read(sc->sc_dev, 0, 1, &bmsr); 236 DPRINTF(XID_MII | XID_CONFIG, ("xi: bmsr %x\n", bmsr)); 237 #endif 238 239 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 240 MII_OFFSET_ANY, 0); 241 if (LIST_FIRST(&mii->mii_phys) == NULL) 242 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); 243 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 244 245 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 246 RND_TYPE_NET, RND_FLAG_DEFAULT); 247 } 248 249 int 250 xi_detach(device_t self, int flags) 251 { 252 struct xi_softc *sc = device_private(self); 253 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 254 255 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 256 257 xi_disable(sc); 258 259 rnd_detach_source(&sc->sc_rnd_source); 260 261 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 262 ether_ifdetach(ifp); 263 if_detach(ifp); 264 ifmedia_fini(&sc->sc_mii.mii_media); 265 266 return 0; 267 } 268 269 int 270 xi_intr(void *arg) 271 { 272 struct xi_softc *sc = arg; 273 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 274 uint8_t esr, rsr, isr, rx_status; 275 uint16_t tx_status, recvcount = 0, tempint; 276 277 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 278 279 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 280 return (0); 281 282 ifp->if_timer = 0; /* turn watchdog timer off */ 283 284 PAGE(sc, 0); 285 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 286 /* Disable interrupt (Linux does it). */ 287 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 288 } 289 290 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 291 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 292 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 293 294 /* Check to see if card has been ejected. */ 295 if (isr == 0xff) { 296 #ifdef DIAGNOSTIC 297 printf("%s: interrupt for dead card\n", 298 device_xname(sc->sc_dev)); 299 #endif 300 goto end; 301 } 302 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 303 304 PAGE(sc, 0x40); 305 rx_status = 306 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 307 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 308 tx_status = 309 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 310 tx_status |= 311 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 312 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 313 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 314 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 315 tx_status)); 316 317 PAGE(sc, 0); 318 while (esr & FULL_PKT_RCV) { 319 if (!(rsr & RSR_RX_OK)) 320 break; 321 322 /* Compare bytes read this interrupt to hard maximum. */ 323 if (recvcount > MAX_BYTES_INTR) { 324 DPRINTF(XID_INTR, 325 ("xi: too many bytes this interrupt\n")); 326 if_statinc(ifp, if_iqdrops); 327 /* Drop packet. */ 328 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 329 DO_SKIP_RX_PKT); 330 } 331 tempint = xi_get(sc); /* XXX doesn't check the error! */ 332 recvcount += tempint; 333 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 334 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 335 } 336 337 /* Packet too long? */ 338 if (rsr & RSR_TOO_LONG) { 339 if_statinc(ifp, if_ierrors); 340 DPRINTF(XID_INTR, ("xi: packet too long\n")); 341 } 342 343 /* CRC error? */ 344 if (rsr & RSR_CRCERR) { 345 if_statinc(ifp, if_ierrors); 346 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 347 } 348 349 /* Alignment error? */ 350 if (rsr & RSR_ALIGNERR) { 351 if_statinc(ifp, if_ierrors); 352 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 353 } 354 355 /* Check for rx overrun. */ 356 if (rx_status & RX_OVERRUN) { 357 if_statinc(ifp, if_ierrors); 358 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 359 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 360 } 361 362 /* Try to start more packets transmitting. */ 363 if_schedule_deferred_start(ifp); 364 365 /* Detected excessive collisions? */ 366 if ((tx_status & EXCESSIVE_COLL) /* XXX && ifp->if_opackets > 0 */) { 367 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 368 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 369 if_statinc(ifp, if_oerrors); 370 } 371 372 if ((tx_status & TX_ABORT) /* && XXX ifp->if_opackets > 0 */) 373 if_statinc(ifp, if_oerrors); 374 375 /* have handled the interrupt */ 376 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 377 378 end: 379 /* Reenable interrupts. */ 380 PAGE(sc, 0); 381 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 382 383 return (1); 384 } 385 386 /* 387 * Pull a packet from the card into an mbuf chain. 388 */ 389 STATIC uint16_t 390 xi_get(struct xi_softc *sc) 391 { 392 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 393 struct mbuf *top, **mp, *m; 394 uint16_t pktlen, len, recvcount = 0; 395 uint8_t *data; 396 397 DPRINTF(XID_CONFIG, ("xi_get()\n")); 398 399 PAGE(sc, 0); 400 pktlen = 401 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 402 403 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 404 405 if (pktlen == 0) { 406 /* 407 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 408 * when MPE is set. It is not known why. 409 */ 410 return (0); 411 } 412 413 /* XXX should this be incremented now ? */ 414 recvcount += pktlen; 415 416 MGETHDR(m, M_DONTWAIT, MT_DATA); 417 if (m == NULL) 418 return (recvcount); 419 m_set_rcvif(m, ifp); 420 m->m_pkthdr.len = pktlen; 421 len = MHLEN; 422 top = NULL; 423 mp = ⊤ 424 425 while (pktlen > 0) { 426 if (top) { 427 MGET(m, M_DONTWAIT, MT_DATA); 428 if (m == NULL) { 429 m_freem(top); 430 return (recvcount); 431 } 432 len = MLEN; 433 } 434 if (pktlen >= MINCLSIZE) { 435 MCLGET(m, M_DONTWAIT); 436 if (!(m->m_flags & M_EXT)) { 437 m_freem(m); 438 m_freem(top); 439 return (recvcount); 440 } 441 len = MCLBYTES; 442 } 443 if (top == NULL) { 444 char *newdata = (char *)ALIGN(m->m_data + 445 sizeof(struct ether_header)) - 446 sizeof(struct ether_header); 447 len -= newdata - m->m_data; 448 m->m_data = newdata; 449 } 450 len = uimin(pktlen, len); 451 data = mtod(m, uint8_t *); 452 if (len > 1) { 453 len &= ~1; 454 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 455 (uint16_t *)data, len>>1); 456 } else 457 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 458 m->m_len = len; 459 pktlen -= len; 460 *mp = m; 461 mp = &m->m_next; 462 } 463 464 /* Skip Rx packet. */ 465 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 466 467 if (top == NULL) 468 return recvcount; 469 470 /* Trim the CRC off the end of the packet. */ 471 m_adj(top, -ETHER_CRC_LEN); 472 473 if_percpuq_enqueue(ifp->if_percpuq, top); 474 return (recvcount); 475 } 476 477 /* 478 * Serial management for the MII. 479 * The DELAY's below stem from the fact that the maximum frequency 480 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 481 * go much faster than that. 482 */ 483 484 /* Let the MII serial management be idle for one period. */ 485 static INLINE void xi_mdi_idle(struct xi_softc *); 486 static INLINE void 487 xi_mdi_idle(struct xi_softc *sc) 488 { 489 bus_space_tag_t bst = sc->sc_bst; 490 bus_space_handle_t bsh = sc->sc_bsh; 491 492 /* Drive MDC low... */ 493 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 494 DELAY(1); 495 496 /* and high again. */ 497 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 498 DELAY(1); 499 } 500 501 /* Pulse out one bit of data. */ 502 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 503 static INLINE void 504 xi_mdi_pulse(struct xi_softc *sc, int data) 505 { 506 bus_space_tag_t bst = sc->sc_bst; 507 bus_space_handle_t bsh = sc->sc_bsh; 508 uint8_t bit = data ? MDIO_HIGH : MDIO_LOW; 509 510 /* First latch the data bit MDIO with clock bit MDC low...*/ 511 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 512 DELAY(1); 513 514 /* then raise the clock again, preserving the data bit. */ 515 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 516 DELAY(1); 517 } 518 519 /* Probe one bit of data. */ 520 static INLINE int xi_mdi_probe(struct xi_softc *sc); 521 static INLINE int 522 xi_mdi_probe(struct xi_softc *sc) 523 { 524 bus_space_tag_t bst = sc->sc_bst; 525 bus_space_handle_t bsh = sc->sc_bsh; 526 uint8_t x; 527 528 /* Pull clock bit MDCK low... */ 529 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 530 DELAY(1); 531 532 /* Read data and drive clock high again. */ 533 x = bus_space_read_1(bst, bsh, GP2); 534 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 535 DELAY(1); 536 537 return (x & MDIO); 538 } 539 540 /* Pulse out a sequence of data bits. */ 541 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, uint32_t, int); 542 static INLINE void 543 xi_mdi_pulse_bits(struct xi_softc *sc, uint32_t data, int len) 544 { 545 uint32_t mask; 546 547 for (mask = 1 << (len - 1); mask; mask >>= 1) 548 xi_mdi_pulse(sc, data & mask); 549 } 550 551 /* Read a PHY register. */ 552 STATIC int 553 xi_mdi_read(device_t self, int phy, int reg, uint16_t *val) 554 { 555 struct xi_softc *sc = device_private(self); 556 int i; 557 uint32_t mask; 558 uint16_t data = 0; 559 560 PAGE(sc, 2); 561 for (i = 0; i < 32; i++) /* Synchronize. */ 562 xi_mdi_pulse(sc, 1); 563 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 564 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 565 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 566 xi_mdi_idle(sc); /* Turn around. */ 567 xi_mdi_probe(sc); /* Drop initial zero bit. */ 568 569 for (mask = 1 << 15; mask; mask >>= 1) { 570 if (xi_mdi_probe(sc)) 571 data |= mask; 572 } 573 xi_mdi_idle(sc); 574 575 DPRINTF(XID_MII, 576 ("xi_mdi_read: phy %d reg %d -> %04hx\n", phy, reg, data)); 577 578 *val = data; 579 return 0; 580 } 581 582 /* Write a PHY register. */ 583 STATIC int 584 xi_mdi_write(device_t self, int phy, int reg, uint16_t val) 585 { 586 struct xi_softc *sc = device_private(self); 587 int i; 588 589 PAGE(sc, 2); 590 for (i = 0; i < 32; i++) /* Synchronize. */ 591 xi_mdi_pulse(sc, 1); 592 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 593 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 594 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 595 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 596 xi_mdi_pulse_bits(sc, val, 16); /* Write the data */ 597 xi_mdi_idle(sc); /* Idle away. */ 598 599 DPRINTF(XID_MII, 600 ("xi_mdi_write: phy %d reg %d val %04hx\n", phy, reg, val)); 601 602 return 0; 603 } 604 605 STATIC void 606 xi_statchg(struct ifnet *ifp) 607 { 608 /* XXX Update ifp->if_baudrate */ 609 } 610 611 /* 612 * Change media according to request. 613 */ 614 STATIC int 615 xi_mediachange(struct ifnet *ifp) 616 { 617 int s; 618 619 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 620 621 if (ifp->if_flags & IFF_UP) { 622 s = splnet(); 623 xi_init(ifp->if_softc); 624 splx(s); 625 } 626 return (0); 627 } 628 629 STATIC void 630 xi_reset(struct xi_softc *sc) 631 { 632 int s; 633 634 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 635 636 s = splnet(); 637 xi_stop(sc); 638 xi_init(sc); 639 splx(s); 640 } 641 642 STATIC void 643 xi_watchdog(struct ifnet *ifp) 644 { 645 struct xi_softc *sc = ifp->if_softc; 646 647 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 648 if_statinc(ifp, if_oerrors); 649 650 xi_reset(sc); 651 } 652 653 STATIC void 654 xi_stop(register struct xi_softc *sc) 655 { 656 bus_space_tag_t bst = sc->sc_bst; 657 bus_space_handle_t bsh = sc->sc_bsh; 658 659 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 660 661 PAGE(sc, 0x40); 662 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 663 664 /* Disable interrupts. */ 665 PAGE(sc, 0); 666 bus_space_write_1(bst, bsh, CR, 0); 667 668 PAGE(sc, 1); 669 bus_space_write_1(bst, bsh, IMR0, 0); 670 671 /* Cancel watchdog timer. */ 672 sc->sc_ethercom.ec_if.if_timer = 0; 673 } 674 675 STATIC int 676 xi_enable(struct xi_softc *sc) 677 { 678 int error; 679 680 if (!sc->sc_enabled) { 681 error = (*sc->sc_enable)(sc); 682 if (error) 683 return (error); 684 sc->sc_enabled = 1; 685 xi_full_reset(sc); 686 } 687 return (0); 688 } 689 690 STATIC void 691 xi_disable(struct xi_softc *sc) 692 { 693 694 if (sc->sc_enabled) { 695 sc->sc_enabled = 0; 696 (*sc->sc_disable)(sc); 697 } 698 } 699 700 STATIC void 701 xi_init(struct xi_softc *sc) 702 { 703 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 704 bus_space_tag_t bst = sc->sc_bst; 705 bus_space_handle_t bsh = sc->sc_bsh; 706 707 DPRINTF(XID_CONFIG, ("xi_init()\n")); 708 709 /* Setup the ethernet interrupt mask. */ 710 PAGE(sc, 1); 711 bus_space_write_1(bst, bsh, IMR0, 712 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 713 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 714 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 715 /* XXX What is this? Not for Dingo at least. */ 716 /* Unmask TX underrun detection */ 717 bus_space_write_1(bst, bsh, IMR1, 1); 718 } 719 720 /* Enable interrupts. */ 721 PAGE(sc, 0); 722 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 723 724 xi_set_address(sc); 725 726 PAGE(sc, 0x40); 727 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 728 729 PAGE(sc, 0); 730 731 /* Set current media. */ 732 mii_mediachg(&sc->sc_mii); 733 734 ifp->if_flags |= IFF_RUNNING; 735 ifp->if_flags &= ~IFF_OACTIVE; 736 737 xi_start(ifp); 738 } 739 740 /* 741 * Start outputting on the interface. 742 * Always called as splnet(). 743 */ 744 STATIC void 745 xi_start(struct ifnet *ifp) 746 { 747 struct xi_softc *sc = ifp->if_softc; 748 bus_space_tag_t bst = sc->sc_bst; 749 bus_space_handle_t bsh = sc->sc_bsh; 750 unsigned int s, len, pad = 0; 751 struct mbuf *m0, *m; 752 uint16_t space; 753 754 DPRINTF(XID_CONFIG, ("xi_start()\n")); 755 756 /* Don't transmit if interface is busy or not running. */ 757 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 758 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 759 return; 760 } 761 762 /* Peek at the next packet. */ 763 IFQ_POLL(&ifp->if_snd, m0); 764 if (m0 == 0) 765 return; 766 767 /* We need to use m->m_pkthdr.len, so require the header. */ 768 if (!(m0->m_flags & M_PKTHDR)) 769 panic("xi_start: no header mbuf"); 770 771 len = m0->m_pkthdr.len; 772 773 #if 1 774 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 775 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 776 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 777 #else 778 pad = 0; 779 #endif 780 781 PAGE(sc, 0); 782 783 bus_space_write_2(bst, bsh, TRS, (uint16_t)len + pad + 2); 784 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 785 if (len + pad + 2 > space) { 786 DPRINTF(XID_FIFO, 787 ("xi: not enough space in output FIFO (%d > %d)\n", 788 len + pad + 2, space)); 789 return; 790 } 791 792 IFQ_DEQUEUE(&ifp->if_snd, m0); 793 794 bpf_mtap(ifp, m0, BPF_D_OUT); 795 796 /* 797 * Do the output at splhigh() so that an interrupt from another device 798 * won't cause a FIFO underrun. 799 */ 800 s = splhigh(); 801 802 bus_space_write_2(bst, bsh, EDP, (uint16_t)len + pad); 803 for (m = m0; m; ) { 804 if (m->m_len > 1) 805 bus_space_write_multi_2(bst, bsh, EDP, 806 mtod(m, uint16_t *), m->m_len>>1); 807 if (m->m_len & 1) { 808 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 809 bus_space_write_1(bst, bsh, EDP, 810 *(mtod(m, uint8_t *) + m->m_len - 1)); 811 } 812 m = m0 = m_free(m); 813 } 814 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 815 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 816 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 817 else { 818 for (; pad > 1; pad -= 2) 819 bus_space_write_2(bst, bsh, EDP, 0); 820 if (pad == 1) 821 bus_space_write_1(bst, bsh, EDP, 0); 822 } 823 824 splx(s); 825 826 ifp->if_timer = 5; 827 if_statinc(ifp, if_opackets); 828 } 829 830 STATIC int 831 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 832 { 833 struct ifaddr *ifa = (struct ifaddr *)data; 834 struct xi_softc *sc = ifp->if_softc; 835 int error; 836 837 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 838 839 switch (cmd) { 840 case SIOCINITIFADDR: 841 if ((error = xi_enable(sc)) != 0) 842 break; 843 844 ifp->if_flags |= IFF_UP; 845 846 xi_init(sc); 847 switch (ifa->ifa_addr->sa_family) { 848 #ifdef INET 849 case AF_INET: 850 arp_ifinit(ifp, ifa); 851 break; 852 #endif /* INET */ 853 854 855 default: 856 break; 857 } 858 break; 859 860 default: 861 return (EINVAL); 862 } 863 864 return (0); 865 } 866 867 STATIC int 868 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 869 { 870 struct xi_softc *sc = ifp->if_softc; 871 int s, error = 0; 872 873 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 874 875 s = splnet(); 876 877 switch (cmd) { 878 case SIOCINITIFADDR: 879 error = xi_ether_ioctl(ifp, cmd, data); 880 break; 881 882 case SIOCSIFFLAGS: 883 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 884 break; 885 /* XXX re-use ether_ioctl() */ 886 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 887 case IFF_RUNNING: 888 /* 889 * If interface is marked down and it is running, 890 * stop it. 891 */ 892 xi_stop(sc); 893 ifp->if_flags &= ~IFF_RUNNING; 894 xi_disable(sc); 895 break; 896 case IFF_UP: 897 /* 898 * If interface is marked up and it is stopped, 899 * start it. 900 */ 901 if ((error = xi_enable(sc)) != 0) 902 break; 903 xi_init(sc); 904 break; 905 case IFF_UP | IFF_RUNNING: 906 /* 907 * Reset the interface to pick up changes in any 908 * other flags that affect hardware registers. 909 */ 910 xi_set_address(sc); 911 break; 912 case 0: 913 break; 914 } 915 break; 916 917 case SIOCADDMULTI: 918 case SIOCDELMULTI: 919 if (sc->sc_enabled == 0) { 920 error = EIO; 921 break; 922 } 923 /*FALLTHROUGH*/ 924 default: 925 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 926 /* 927 * Multicast list has changed; set the hardware 928 * filter accordingly. 929 */ 930 if (ifp->if_flags & IFF_RUNNING) 931 xi_set_address(sc); 932 error = 0; 933 } 934 break; 935 } 936 937 splx(s); 938 return (error); 939 } 940 941 STATIC void 942 xi_set_address(struct xi_softc *sc) 943 { 944 bus_space_tag_t bst = sc->sc_bst; 945 bus_space_handle_t bsh = sc->sc_bsh; 946 struct ethercom *ec = &sc->sc_ethercom; 947 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 948 struct ether_multistep step; 949 struct ether_multi *enm; 950 int page, num; 951 int i; 952 uint8_t x; 953 const uint8_t *enaddr; 954 uint8_t indaddr[64]; 955 956 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 957 958 enaddr = (const uint8_t *)CLLADDR(ifp->if_sadl); 959 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 960 for (i = 0; i < 6; i++) 961 indaddr[i] = enaddr[5 - i]; 962 else 963 for (i = 0; i < 6; i++) 964 indaddr[i] = enaddr[i]; 965 num = 1; 966 967 ETHER_LOCK(ec); 968 if (ec->ec_multicnt > 9) { 969 ifp->if_flags |= IFF_ALLMULTI; 970 goto done; 971 } 972 973 ETHER_FIRST_MULTI(step, ec, enm); 974 for (; enm; num++) { 975 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 976 sizeof(enm->enm_addrlo)) != 0) { 977 /* 978 * The multicast address is really a range; 979 * it's easier just to accept all multicasts. 980 * XXX should we be setting IFF_ALLMULTI here? 981 */ 982 ifp->if_flags |= IFF_ALLMULTI; 983 goto done; 984 } 985 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 986 for (i = 0; i < 6; i++) 987 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 988 else 989 for (i = 0; i < 6; i++) 990 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 991 ETHER_NEXT_MULTI(step, enm); 992 } 993 ifp->if_flags &= ~IFF_ALLMULTI; 994 995 done: 996 ETHER_UNLOCK(ec); 997 if (num < 10) 998 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 999 1000 for (page = 0; page < 8; page++) { 1001 #ifdef XIDEBUG 1002 if (xidebug & XID_MCAST) { 1003 printf("page %d before:", page); 1004 for (i = 0; i < 8; i++) 1005 printf(" %02x", indaddr[page * 8 + i]); 1006 printf("\n"); 1007 } 1008 #endif 1009 1010 PAGE(sc, 0x50 + page); 1011 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1012 page == 7 ? 4 : 8); 1013 /* 1014 * XXX 1015 * Without this delay, the address registers on my CE2 get 1016 * trashed the first and I have to cycle it. I have no idea 1017 * why. - mycroft, 2004/08/09 1018 */ 1019 DELAY(50); 1020 1021 #ifdef XIDEBUG 1022 if (xidebug & XID_MCAST) { 1023 bus_space_read_region_1(bst, bsh, IA, 1024 &indaddr[page * 8], page == 7 ? 4 : 8); 1025 printf("page %d after: ", page); 1026 for (i = 0; i < 8; i++) 1027 printf(" %02x", indaddr[page * 8 + i]); 1028 printf("\n"); 1029 } 1030 #endif 1031 } 1032 1033 PAGE(sc, 0x42); 1034 x = SWC1_IND_ADDR; 1035 if (ifp->if_flags & IFF_PROMISC) 1036 x |= SWC1_PROMISC; 1037 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) 1038 x |= SWC1_MCAST_PROM; 1039 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1040 x |= SWC1_AUTO_MEDIA; 1041 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1042 } 1043 1044 STATIC void 1045 xi_cycle_power(struct xi_softc *sc) 1046 { 1047 bus_space_tag_t bst = sc->sc_bst; 1048 bus_space_handle_t bsh = sc->sc_bsh; 1049 1050 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1051 1052 PAGE(sc, 4); 1053 DELAY(1); 1054 bus_space_write_1(bst, bsh, GP1, 0); 1055 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1056 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1057 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1058 else 1059 /* XXX What is bit 2 (aka AIC)? */ 1060 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1061 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1062 } 1063 1064 STATIC void 1065 xi_full_reset(struct xi_softc *sc) 1066 { 1067 bus_space_tag_t bst = sc->sc_bst; 1068 bus_space_handle_t bsh = sc->sc_bsh; 1069 uint8_t x; 1070 1071 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1072 1073 /* Do an as extensive reset as possible on all functions. */ 1074 xi_cycle_power(sc); 1075 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1076 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1077 bus_space_write_1(bst, bsh, CR, 0); 1078 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1079 PAGE(sc, 4); 1080 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1081 /* 1082 * Drive GP1 low to power up ML6692 and GP2 high to power up 1083 * the 10MHz chip. XXX What chip is that? The phy? 1084 */ 1085 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1086 } 1087 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1088 1089 /* Get revision information. XXX Symbolic constants. */ 1090 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1091 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1092 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1093 1094 /* Media selection. XXX Maybe manual overriding too? */ 1095 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1096 /* 1097 * XXX I have no idea what this really does, it is from the 1098 * Linux driver. 1099 */ 1100 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1101 } 1102 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1103 1104 /* 1105 * Disable source insertion. 1106 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1107 */ 1108 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1109 PAGE(sc, 0x42); 1110 bus_space_write_1(bst, bsh, SWC0, 0x20); 1111 } 1112 1113 /* Set the local memory dividing line. */ 1114 if (sc->sc_rev != 1) { 1115 PAGE(sc, 2); 1116 /* XXX Symbolic constant preferrable. */ 1117 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1118 } 1119 1120 /* 1121 * Apparently the receive byte pointer can be bad after a reset, so 1122 * we hardwire it correctly. 1123 */ 1124 PAGE(sc, 0); 1125 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1126 1127 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1128 PAGE(sc, 0x40); 1129 bus_space_write_1(bst, bsh, RX0MSK, 1130 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1131 bus_space_write_1(bst, bsh, TX0MSK, 1132 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1133 SQE | TX_ABORT | TX_OK); 1134 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1135 /* XXX From Linux, dunno what 0xb0 means. */ 1136 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1137 bus_space_write_1(bst, bsh, RXST0, 0); 1138 bus_space_write_1(bst, bsh, TXST0, 0); 1139 bus_space_write_1(bst, bsh, TXST1, 0); 1140 1141 PAGE(sc, 2); 1142 1143 /* Enable MII function if available. */ 1144 x = 0; 1145 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1146 x |= SELECT_MII; 1147 bus_space_write_1(bst, bsh, MSR, x); 1148 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1149 1150 /* Configure the LED registers. */ 1151 /* XXX This is not good for 10base2. */ 1152 bus_space_write_1(bst, bsh, LED, 1153 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1154 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1155 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1156 1157 /* 1158 * The Linux driver says this: 1159 * We should switch back to page 0 to avoid a bug in revision 0 1160 * where regs with offset below 8 can't be read after an access 1161 * to the MAC registers. 1162 */ 1163 PAGE(sc, 0); 1164 } 1165
Indexes created Tue Sep 30 17:09:57 GMT 2025