if_xireg.h revision 1.2
1 /* $NetBSD: if_xireg.h,v 1.2 2001/06/12 15:17:26 wiz Exp $ */ 2 /* OpenBSD: if_xereg.h,v 1.1 1999/05/18 19:18:21 niklas Exp */ 3 4 /* 5 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Niklas Hallqvist, 19 * Brandon Creighton and Job de Haas. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* Additional Card Configuration Registers on Dingo */ 36 37 #define PCMCIA_CCR_DCOR0 0x20 38 #define PCMCIA_CCR_DCOR0_MRST_SFRST 0x80 39 #define PCMCIA_CCR_DCOR0_MRST_SFPWDN 0x40 40 #define PCMCIA_CCR_DCOR0_LED3_SFRST 0x20 41 #define PCMCIA_CCR_DCOR0_LED3_SFPWDN 0x10 42 #define PCMCIA_CCR_DCOR0_BUS 0x08 43 #define PCMCIA_CCR_DCOR0_DECODE 0x04 44 #define PCMCIA_CCR_DCOR0_SFINT 0x01 45 #define PCMCIA_CCR_DCOR1 0x22 46 #define PCMCIA_CCR_DCOR1_SFCSR_WAIT 0xC0 47 #define PCMCIA_CCR_DCOR1_SHADOW_SFIOB 0x20 48 #define PCMCIA_CCR_DCOR1_SHADOW_SFCSR 0x10 49 #define PCMCIA_CCR_DCOR1_FORCE_LEVIREQ 0x08 50 #define PCMCIA_CCR_DCOR1_D6 0x04 51 #define PCMCIA_CCR_DCOR1_SF_STSCHG 0x02 52 #define PCMCIA_CCR_DCOR1_SF_IREQ 0x01 53 #define PCMCIA_CCR_DCOR2 0x24 54 #define PCMCIA_CCR_DCOR2_SHADOW_SFCOR 0x10 55 #define PCMCIA_CCR_DCOR2_SMEM_BASE 0x0F 56 #define PCMCIA_CCR_DCOR3 0x26 57 #define PCMCIA_CCR_DCOR4 0x28 58 #define PCMCIA_CCR_SFCOR 0x40 59 #define PCMCIA_CCR_SFCOR_SRESET 0x80 60 #define PCMCIA_CCR_SFCOR_LEVIREQ 0x40 61 #define PCMCIA_CCR_SFCOR_IRQ_STSCHG 0x20 62 #define PCMCIA_CCR_SFCOR_CFINDEX 0x18 63 #define PCMCIA_CCR_SFCOR_IREQ_ENABLE 0x04 64 #define PCMCIA_CCR_SFCOR_ADDR_DECODE 0x02 65 #define PCMCIA_CCR_SFCOR_FUNC_ENABLE 0x01 66 #define PCMCIA_CCR_SFCSR 0x42 67 #define PCMCIA_CCR_SFCSR_IOIS8 0x20 68 #define PCMCIA_CCR_SFCSR_AUDIO 0x08 69 #define PCMCIA_CCR_SFCSR_PWRDWN 0x04 70 #define PCMCIA_CCR_SFCSR_INTR 0x02 71 #define PCMCIA_CCR_SFCSR_INTRACK 0x01 72 #define PCMCIA_CCR_SFIOBASE0 0x4A 73 #define PCMCIA_CCR_SFIOBASE1 0x4C 74 #define PCMCIA_CCR_SFILR 0x52 75 76 #define PCMCIA_CCR_SIZE_DINGO 0x54 77 78 /* All pages */ 79 #define CR 0x0 /* W - Command register */ 80 #define ESR 0x0 /* R - Ethernet status register */ 81 #define PR 0x1 /* RW - Page register select */ 82 #define EDP 0x2 /* RW - Ethernet data port, 4 registers */ 83 #define ISR0 0x6 /* R - Etherenet interrupt status register */ 84 #define GIR 0x7 /* RW - Global interrupt register */ 85 #define PTR 0xd /* R - Packets Transmitted register */ 86 87 /* Page 0 */ 88 #define TSO0 0x8 /* R - Transmit space open, 3 registers */ 89 #define TSO1 0x9 90 #define TSO2 0xa 91 #define DO0 0xc /* W - Data offset, 2 registers */ 92 #define DO1 0xd 93 #define RSR 0xc /* R - Rx status register */ 94 #define TPR 0xd /* R - Tx packets register */ 95 #define RBC0 0xe /* R - Rx byte count, 2 registers */ 96 #define RBC1 0xf 97 98 /* Page 1 */ 99 #define IMR0 0xc /* RW - Interrupt mask, 2 registers */ 100 #define IMR1 0xd 101 #define ECR 0xe /* RW - Ethernet config register */ 102 103 /* Page 2 */ 104 #define RBS0 0x8 /* RW - Receive buffer start, 2 registers */ 105 #define RBS1 0x9 106 #define LED 0xa /* RW - LED control register */ 107 #define LED3 0xb /* RW - LED3 control register */ 108 #define MSR 0xc /* RW - Misc. setup register */ 109 #define GP2 0xd /* RW - General purpose register 2 */ 110 111 /* Page 3 */ 112 #define TPT0 0xa /* RW - Tx packet threshold, 2 registers */ 113 #define TPT1 0xb 114 115 /* Page 4 */ 116 #define GP0 0x8 /* RW - General purpose register 0 */ 117 #define GP1 0x9 /* RW - General purpose register 1 */ 118 #define BV 0xa /* R - Bonding version register */ 119 #define EES 0xb /* RW - EEPROM control register */ 120 121 /* Page 5 */ 122 #define RHSA0 0xa /* RX host start address */ 123 124 /* Page 6 */ 125 126 /* Page 7 */ 127 128 /* Page 8 */ 129 130 /* Page 16 */ 131 132 /* Page 0x40 */ 133 #define CMD0 0x8 /* W - Receive status register */ 134 #define RXST0 0x9 /* RW - Receive status register */ 135 #define TXST0 0xb /* RW - Transmit status, 2 registers */ 136 #define TXST1 0xc 137 #define RX0MSK 0xd /* RW - Receive status mask register */ 138 #define TX0MSK 0xe /* RW - Transmit status mask, 2 registers */ 139 #define TX1MSK 0xf /* RW - Dingo does not define this register */ 140 141 /* Page 0x42 */ 142 #define SWC0 0x8 /* RW - Software configuration, 2 registers */ 143 #define SWC1 0x9 144 145 /* Page 0x50-0x57 */ 146 #define IA 0x8 /* RW - Individual address */ 147 148 /* CR register bits */ 149 #define TX_PKT 0x01 /* Transmit packet. */ 150 #define SOFT_RESET 0x02 /* Software reset. */ 151 #define ENABLE_INT 0x04 /* Enable interrupt. */ 152 #define FORCE_INT 0x08 /* Force interrupt. */ 153 #define CLR_TX_FIFO 0x10 /* Clear transmit FIFO. */ 154 #define CLR_RX_OVERRUN 0x20 /* Clear receive overrun. */ 155 #define RESTART_TX 0x40 /* Restart transmit process. */ 156 157 /* ESR register bits */ 158 #define FULL_PKT_RCV 0x01 /* Full packet received. */ 159 #define PKT_REJECTED 0x04 /* A packet was rejected. */ 160 #define TX_PKT_PEND 0x08 /* TX Packet Pending. */ 161 #define INCOR_POLARITY 0x10 /* XXX from linux driver, but not used there */ 162 #define MEDIA_SELECT 0x20 /* set if TP, clear if AUI */ 163 164 /* DO register bits */ 165 #define DO_OFF_MASK 0x1fff /* Mask for offset value. */ 166 #define DO_CHG_OFFSET 0x2000 /* Change offset command. */ 167 #define DO_SHM_MODE 0x4000 /* Shared memory mode. */ 168 #define DO_SKIP_RX_PKT 0x8000 /* Skip Rx packet. */ 169 170 /* RBC register bits */ 171 #define RBC_COUNT_MASK 0x1fff /* Mask for byte count. */ 172 #define RBC_RX_FULL 0x2000 /* Receive full packet. */ 173 #define RBC_RX_PARTIAL 0x4000 /* Receive partial packet. */ 174 #define RBC_RX_PKT_REJ 0x8000 /* Receive packet rejected. */ 175 176 /* ISR0(/IMR0) register bits */ 177 #define ISR_TX_OFLOW 0x01 /* Transmit buffer overflow. */ 178 #define ISR_PKT_TX 0x02 /* Packet transmitted. */ 179 #define ISR_MAC_INT 0x04 /* MAC interrupt. */ 180 #define ISR_RX_EARLY 0x10 /* Receive early packet. */ 181 #define ISR_RX_FULL 0x20 /* Receive full packet. */ 182 #define ISR_RX_PKT_REJ 0x40 /* Receive packet rejected. */ 183 #define ISR_FORCED_INT 0x80 /* Forced interrupt. */ 184 185 /* ECR register bits */ 186 #define ECR_EARLY_TX 0x01 /* Early transmit mode. */ 187 #define ECR_EARLY_RX 0x02 /* Early receive mode. */ 188 #define ECR_FULL_DUPLEX 0x04 /* Full duplex select. */ 189 #define ECR_LNK_PLS_DIS 0x20 /* Link pulse disable. */ 190 #define ECR_SW_COMPAT 0x80 /* Software compatibility switch. */ 191 192 /* GP0 register bits */ 193 #define GP1_WR 0x01 /* GP1 pin output value. */ 194 #define GP2_WR 0x02 /* GP2 pin output value. */ 195 #define GP1_OUT 0x04 /* GP1 pin output select. */ 196 #define GP2_OUT 0x08 /* GP2 pin output select. */ 197 #define GP1_RD 0x10 /* GP1 pin input value. */ 198 #define GP2_RD 0x20 /* GP2 pin input value. */ 199 200 /* GP1 register bits */ 201 #define POWER_UP 0x01 /* When 0, power down analogue part of chip. */ 202 203 /* LED register bits */ 204 #define LED0_SHIFT 0 /* LED0 Output shift & mask */ 205 #define LED0_MASK 0x7 206 #define LED1_SHIFT 3 /* LED1 Output shift & mask */ 207 #define LED1_MASK 0x38 208 #define LED0_RX_ENA 0x40 /* LED0 - receive enable */ 209 #define LED1_RX_ENA 0x80 /* LED1 - receive enable */ 210 211 /* LED3 register bits */ 212 #define LED3_SHIFT 0 /* LED0 output shift & mask */ 213 #define LED3_MASK 0x7 214 #define LED3_RX_ENA 0x40 /* LED0 - receive enable */ 215 216 /* LED output values */ 217 #define LED_DISABLE 0 /* LED disabled */ 218 #define LED_COLL_ACT 1 /* Collision activity */ 219 #define LED_COLL_INACT 2 /* (NOT) Collision activity */ 220 #define LED_10MB_LINK 3 /* 10 Mb link detected */ 221 #define LED_100MB_LINK 4 /* 100 Mb link detected */ 222 #define LED_LINK 5 /* 10 Mb or 100 Mb link detected */ 223 #define LED_AUTO 6 /* Automatic assertion */ 224 #define LED_TX_ACT 7 /* Transmit activity */ 225 226 /* MSR register bits */ 227 #define SRAM_128K_EXT 0x01 /* 128K SRAM extension */ 228 #define RBS_BIT16 0x02 /* RBS bit 16 */ 229 #define SELECT_MII 0x08 /* Select MII */ 230 #define HASH_TBL_ENA 0x20 /* Hash table enable */ 231 232 /* GP2 register bits */ 233 #define GP3_WR 0x01 /* GP3 pin output value. */ 234 #define GP4_WR 0x02 /* GP4 pin output value. */ 235 #define GP3_OUT 0x04 /* GP3 pin output select. */ 236 #define GP4_OUT 0x08 /* GP4 pin output select. */ 237 #define GP3_RD 0x10 /* GP3 pin input value. */ 238 #define GP4_RD 0x20 /* GP4 pin input value. */ 239 240 /* RSR register bits */ 241 #define RSR_NOTMCAST 0x01 /* clear when multicast packet */ 242 #define RSR_BCAST 0x02 /* set when broadcast packet */ 243 #define RSR_TOO_LONG 0x04 /* set if packet is longer than 1518 octets */ 244 #define RSR_ALIGNERR 0x10 /* incorrect CRC and last octet not complete */ 245 #define RSR_CRCERR 0x20 /* incorrect CRC and last octet complete */ 246 #define RSR_RX_OK 0x80 /* packet received okay */ 247 248 /* CMD0 register bits */ 249 #define ONLINE 0x04 /* Online */ 250 #define OFFLINE 0x08 /* Online */ 251 #define ENABLE_RX 0x20 /* Enable receiver */ 252 #define DISABLE_RX 0x80 /* Disable receiver */ 253 254 /* RX0Msk register bits */ 255 #define PKT_TOO_LONG 0x02 /* Packet too long mask. */ 256 #define CRC_ERR 0x08 /* CRC error mask. */ 257 #define RX_OVERRUN 0x10 /* Receive overrun mask. */ 258 #define RX_ABORT 0x40 /* Receive abort mask. */ 259 #define RX_OK 0x80 /* Receive OK mask. */ 260 261 /* TX0Msk register bits */ 262 #define CARRIER_LOST 0x01 /* Carrier sense lost. */ 263 #define EXCESSIVE_COLL 0x02 /* Excessive collisions mask. */ 264 #define TX_UNDERRUN 0x08 /* Transmit underrun mask. */ 265 #define LATE_COLLISION 0x10 /* Late collision mask. */ 266 #define SQE 0x20 /* Signal quality error mask.. */ 267 #define TX_ABORT 0x40 /* Transmit abort mask. */ 268 #define TX_OK 0x80 /* Transmit OK mask. */ 269 270 /* SWC1 register bits */ 271 #define SWC1_IND_ADDR 0x01 /* Individual address enable. */ 272 #define SWC1_MCAST_PROM 0x02 /* Multicast promiscuous enable. */ 273 #define SWC1_PROMISC 0x04 /* Promiscuous mode enable. */ 274 #define SWC1_BCAST_DIS 0x08 /* Broadcast disable. */ 275 #define SWC1_MEDIA_SEL 0x40 /* Media select (Mohawk). */ 276 #define SWC1_AUTO_MEDIA 0x80 /* Automatic media select (Mohawk). */ 277 278 /* Misc. defines. */ 279 280 #define PAGE(sc, page) \ 281 bus_space_write_1((sc->sc_bst), (sc->sc_bsh), (sc->sc_offset) + PR, (page)) 282 283 /* 284 * GP3 is connected to the MDC pin of the NS DP83840A PHY, GP4 is 285 * connected to the MDIO pin. These are utility macros to enhance 286 * readability of the code. 287 */ 288 #define MDC_LOW GP3_OUT 289 #define MDC_HIGH (GP3_OUT | GP3_WR) 290 #define MDIO_LOW GP4_OUT 291 #define MDIO_HIGH (GP4_OUT | GP4_WR) 292 #define MDIO GP4_RD 293 294 /* Values found in MANFID. */ 295 #define XIMEDIA_ETHER 0x01 296 #define XIMEDIA_TOKEN 0x02 297 #define XIMEDIA_ARC 0x04 298 #define XIMEDIA_WIRELESS 0x08 299 #define XIMEDIA_MODEM 0x10 300 #define XIMEDIA_GSM 0x20 301 302 #define XIPROD_IDMASK 0x0f 303 #define XIPROD_POCKET 0x10 304 #define XIPROD_EXTERNAL 0x20 305 #define XIPROD_CREDITCARD 0x40 306 #define XIPROD_CARDBUS 0x80 307
Indexes created Tue Sep 30 20:09:53 GMT 2025