hcsc.c revision 1.18
1 /* $NetBSD: hcsc.c,v 1.18 2008/04/04 16:00:58 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 * 72 * Andy Armstrong gives some details of the HCCS SCSI cards at 73 * <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.18 2008/04/04 16:00:58 tsutsui Exp $"); 78 79 #include <sys/param.h> 80 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/buf.h> 85 #include <dev/scsipi/scsi_all.h> 86 #include <dev/scsipi/scsipi_all.h> 87 #include <dev/scsipi/scsiconf.h> 88 89 #include <dev/ic/ncr5380reg.h> 90 #include <dev/ic/ncr5380var.h> 91 92 #include <machine/bootconfig.h> 93 94 #include <dev/podulebus/podulebus.h> 95 #include <dev/podulebus/podules.h> 96 #include <dev/podulebus/powerromreg.h> 97 98 #include <dev/podulebus/hcscreg.h> 99 100 int hcsc_match(device_t, cfdata_t, void *); 101 void hcsc_attach(device_t, device_t, void *); 102 103 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, uint8_t *); 104 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, uint8_t *); 105 106 107 /* 108 * HCCS 8-bit SCSI softc structure. 109 * 110 * Contains the generic ncr5380 device node, podule information and 111 * global information required by the driver. 112 */ 113 114 struct hcsc_softc { 115 struct ncr5380_softc sc_ncr5380; 116 bus_space_tag_t sc_pdmat; 117 bus_space_handle_t sc_pdmah; 118 void *sc_ih; 119 struct evcnt sc_intrcnt; 120 }; 121 122 CFATTACH_DECL_NEW(hcsc, sizeof(struct hcsc_softc), 123 hcsc_match, hcsc_attach, NULL, NULL); 124 125 /* 126 * Card probe function 127 * 128 * Just match the manufacturer and podule ID's 129 */ 130 131 int 132 hcsc_match(device_t parent, cfdata_t cf, void *aux) 133 { 134 struct podulebus_attach_args *pa = aux; 135 136 /* Normal ROM */ 137 if (pa->pa_product == PODULE_HCCS_IDESCSI && 138 strncmp(pa->pa_descr, "SCSI", 4) == 0) 139 return 1; 140 /* PowerROM */ 141 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 142 podulebus_initloader(pa) == 0 && 143 podloader_callloader(pa, 0, 0) == PRID_HCCS_SCSI1) 144 return 1; 145 return 0; 146 } 147 148 /* 149 * Card attach function 150 * 151 */ 152 153 void 154 hcsc_attach(device_t parent, device_t self, void *aux) 155 { 156 struct hcsc_softc *sc = device_private(self); 157 struct ncr5380_softc *ncr_sc = &sc->sc_ncr5380; 158 struct podulebus_attach_args *pa = aux; 159 #ifndef NCR5380_USE_BUS_SPACE 160 uint8_t *iobase; 161 #endif 162 char hi_option[sizeof(self->dv_xname) + 8]; 163 164 ncr_sc->sc_dev = self; 165 ncr_sc->sc_min_dma_len = 0; 166 ncr_sc->sc_no_disconnect = 0; 167 ncr_sc->sc_parity_disable = 0; 168 169 ncr_sc->sc_dma_alloc = NULL; 170 ncr_sc->sc_dma_free = NULL; 171 ncr_sc->sc_dma_poll = NULL; 172 ncr_sc->sc_dma_setup = NULL; 173 ncr_sc->sc_dma_start = NULL; 174 ncr_sc->sc_dma_eop = NULL; 175 ncr_sc->sc_dma_stop = NULL; 176 ncr_sc->sc_intr_on = NULL; 177 ncr_sc->sc_intr_off = NULL; 178 179 #ifdef NCR5380_USE_BUS_SPACE 180 ncr_sc->sc_regt = pa->pa_fast_t; 181 bus_space_map(ncr_sc->sc_regt, 182 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 183 &ncr_sc->sc_regh); 184 ncr_sc->sci_r0 = 0; 185 ncr_sc->sci_r1 = 1; 186 ncr_sc->sci_r2 = 2; 187 ncr_sc->sci_r3 = 3; 188 ncr_sc->sci_r4 = 4; 189 ncr_sc->sci_r5 = 5; 190 ncr_sc->sci_r6 = 6; 191 ncr_sc->sci_r7 = 7; 192 #else 193 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 194 ncr_sc->sci_r0 = iobase + 0; 195 ncr_sc->sci_r1 = iobase + 4; 196 ncr_sc->sci_r2 = iobase + 8; 197 ncr_sc->sci_r3 = iobase + 12; 198 ncr_sc->sci_r4 = iobase + 16; 199 ncr_sc->sci_r5 = iobase + 20; 200 ncr_sc->sci_r6 = iobase + 24; 201 ncr_sc->sci_r7 = iobase + 28; 202 #endif 203 sc->sc_pdmat = pa->pa_mod_t; 204 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 205 &sc->sc_pdmah); 206 207 ncr_sc->sc_rev = NCR_VARIANT_DP8490; 208 209 ncr_sc->sc_pio_in = hcsc_pdma_in; 210 ncr_sc->sc_pio_out = hcsc_pdma_out; 211 212 /* Provide an override for the host id */ 213 ncr_sc->sc_channel.chan_id = 7; 214 snprintf(hi_option, sizeof(hi_option), "%s.hostid", 215 device_xname(self)); 216 (void)get_bootconf_option(boot_args, hi_option, 217 BOOTOPT_TYPE_INT, &ncr_sc->sc_channel.chan_id); 218 ncr_sc->sc_adapter.adapt_minphys = minphys; 219 220 aprint_normal(": host ID %d\n", ncr_sc->sc_channel.chan_id); 221 222 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 223 device_xname(self), "intr"); 224 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 225 sc, &sc->sc_intrcnt); 226 227 ncr5380_attach(ncr_sc); 228 } 229 230 #ifndef HCSC_TSIZE_OUT 231 #define HCSC_TSIZE_OUT 512 232 #endif 233 234 #ifndef HCSC_TSIZE_IN 235 #define HCSC_TSIZE_IN 512 236 #endif 237 238 #define TIMEOUT 1000000 239 240 static inline int 241 hcsc_ready(struct ncr5380_softc *sc) 242 { 243 int i; 244 245 for (i = TIMEOUT; i > 0; i--) { 246 if ((NCR5380_READ(sc,sci_csr) & 247 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 248 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 249 return 1; 250 251 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 252 SCI_BUSY(sc) == 0) 253 return 0; 254 } 255 printf("%s: ready timeout\n", device_xname(sc->sc_dev)); 256 return 0; 257 } 258 259 260 261 /* Return zero on success. */ 262 static inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 263 { 264 int timo; 265 266 for (timo = TIMEOUT; timo; timo--) { 267 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 268 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 269 SCI_BUSY(sc) == 0) { 270 return; 271 } 272 } 273 printf("%s: pdma not_req timeout\n", device_xname(sc->sc_dev)); 274 } 275 276 static int 277 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 278 uint8_t *data) 279 { 280 struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc; 281 bus_space_tag_t pdmat = sc->sc_pdmat; 282 bus_space_handle_t pdmah = sc->sc_pdmah; 283 int s, resid, len; 284 285 s = splbio(); 286 287 NCR5380_WRITE(ncr_sc, sci_mode, 288 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 289 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 290 291 resid = datalen; 292 while (resid > 0) { 293 len = min(resid, HCSC_TSIZE_IN); 294 if (hcsc_ready(ncr_sc) == 0) 295 goto interrupt; 296 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 297 data += len; 298 resid -= len; 299 } 300 301 hcsc_wait_not_req(ncr_sc); 302 303 interrupt: 304 SCI_CLR_INTR(ncr_sc); 305 NCR5380_WRITE(ncr_sc, sci_mode, 306 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 307 splx(s); 308 return datalen - resid; 309 } 310 311 static int 312 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 313 uint8_t *data) 314 { 315 struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc; 316 bus_space_tag_t pdmat = sc->sc_pdmat; 317 bus_space_handle_t pdmah = sc->sc_pdmah; 318 int i, s, icmd, resid; 319 320 s = splbio(); 321 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 322 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 323 NCR5380_WRITE(ncr_sc, sci_mode, 324 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 325 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 326 327 resid = datalen; 328 if (hcsc_ready(ncr_sc) == 0) 329 goto interrupt; 330 331 if (resid > HCSC_TSIZE_OUT) { 332 /* 333 * Because of the chips DMA prefetch, phase changes 334 * etc, won't be detected until we have written at 335 * least one byte more. We pre-write 4 bytes so 336 * subsequent transfers will be aligned to a 4 byte 337 * boundary. Assuming disconects will only occur on 338 * block boundaries, we then correct for the pre-write 339 * when and if we get a phase change. If the chip had 340 * DMA byte counting hardware, the assumption would not 341 * be necessary. 342 */ 343 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 344 data += 4; 345 resid -= 4; 346 347 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 348 if (hcsc_ready(ncr_sc) == 0) { 349 resid += 4; /* Overshot */ 350 goto interrupt; 351 } 352 bus_space_write_multi_1(pdmat, pdmah, 0, data, 353 HCSC_TSIZE_OUT); 354 data += HCSC_TSIZE_OUT; 355 } 356 if (hcsc_ready(ncr_sc) == 0) { 357 resid += 4; /* Overshot */ 358 goto interrupt; 359 } 360 } 361 362 if (resid) { 363 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 364 resid = 0; 365 } 366 for (i = TIMEOUT; i > 0; i--) { 367 if ((NCR5380_READ(ncr_sc, sci_csr) 368 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 369 != SCI_CSR_DREQ) 370 break; 371 } 372 if (i != 0) 373 bus_space_write_1(pdmat, pdmah, 0, 0); 374 else 375 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 376 device_xname(ncr_sc->sc_dev)); 377 378 hcsc_wait_not_req(ncr_sc); 379 interrupt: 380 SCI_CLR_INTR(ncr_sc); 381 NCR5380_WRITE(ncr_sc, sci_mode, 382 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 383 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 384 splx(s); 385 return datalen - resid; 386 } 387
Indexes created Tue Sep 30 20:09:53 GMT 2025