hcsc.c revision 1.19
1 /* $NetBSD: hcsc.c,v 1.19 2008/04/28 20:23:56 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Copyright (c) 1996, 1997 Matthias Pfaller. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by Matthias Pfaller. 47 * 4. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 51 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 55 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 59 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 64 * 65 * Andy Armstrong gives some details of the HCCS SCSI cards at 66 * <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.19 2008/04/28 20:23:56 martin Exp $"); 71 72 #include <sys/param.h> 73 74 #include <sys/systm.h> 75 #include <sys/kernel.h> 76 #include <sys/device.h> 77 #include <sys/buf.h> 78 #include <dev/scsipi/scsi_all.h> 79 #include <dev/scsipi/scsipi_all.h> 80 #include <dev/scsipi/scsiconf.h> 81 82 #include <dev/ic/ncr5380reg.h> 83 #include <dev/ic/ncr5380var.h> 84 85 #include <machine/bootconfig.h> 86 87 #include <dev/podulebus/podulebus.h> 88 #include <dev/podulebus/podules.h> 89 #include <dev/podulebus/powerromreg.h> 90 91 #include <dev/podulebus/hcscreg.h> 92 93 int hcsc_match(device_t, cfdata_t, void *); 94 void hcsc_attach(device_t, device_t, void *); 95 96 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, uint8_t *); 97 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, uint8_t *); 98 99 100 /* 101 * HCCS 8-bit SCSI softc structure. 102 * 103 * Contains the generic ncr5380 device node, podule information and 104 * global information required by the driver. 105 */ 106 107 struct hcsc_softc { 108 struct ncr5380_softc sc_ncr5380; 109 bus_space_tag_t sc_pdmat; 110 bus_space_handle_t sc_pdmah; 111 void *sc_ih; 112 struct evcnt sc_intrcnt; 113 }; 114 115 CFATTACH_DECL_NEW(hcsc, sizeof(struct hcsc_softc), 116 hcsc_match, hcsc_attach, NULL, NULL); 117 118 /* 119 * Card probe function 120 * 121 * Just match the manufacturer and podule ID's 122 */ 123 124 int 125 hcsc_match(device_t parent, cfdata_t cf, void *aux) 126 { 127 struct podulebus_attach_args *pa = aux; 128 129 /* Normal ROM */ 130 if (pa->pa_product == PODULE_HCCS_IDESCSI && 131 strncmp(pa->pa_descr, "SCSI", 4) == 0) 132 return 1; 133 /* PowerROM */ 134 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 135 podulebus_initloader(pa) == 0 && 136 podloader_callloader(pa, 0, 0) == PRID_HCCS_SCSI1) 137 return 1; 138 return 0; 139 } 140 141 /* 142 * Card attach function 143 * 144 */ 145 146 void 147 hcsc_attach(device_t parent, device_t self, void *aux) 148 { 149 struct hcsc_softc *sc = device_private(self); 150 struct ncr5380_softc *ncr_sc = &sc->sc_ncr5380; 151 struct podulebus_attach_args *pa = aux; 152 #ifndef NCR5380_USE_BUS_SPACE 153 uint8_t *iobase; 154 #endif 155 char hi_option[sizeof(self->dv_xname) + 8]; 156 157 ncr_sc->sc_dev = self; 158 ncr_sc->sc_min_dma_len = 0; 159 ncr_sc->sc_no_disconnect = 0; 160 ncr_sc->sc_parity_disable = 0; 161 162 ncr_sc->sc_dma_alloc = NULL; 163 ncr_sc->sc_dma_free = NULL; 164 ncr_sc->sc_dma_poll = NULL; 165 ncr_sc->sc_dma_setup = NULL; 166 ncr_sc->sc_dma_start = NULL; 167 ncr_sc->sc_dma_eop = NULL; 168 ncr_sc->sc_dma_stop = NULL; 169 ncr_sc->sc_intr_on = NULL; 170 ncr_sc->sc_intr_off = NULL; 171 172 #ifdef NCR5380_USE_BUS_SPACE 173 ncr_sc->sc_regt = pa->pa_fast_t; 174 bus_space_map(ncr_sc->sc_regt, 175 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 176 &ncr_sc->sc_regh); 177 ncr_sc->sci_r0 = 0; 178 ncr_sc->sci_r1 = 1; 179 ncr_sc->sci_r2 = 2; 180 ncr_sc->sci_r3 = 3; 181 ncr_sc->sci_r4 = 4; 182 ncr_sc->sci_r5 = 5; 183 ncr_sc->sci_r6 = 6; 184 ncr_sc->sci_r7 = 7; 185 #else 186 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 187 ncr_sc->sci_r0 = iobase + 0; 188 ncr_sc->sci_r1 = iobase + 4; 189 ncr_sc->sci_r2 = iobase + 8; 190 ncr_sc->sci_r3 = iobase + 12; 191 ncr_sc->sci_r4 = iobase + 16; 192 ncr_sc->sci_r5 = iobase + 20; 193 ncr_sc->sci_r6 = iobase + 24; 194 ncr_sc->sci_r7 = iobase + 28; 195 #endif 196 sc->sc_pdmat = pa->pa_mod_t; 197 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 198 &sc->sc_pdmah); 199 200 ncr_sc->sc_rev = NCR_VARIANT_DP8490; 201 202 ncr_sc->sc_pio_in = hcsc_pdma_in; 203 ncr_sc->sc_pio_out = hcsc_pdma_out; 204 205 /* Provide an override for the host id */ 206 ncr_sc->sc_channel.chan_id = 7; 207 snprintf(hi_option, sizeof(hi_option), "%s.hostid", 208 device_xname(self)); 209 (void)get_bootconf_option(boot_args, hi_option, 210 BOOTOPT_TYPE_INT, &ncr_sc->sc_channel.chan_id); 211 ncr_sc->sc_adapter.adapt_minphys = minphys; 212 213 aprint_normal(": host ID %d\n", ncr_sc->sc_channel.chan_id); 214 215 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 216 device_xname(self), "intr"); 217 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 218 sc, &sc->sc_intrcnt); 219 220 ncr5380_attach(ncr_sc); 221 } 222 223 #ifndef HCSC_TSIZE_OUT 224 #define HCSC_TSIZE_OUT 512 225 #endif 226 227 #ifndef HCSC_TSIZE_IN 228 #define HCSC_TSIZE_IN 512 229 #endif 230 231 #define TIMEOUT 1000000 232 233 static inline int 234 hcsc_ready(struct ncr5380_softc *sc) 235 { 236 int i; 237 238 for (i = TIMEOUT; i > 0; i--) { 239 if ((NCR5380_READ(sc,sci_csr) & 240 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 241 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 242 return 1; 243 244 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 245 SCI_BUSY(sc) == 0) 246 return 0; 247 } 248 printf("%s: ready timeout\n", device_xname(sc->sc_dev)); 249 return 0; 250 } 251 252 253 254 /* Return zero on success. */ 255 static inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 256 { 257 int timo; 258 259 for (timo = TIMEOUT; timo; timo--) { 260 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 261 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 262 SCI_BUSY(sc) == 0) { 263 return; 264 } 265 } 266 printf("%s: pdma not_req timeout\n", device_xname(sc->sc_dev)); 267 } 268 269 static int 270 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 271 uint8_t *data) 272 { 273 struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc; 274 bus_space_tag_t pdmat = sc->sc_pdmat; 275 bus_space_handle_t pdmah = sc->sc_pdmah; 276 int s, resid, len; 277 278 s = splbio(); 279 280 NCR5380_WRITE(ncr_sc, sci_mode, 281 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 282 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 283 284 resid = datalen; 285 while (resid > 0) { 286 len = min(resid, HCSC_TSIZE_IN); 287 if (hcsc_ready(ncr_sc) == 0) 288 goto interrupt; 289 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 290 data += len; 291 resid -= len; 292 } 293 294 hcsc_wait_not_req(ncr_sc); 295 296 interrupt: 297 SCI_CLR_INTR(ncr_sc); 298 NCR5380_WRITE(ncr_sc, sci_mode, 299 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 300 splx(s); 301 return datalen - resid; 302 } 303 304 static int 305 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 306 uint8_t *data) 307 { 308 struct hcsc_softc *sc = (struct hcsc_softc *)ncr_sc; 309 bus_space_tag_t pdmat = sc->sc_pdmat; 310 bus_space_handle_t pdmah = sc->sc_pdmah; 311 int i, s, icmd, resid; 312 313 s = splbio(); 314 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 315 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 316 NCR5380_WRITE(ncr_sc, sci_mode, 317 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 318 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 319 320 resid = datalen; 321 if (hcsc_ready(ncr_sc) == 0) 322 goto interrupt; 323 324 if (resid > HCSC_TSIZE_OUT) { 325 /* 326 * Because of the chips DMA prefetch, phase changes 327 * etc, won't be detected until we have written at 328 * least one byte more. We pre-write 4 bytes so 329 * subsequent transfers will be aligned to a 4 byte 330 * boundary. Assuming disconects will only occur on 331 * block boundaries, we then correct for the pre-write 332 * when and if we get a phase change. If the chip had 333 * DMA byte counting hardware, the assumption would not 334 * be necessary. 335 */ 336 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 337 data += 4; 338 resid -= 4; 339 340 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 341 if (hcsc_ready(ncr_sc) == 0) { 342 resid += 4; /* Overshot */ 343 goto interrupt; 344 } 345 bus_space_write_multi_1(pdmat, pdmah, 0, data, 346 HCSC_TSIZE_OUT); 347 data += HCSC_TSIZE_OUT; 348 } 349 if (hcsc_ready(ncr_sc) == 0) { 350 resid += 4; /* Overshot */ 351 goto interrupt; 352 } 353 } 354 355 if (resid) { 356 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 357 resid = 0; 358 } 359 for (i = TIMEOUT; i > 0; i--) { 360 if ((NCR5380_READ(ncr_sc, sci_csr) 361 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 362 != SCI_CSR_DREQ) 363 break; 364 } 365 if (i != 0) 366 bus_space_write_1(pdmat, pdmah, 0, 0); 367 else 368 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 369 device_xname(ncr_sc->sc_dev)); 370 371 hcsc_wait_not_req(ncr_sc); 372 interrupt: 373 SCI_CLR_INTR(ncr_sc); 374 NCR5380_WRITE(ncr_sc, sci_mode, 375 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 376 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 377 splx(s); 378 return datalen - resid; 379 } 380
Indexes created Thu Oct 02 10:09:58 GMT 2025