hcsc.c revision 1.3
1 /* $NetBSD: hcsc.c,v 1.3 2001/06/02 11:43:40 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 */ 72 73 #include <sys/param.h> 74 75 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.3 2001/06/02 11:43:40 bjh21 Exp $"); 76 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/buf.h> 81 #include <dev/scsipi/scsi_all.h> 82 #include <dev/scsipi/scsipi_all.h> 83 #include <dev/scsipi/scsiconf.h> 84 85 #include <dev/ic/ncr5380reg.h> 86 #include <dev/ic/ncr5380var.h> 87 88 #include <machine/bootconfig.h> 89 90 #include <dev/podulebus/podulebus.h> 91 #include <dev/podulebus/podules.h> 92 93 void hcsc_attach (struct device *, struct device *, void *); 94 int hcsc_match (struct device *, struct cfdata *, void *); 95 96 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *); 97 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *); 98 99 100 /* 101 * HCCS 8-bit SCSI softc structure. 102 * 103 * Contains the generic ncr5380 device node, podule information and 104 * global information required by the driver. 105 */ 106 107 struct hcsc_softc { 108 struct ncr5380_softc sc_ncr5380; 109 bus_space_tag_t sc_pdmat; 110 bus_space_handle_t sc_pdmah; 111 void *sc_ih; 112 struct evcnt sc_intrcnt; 113 }; 114 115 struct cfattach hcsc_ca = { 116 sizeof(struct hcsc_softc), hcsc_match, hcsc_attach 117 }; 118 119 /* 120 * Card probe function 121 * 122 * Just match the manufacturer and podule ID's 123 */ 124 125 int 126 hcsc_match(struct device *parent, struct cfdata *cf, void *aux) 127 { 128 struct podulebus_attach_args *pa = aux; 129 130 if (matchpodule(pa, MANUFACTURER_HCCS, PODULE_HCCS_IDESCSI, -1) == 0) 131 return(0); 132 133 return(1); 134 } 135 136 /* 137 * Card attach function 138 * 139 */ 140 141 void 142 hcsc_attach(struct device *parent, struct device *self, void *aux) 143 { 144 struct hcsc_softc *sc = (struct hcsc_softc *)self; 145 struct podulebus_attach_args *pa = aux; 146 u_char *iobase; 147 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8]; 148 149 sc->sc_ncr5380.sc_min_dma_len = 0; 150 sc->sc_ncr5380.sc_no_disconnect = 0; 151 sc->sc_ncr5380.sc_parity_disable = 0; 152 153 sc->sc_ncr5380.sc_dma_alloc = NULL; 154 sc->sc_ncr5380.sc_dma_free = NULL; 155 sc->sc_ncr5380.sc_dma_poll = NULL; 156 sc->sc_ncr5380.sc_dma_setup = NULL; 157 sc->sc_ncr5380.sc_dma_start = NULL; 158 sc->sc_ncr5380.sc_dma_eop = NULL; 159 sc->sc_ncr5380.sc_dma_stop = NULL; 160 sc->sc_ncr5380.sc_intr_on = NULL; 161 sc->sc_ncr5380.sc_intr_off = NULL; 162 163 #ifdef NCR5380_USE_BUS_SPACE 164 sc->sc_ncr5380.sc_regt = pa->pa_fast_t; 165 bus_space_map(sc->sc_ncr5380.sc_regt, pa->pa_fast_base + 0x2000, 8, 0, 166 &sc->sc_ncr5380.sc_regh); 167 sc->sc_ncr5380.sci_r0 = 0; 168 sc->sc_ncr5380.sci_r1 = 1; 169 sc->sc_ncr5380.sci_r2 = 2; 170 sc->sc_ncr5380.sci_r3 = 3; 171 sc->sc_ncr5380.sci_r4 = 4; 172 sc->sc_ncr5380.sci_r5 = 5; 173 sc->sc_ncr5380.sci_r6 = 6; 174 sc->sc_ncr5380.sci_r7 = 7; 175 #else 176 iobase = (u_char *)pa->pa_fast_base + 0x2000; 177 sc->sc_ncr5380.sci_r0 = iobase + 0; 178 sc->sc_ncr5380.sci_r1 = iobase + 4; 179 sc->sc_ncr5380.sci_r2 = iobase + 8; 180 sc->sc_ncr5380.sci_r3 = iobase + 12; 181 sc->sc_ncr5380.sci_r4 = iobase + 16; 182 sc->sc_ncr5380.sci_r5 = iobase + 20; 183 sc->sc_ncr5380.sci_r6 = iobase + 24; 184 sc->sc_ncr5380.sci_r7 = iobase + 28; 185 #endif 186 sc->sc_pdmat = pa->pa_mod_t; 187 bus_space_map(sc->sc_pdmat, pa->pa_mod_base, 1, 0, &sc->sc_pdmah); 188 189 sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490; 190 191 sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in; 192 sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out; 193 194 /* Provide an override for the host id */ 195 sc->sc_ncr5380.sc_channel.chan_id = 7; 196 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname); 197 (void)get_bootconf_option(boot_args, hi_option, 198 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id); 199 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys; 200 201 printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id); 202 203 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 204 self->dv_xname, "intr"); 205 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 206 sc, &sc->sc_intrcnt); 207 208 ncr5380_attach(&sc->sc_ncr5380); 209 } 210 211 #ifndef HCSC_TSIZE_OUT 212 #define HCSC_TSIZE_OUT 512 213 #endif 214 215 #ifndef HCSC_TSIZE_IN 216 #define HCSC_TSIZE_IN 512 217 #endif 218 219 #define TIMEOUT 1000000 220 221 static __inline int 222 hcsc_ready(struct ncr5380_softc *sc) 223 { 224 int i; 225 226 for (i = TIMEOUT; i > 0; i--) { 227 if ((NCR5380_READ(sc,sci_csr) & 228 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 229 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 230 return(1); 231 232 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 233 SCI_BUSY(sc) == 0) 234 return(0); 235 } 236 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 237 return(0); 238 } 239 240 241 242 /* Return zero on success. */ 243 static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 244 { 245 int timo; 246 for (timo = TIMEOUT; timo; timo--) { 247 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 248 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 249 SCI_BUSY(sc) == 0) { 250 return; 251 } 252 } 253 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 254 } 255 256 static int 257 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 258 u_char *data) 259 { 260 struct hcsc_softc *sc = (void *)ncr_sc; 261 bus_space_tag_t pdmat = sc->sc_pdmat; 262 bus_space_handle_t pdmah = sc->sc_pdmah; 263 int s, resid, len; 264 265 s = splbio(); 266 267 NCR5380_WRITE(ncr_sc, sci_mode, 268 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 269 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 270 271 resid = datalen; 272 while (resid > 0) { 273 len = min(resid, HCSC_TSIZE_IN); 274 if (hcsc_ready(ncr_sc) == 0) 275 goto interrupt; 276 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 277 data += len; 278 resid -= len; 279 } 280 281 hcsc_wait_not_req(ncr_sc); 282 283 interrupt: 284 SCI_CLR_INTR(ncr_sc); 285 NCR5380_WRITE(ncr_sc, sci_mode, 286 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 287 splx(s); 288 return datalen - resid; 289 } 290 291 static int 292 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 293 u_char *data) 294 { 295 struct hcsc_softc *sc = (void *)ncr_sc; 296 bus_space_tag_t pdmat = sc->sc_pdmat; 297 bus_space_handle_t pdmah = sc->sc_pdmah; 298 int i, s, icmd, resid; 299 300 s = splbio(); 301 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 302 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 303 NCR5380_WRITE(ncr_sc, sci_mode, 304 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 305 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 306 307 resid = datalen; 308 if (hcsc_ready(ncr_sc) == 0) 309 goto interrupt; 310 311 if (resid > HCSC_TSIZE_OUT) { 312 /* 313 * Because of the chips DMA prefetch, phase changes 314 * etc, won't be detected until we have written at 315 * least one byte more. We pre-write 4 bytes so 316 * subsequent transfers will be aligned to a 4 byte 317 * boundary. Assuming disconects will only occur on 318 * block boundaries, we then correct for the pre-write 319 * when and if we get a phase change. If the chip had 320 * DMA byte counting hardware, the assumption would not 321 * be necessary. 322 */ 323 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 324 data += 4; 325 resid -= 4; 326 327 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 328 if (hcsc_ready(ncr_sc) == 0) { 329 resid += 4; /* Overshot */ 330 goto interrupt; 331 } 332 bus_space_write_multi_1(pdmat, pdmah, 0, data, 333 HCSC_TSIZE_OUT); 334 data += HCSC_TSIZE_OUT; 335 } 336 if (hcsc_ready(ncr_sc) == 0) { 337 resid += 4; /* Overshot */ 338 goto interrupt; 339 } 340 } 341 342 if (resid) { 343 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 344 resid = 0; 345 } 346 for (i = TIMEOUT; i > 0; i--) { 347 if ((NCR5380_READ(ncr_sc, sci_csr) 348 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 349 != SCI_CSR_DREQ) 350 break; 351 } 352 if (i != 0) 353 bus_space_write_1(pdmat, pdmah, 0, 0); 354 else 355 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 356 ncr_sc->sc_dev.dv_xname); 357 358 hcsc_wait_not_req(ncr_sc); 359 interrupt: 360 SCI_CLR_INTR(ncr_sc); 361 NCR5380_WRITE(ncr_sc, sci_mode, 362 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 363 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 364 splx(s); 365 return(datalen - resid); 366 } 367
Indexes created Tue Sep 30 20:09:53 GMT 2025