hcsc.c revision 1.5
1 /* $NetBSD: hcsc.c,v 1.5 2001/06/02 20:13:50 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 */ 72 73 #include <sys/param.h> 74 75 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.5 2001/06/02 20:13:50 bjh21 Exp $"); 76 77 #include <sys/systm.h> 78 #include <sys/kernel.h> 79 #include <sys/device.h> 80 #include <sys/buf.h> 81 #include <dev/scsipi/scsi_all.h> 82 #include <dev/scsipi/scsipi_all.h> 83 #include <dev/scsipi/scsiconf.h> 84 85 #include <dev/ic/ncr5380reg.h> 86 #include <dev/ic/ncr5380var.h> 87 88 #include <machine/bootconfig.h> 89 90 #include <dev/podulebus/podulebus.h> 91 #include <dev/podulebus/podules.h> 92 93 #include <dev/podulebus/hcscreg.h> 94 95 void hcsc_attach (struct device *, struct device *, void *); 96 int hcsc_match (struct device *, struct cfdata *, void *); 97 98 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *); 99 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *); 100 101 102 /* 103 * HCCS 8-bit SCSI softc structure. 104 * 105 * Contains the generic ncr5380 device node, podule information and 106 * global information required by the driver. 107 */ 108 109 struct hcsc_softc { 110 struct ncr5380_softc sc_ncr5380; 111 bus_space_tag_t sc_pdmat; 112 bus_space_handle_t sc_pdmah; 113 void *sc_ih; 114 struct evcnt sc_intrcnt; 115 }; 116 117 struct cfattach hcsc_ca = { 118 sizeof(struct hcsc_softc), hcsc_match, hcsc_attach 119 }; 120 121 /* 122 * Card probe function 123 * 124 * Just match the manufacturer and podule ID's 125 */ 126 127 int 128 hcsc_match(struct device *parent, struct cfdata *cf, void *aux) 129 { 130 struct podulebus_attach_args *pa = aux; 131 132 if (pa->pa_product == PODULE_HCCS_IDESCSI && 133 strncmp(pa->pa_descr, "SCSI", 4) == 0) 134 return 1; 135 return 0; 136 } 137 138 /* 139 * Card attach function 140 * 141 */ 142 143 void 144 hcsc_attach(struct device *parent, struct device *self, void *aux) 145 { 146 struct hcsc_softc *sc = (struct hcsc_softc *)self; 147 struct podulebus_attach_args *pa = aux; 148 u_char *iobase; 149 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8]; 150 151 sc->sc_ncr5380.sc_min_dma_len = 0; 152 sc->sc_ncr5380.sc_no_disconnect = 0; 153 sc->sc_ncr5380.sc_parity_disable = 0; 154 155 sc->sc_ncr5380.sc_dma_alloc = NULL; 156 sc->sc_ncr5380.sc_dma_free = NULL; 157 sc->sc_ncr5380.sc_dma_poll = NULL; 158 sc->sc_ncr5380.sc_dma_setup = NULL; 159 sc->sc_ncr5380.sc_dma_start = NULL; 160 sc->sc_ncr5380.sc_dma_eop = NULL; 161 sc->sc_ncr5380.sc_dma_stop = NULL; 162 sc->sc_ncr5380.sc_intr_on = NULL; 163 sc->sc_ncr5380.sc_intr_off = NULL; 164 165 #ifdef NCR5380_USE_BUS_SPACE 166 sc->sc_ncr5380.sc_regt = pa->pa_fast_t; 167 bus_space_map(sc->sc_ncr5380.sc_regt, 168 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 169 &sc->sc_ncr5380.sc_regh); 170 sc->sc_ncr5380.sci_r0 = 0; 171 sc->sc_ncr5380.sci_r1 = 1; 172 sc->sc_ncr5380.sci_r2 = 2; 173 sc->sc_ncr5380.sci_r3 = 3; 174 sc->sc_ncr5380.sci_r4 = 4; 175 sc->sc_ncr5380.sci_r5 = 5; 176 sc->sc_ncr5380.sci_r6 = 6; 177 sc->sc_ncr5380.sci_r7 = 7; 178 #else 179 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 180 sc->sc_ncr5380.sci_r0 = iobase + 0; 181 sc->sc_ncr5380.sci_r1 = iobase + 4; 182 sc->sc_ncr5380.sci_r2 = iobase + 8; 183 sc->sc_ncr5380.sci_r3 = iobase + 12; 184 sc->sc_ncr5380.sci_r4 = iobase + 16; 185 sc->sc_ncr5380.sci_r5 = iobase + 20; 186 sc->sc_ncr5380.sci_r6 = iobase + 24; 187 sc->sc_ncr5380.sci_r7 = iobase + 28; 188 #endif 189 sc->sc_pdmat = pa->pa_mod_t; 190 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 191 &sc->sc_pdmah); 192 193 sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490; 194 195 sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in; 196 sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out; 197 198 /* Provide an override for the host id */ 199 sc->sc_ncr5380.sc_channel.chan_id = 7; 200 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname); 201 (void)get_bootconf_option(boot_args, hi_option, 202 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id); 203 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys; 204 205 printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id); 206 207 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 208 self->dv_xname, "intr"); 209 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 210 sc, &sc->sc_intrcnt); 211 212 ncr5380_attach(&sc->sc_ncr5380); 213 } 214 215 #ifndef HCSC_TSIZE_OUT 216 #define HCSC_TSIZE_OUT 512 217 #endif 218 219 #ifndef HCSC_TSIZE_IN 220 #define HCSC_TSIZE_IN 512 221 #endif 222 223 #define TIMEOUT 1000000 224 225 static __inline int 226 hcsc_ready(struct ncr5380_softc *sc) 227 { 228 int i; 229 230 for (i = TIMEOUT; i > 0; i--) { 231 if ((NCR5380_READ(sc,sci_csr) & 232 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 233 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 234 return(1); 235 236 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 237 SCI_BUSY(sc) == 0) 238 return(0); 239 } 240 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 241 return(0); 242 } 243 244 245 246 /* Return zero on success. */ 247 static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 248 { 249 int timo; 250 for (timo = TIMEOUT; timo; timo--) { 251 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 252 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 253 SCI_BUSY(sc) == 0) { 254 return; 255 } 256 } 257 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 258 } 259 260 static int 261 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 262 u_char *data) 263 { 264 struct hcsc_softc *sc = (void *)ncr_sc; 265 bus_space_tag_t pdmat = sc->sc_pdmat; 266 bus_space_handle_t pdmah = sc->sc_pdmah; 267 int s, resid, len; 268 269 s = splbio(); 270 271 NCR5380_WRITE(ncr_sc, sci_mode, 272 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 273 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 274 275 resid = datalen; 276 while (resid > 0) { 277 len = min(resid, HCSC_TSIZE_IN); 278 if (hcsc_ready(ncr_sc) == 0) 279 goto interrupt; 280 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 281 data += len; 282 resid -= len; 283 } 284 285 hcsc_wait_not_req(ncr_sc); 286 287 interrupt: 288 SCI_CLR_INTR(ncr_sc); 289 NCR5380_WRITE(ncr_sc, sci_mode, 290 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 291 splx(s); 292 return datalen - resid; 293 } 294 295 static int 296 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 297 u_char *data) 298 { 299 struct hcsc_softc *sc = (void *)ncr_sc; 300 bus_space_tag_t pdmat = sc->sc_pdmat; 301 bus_space_handle_t pdmah = sc->sc_pdmah; 302 int i, s, icmd, resid; 303 304 s = splbio(); 305 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 306 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 307 NCR5380_WRITE(ncr_sc, sci_mode, 308 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 309 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 310 311 resid = datalen; 312 if (hcsc_ready(ncr_sc) == 0) 313 goto interrupt; 314 315 if (resid > HCSC_TSIZE_OUT) { 316 /* 317 * Because of the chips DMA prefetch, phase changes 318 * etc, won't be detected until we have written at 319 * least one byte more. We pre-write 4 bytes so 320 * subsequent transfers will be aligned to a 4 byte 321 * boundary. Assuming disconects will only occur on 322 * block boundaries, we then correct for the pre-write 323 * when and if we get a phase change. If the chip had 324 * DMA byte counting hardware, the assumption would not 325 * be necessary. 326 */ 327 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 328 data += 4; 329 resid -= 4; 330 331 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 332 if (hcsc_ready(ncr_sc) == 0) { 333 resid += 4; /* Overshot */ 334 goto interrupt; 335 } 336 bus_space_write_multi_1(pdmat, pdmah, 0, data, 337 HCSC_TSIZE_OUT); 338 data += HCSC_TSIZE_OUT; 339 } 340 if (hcsc_ready(ncr_sc) == 0) { 341 resid += 4; /* Overshot */ 342 goto interrupt; 343 } 344 } 345 346 if (resid) { 347 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 348 resid = 0; 349 } 350 for (i = TIMEOUT; i > 0; i--) { 351 if ((NCR5380_READ(ncr_sc, sci_csr) 352 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 353 != SCI_CSR_DREQ) 354 break; 355 } 356 if (i != 0) 357 bus_space_write_1(pdmat, pdmah, 0, 0); 358 else 359 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 360 ncr_sc->sc_dev.dv_xname); 361 362 hcsc_wait_not_req(ncr_sc); 363 interrupt: 364 SCI_CLR_INTR(ncr_sc); 365 NCR5380_WRITE(ncr_sc, sci_mode, 366 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 367 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 368 splx(s); 369 return(datalen - resid); 370 } 371
Indexes created Tue Sep 30 11:09:46 GMT 2025