hcsc.c revision 1.6
1 /* $NetBSD: hcsc.c,v 1.6 2001/06/12 11:52:03 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 * 72 * Andy Armstrong gives some details of the HCCS SCSI cards at 73 * <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>. 74 */ 75 76 #include <sys/param.h> 77 78 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.6 2001/06/12 11:52:03 bjh21 Exp $"); 79 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/device.h> 83 #include <sys/buf.h> 84 #include <dev/scsipi/scsi_all.h> 85 #include <dev/scsipi/scsipi_all.h> 86 #include <dev/scsipi/scsiconf.h> 87 88 #include <dev/ic/ncr5380reg.h> 89 #include <dev/ic/ncr5380var.h> 90 91 #include <machine/bootconfig.h> 92 93 #include <dev/podulebus/podulebus.h> 94 #include <dev/podulebus/podules.h> 95 96 #include <dev/podulebus/hcscreg.h> 97 98 void hcsc_attach (struct device *, struct device *, void *); 99 int hcsc_match (struct device *, struct cfdata *, void *); 100 101 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *); 102 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *); 103 104 105 /* 106 * HCCS 8-bit SCSI softc structure. 107 * 108 * Contains the generic ncr5380 device node, podule information and 109 * global information required by the driver. 110 */ 111 112 struct hcsc_softc { 113 struct ncr5380_softc sc_ncr5380; 114 bus_space_tag_t sc_pdmat; 115 bus_space_handle_t sc_pdmah; 116 void *sc_ih; 117 struct evcnt sc_intrcnt; 118 }; 119 120 struct cfattach hcsc_ca = { 121 sizeof(struct hcsc_softc), hcsc_match, hcsc_attach 122 }; 123 124 /* 125 * Card probe function 126 * 127 * Just match the manufacturer and podule ID's 128 */ 129 130 int 131 hcsc_match(struct device *parent, struct cfdata *cf, void *aux) 132 { 133 struct podulebus_attach_args *pa = aux; 134 135 if (pa->pa_product == PODULE_HCCS_IDESCSI && 136 strncmp(pa->pa_descr, "SCSI", 4) == 0) 137 return 1; 138 return 0; 139 } 140 141 /* 142 * Card attach function 143 * 144 */ 145 146 void 147 hcsc_attach(struct device *parent, struct device *self, void *aux) 148 { 149 struct hcsc_softc *sc = (struct hcsc_softc *)self; 150 struct podulebus_attach_args *pa = aux; 151 u_char *iobase; 152 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8]; 153 154 sc->sc_ncr5380.sc_min_dma_len = 0; 155 sc->sc_ncr5380.sc_no_disconnect = 0; 156 sc->sc_ncr5380.sc_parity_disable = 0; 157 158 sc->sc_ncr5380.sc_dma_alloc = NULL; 159 sc->sc_ncr5380.sc_dma_free = NULL; 160 sc->sc_ncr5380.sc_dma_poll = NULL; 161 sc->sc_ncr5380.sc_dma_setup = NULL; 162 sc->sc_ncr5380.sc_dma_start = NULL; 163 sc->sc_ncr5380.sc_dma_eop = NULL; 164 sc->sc_ncr5380.sc_dma_stop = NULL; 165 sc->sc_ncr5380.sc_intr_on = NULL; 166 sc->sc_ncr5380.sc_intr_off = NULL; 167 168 #ifdef NCR5380_USE_BUS_SPACE 169 sc->sc_ncr5380.sc_regt = pa->pa_fast_t; 170 bus_space_map(sc->sc_ncr5380.sc_regt, 171 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 172 &sc->sc_ncr5380.sc_regh); 173 sc->sc_ncr5380.sci_r0 = 0; 174 sc->sc_ncr5380.sci_r1 = 1; 175 sc->sc_ncr5380.sci_r2 = 2; 176 sc->sc_ncr5380.sci_r3 = 3; 177 sc->sc_ncr5380.sci_r4 = 4; 178 sc->sc_ncr5380.sci_r5 = 5; 179 sc->sc_ncr5380.sci_r6 = 6; 180 sc->sc_ncr5380.sci_r7 = 7; 181 #else 182 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 183 sc->sc_ncr5380.sci_r0 = iobase + 0; 184 sc->sc_ncr5380.sci_r1 = iobase + 4; 185 sc->sc_ncr5380.sci_r2 = iobase + 8; 186 sc->sc_ncr5380.sci_r3 = iobase + 12; 187 sc->sc_ncr5380.sci_r4 = iobase + 16; 188 sc->sc_ncr5380.sci_r5 = iobase + 20; 189 sc->sc_ncr5380.sci_r6 = iobase + 24; 190 sc->sc_ncr5380.sci_r7 = iobase + 28; 191 #endif 192 sc->sc_pdmat = pa->pa_mod_t; 193 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 194 &sc->sc_pdmah); 195 196 sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490; 197 198 sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in; 199 sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out; 200 201 /* Provide an override for the host id */ 202 sc->sc_ncr5380.sc_channel.chan_id = 7; 203 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname); 204 (void)get_bootconf_option(boot_args, hi_option, 205 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id); 206 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys; 207 208 printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id); 209 210 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 211 self->dv_xname, "intr"); 212 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 213 sc, &sc->sc_intrcnt); 214 215 ncr5380_attach(&sc->sc_ncr5380); 216 } 217 218 #ifndef HCSC_TSIZE_OUT 219 #define HCSC_TSIZE_OUT 512 220 #endif 221 222 #ifndef HCSC_TSIZE_IN 223 #define HCSC_TSIZE_IN 512 224 #endif 225 226 #define TIMEOUT 1000000 227 228 static __inline int 229 hcsc_ready(struct ncr5380_softc *sc) 230 { 231 int i; 232 233 for (i = TIMEOUT; i > 0; i--) { 234 if ((NCR5380_READ(sc,sci_csr) & 235 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 236 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 237 return(1); 238 239 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 240 SCI_BUSY(sc) == 0) 241 return(0); 242 } 243 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 244 return(0); 245 } 246 247 248 249 /* Return zero on success. */ 250 static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 251 { 252 int timo; 253 for (timo = TIMEOUT; timo; timo--) { 254 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 255 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 256 SCI_BUSY(sc) == 0) { 257 return; 258 } 259 } 260 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 261 } 262 263 static int 264 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 265 u_char *data) 266 { 267 struct hcsc_softc *sc = (void *)ncr_sc; 268 bus_space_tag_t pdmat = sc->sc_pdmat; 269 bus_space_handle_t pdmah = sc->sc_pdmah; 270 int s, resid, len; 271 272 s = splbio(); 273 274 NCR5380_WRITE(ncr_sc, sci_mode, 275 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 276 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 277 278 resid = datalen; 279 while (resid > 0) { 280 len = min(resid, HCSC_TSIZE_IN); 281 if (hcsc_ready(ncr_sc) == 0) 282 goto interrupt; 283 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 284 data += len; 285 resid -= len; 286 } 287 288 hcsc_wait_not_req(ncr_sc); 289 290 interrupt: 291 SCI_CLR_INTR(ncr_sc); 292 NCR5380_WRITE(ncr_sc, sci_mode, 293 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 294 splx(s); 295 return datalen - resid; 296 } 297 298 static int 299 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 300 u_char *data) 301 { 302 struct hcsc_softc *sc = (void *)ncr_sc; 303 bus_space_tag_t pdmat = sc->sc_pdmat; 304 bus_space_handle_t pdmah = sc->sc_pdmah; 305 int i, s, icmd, resid; 306 307 s = splbio(); 308 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 309 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 310 NCR5380_WRITE(ncr_sc, sci_mode, 311 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 312 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 313 314 resid = datalen; 315 if (hcsc_ready(ncr_sc) == 0) 316 goto interrupt; 317 318 if (resid > HCSC_TSIZE_OUT) { 319 /* 320 * Because of the chips DMA prefetch, phase changes 321 * etc, won't be detected until we have written at 322 * least one byte more. We pre-write 4 bytes so 323 * subsequent transfers will be aligned to a 4 byte 324 * boundary. Assuming disconects will only occur on 325 * block boundaries, we then correct for the pre-write 326 * when and if we get a phase change. If the chip had 327 * DMA byte counting hardware, the assumption would not 328 * be necessary. 329 */ 330 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 331 data += 4; 332 resid -= 4; 333 334 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 335 if (hcsc_ready(ncr_sc) == 0) { 336 resid += 4; /* Overshot */ 337 goto interrupt; 338 } 339 bus_space_write_multi_1(pdmat, pdmah, 0, data, 340 HCSC_TSIZE_OUT); 341 data += HCSC_TSIZE_OUT; 342 } 343 if (hcsc_ready(ncr_sc) == 0) { 344 resid += 4; /* Overshot */ 345 goto interrupt; 346 } 347 } 348 349 if (resid) { 350 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 351 resid = 0; 352 } 353 for (i = TIMEOUT; i > 0; i--) { 354 if ((NCR5380_READ(ncr_sc, sci_csr) 355 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 356 != SCI_CSR_DREQ) 357 break; 358 } 359 if (i != 0) 360 bus_space_write_1(pdmat, pdmah, 0, 0); 361 else 362 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 363 ncr_sc->sc_dev.dv_xname); 364 365 hcsc_wait_not_req(ncr_sc); 366 interrupt: 367 SCI_CLR_INTR(ncr_sc); 368 NCR5380_WRITE(ncr_sc, sci_mode, 369 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 370 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 371 splx(s); 372 return(datalen - resid); 373 } 374
Indexes created Tue Sep 30 20:09:53 GMT 2025