hcsc.c revision 1.8
1 /* $NetBSD: hcsc.c,v 1.8 2001/11/13 07:23:15 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Ben Harris 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Mark Brinicombe of Causality Limited. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 /* 40 * Copyright (c) 1996, 1997 Matthias Pfaller. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Matthias Pfaller. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * HCCS 8-bit SCSI driver using the generic NCR5380 driver 71 * 72 * Andy Armstrong gives some details of the HCCS SCSI cards at 73 * <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>. 74 */ 75 76 #include <sys/cdefs.h> 77 __KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.8 2001/11/13 07:23:15 lukem Exp $"); 78 79 #include <sys/param.h> 80 81 #include <sys/systm.h> 82 #include <sys/kernel.h> 83 #include <sys/device.h> 84 #include <sys/buf.h> 85 #include <dev/scsipi/scsi_all.h> 86 #include <dev/scsipi/scsipi_all.h> 87 #include <dev/scsipi/scsiconf.h> 88 89 #include <dev/ic/ncr5380reg.h> 90 #include <dev/ic/ncr5380var.h> 91 92 #include <machine/bootconfig.h> 93 94 #include <dev/podulebus/podulebus.h> 95 #include <dev/podulebus/podules.h> 96 #include <dev/podulebus/powerromreg.h> 97 98 #include <dev/podulebus/hcscreg.h> 99 100 void hcsc_attach (struct device *, struct device *, void *); 101 int hcsc_match (struct device *, struct cfdata *, void *); 102 103 static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *); 104 static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *); 105 106 107 /* 108 * HCCS 8-bit SCSI softc structure. 109 * 110 * Contains the generic ncr5380 device node, podule information and 111 * global information required by the driver. 112 */ 113 114 struct hcsc_softc { 115 struct ncr5380_softc sc_ncr5380; 116 bus_space_tag_t sc_pdmat; 117 bus_space_handle_t sc_pdmah; 118 void *sc_ih; 119 struct evcnt sc_intrcnt; 120 }; 121 122 struct cfattach hcsc_ca = { 123 sizeof(struct hcsc_softc), hcsc_match, hcsc_attach 124 }; 125 126 /* 127 * Card probe function 128 * 129 * Just match the manufacturer and podule ID's 130 */ 131 132 int 133 hcsc_match(struct device *parent, struct cfdata *cf, void *aux) 134 { 135 struct podulebus_attach_args *pa = aux; 136 137 /* Normal ROM */ 138 if (pa->pa_product == PODULE_HCCS_IDESCSI && 139 strncmp(pa->pa_descr, "SCSI", 4) == 0) 140 return 1; 141 /* PowerROM */ 142 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI && 143 podulebus_initloader(pa) == 0 && 144 podloader_callloader(pa, 0, 0) == PRID_HCCS_SCSI1) 145 return 1; 146 return 0; 147 } 148 149 /* 150 * Card attach function 151 * 152 */ 153 154 void 155 hcsc_attach(struct device *parent, struct device *self, void *aux) 156 { 157 struct hcsc_softc *sc = (struct hcsc_softc *)self; 158 struct podulebus_attach_args *pa = aux; 159 u_char *iobase; 160 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8]; 161 162 sc->sc_ncr5380.sc_min_dma_len = 0; 163 sc->sc_ncr5380.sc_no_disconnect = 0; 164 sc->sc_ncr5380.sc_parity_disable = 0; 165 166 sc->sc_ncr5380.sc_dma_alloc = NULL; 167 sc->sc_ncr5380.sc_dma_free = NULL; 168 sc->sc_ncr5380.sc_dma_poll = NULL; 169 sc->sc_ncr5380.sc_dma_setup = NULL; 170 sc->sc_ncr5380.sc_dma_start = NULL; 171 sc->sc_ncr5380.sc_dma_eop = NULL; 172 sc->sc_ncr5380.sc_dma_stop = NULL; 173 sc->sc_ncr5380.sc_intr_on = NULL; 174 sc->sc_ncr5380.sc_intr_off = NULL; 175 176 #ifdef NCR5380_USE_BUS_SPACE 177 sc->sc_ncr5380.sc_regt = pa->pa_fast_t; 178 bus_space_map(sc->sc_ncr5380.sc_regt, 179 pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0, 180 &sc->sc_ncr5380.sc_regh); 181 sc->sc_ncr5380.sci_r0 = 0; 182 sc->sc_ncr5380.sci_r1 = 1; 183 sc->sc_ncr5380.sci_r2 = 2; 184 sc->sc_ncr5380.sci_r3 = 3; 185 sc->sc_ncr5380.sci_r4 = 4; 186 sc->sc_ncr5380.sci_r5 = 5; 187 sc->sc_ncr5380.sci_r6 = 6; 188 sc->sc_ncr5380.sci_r7 = 7; 189 #else 190 iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET; 191 sc->sc_ncr5380.sci_r0 = iobase + 0; 192 sc->sc_ncr5380.sci_r1 = iobase + 4; 193 sc->sc_ncr5380.sci_r2 = iobase + 8; 194 sc->sc_ncr5380.sci_r3 = iobase + 12; 195 sc->sc_ncr5380.sci_r4 = iobase + 16; 196 sc->sc_ncr5380.sci_r5 = iobase + 20; 197 sc->sc_ncr5380.sci_r6 = iobase + 24; 198 sc->sc_ncr5380.sci_r7 = iobase + 28; 199 #endif 200 sc->sc_pdmat = pa->pa_mod_t; 201 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0, 202 &sc->sc_pdmah); 203 204 sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490; 205 206 sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in; 207 sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out; 208 209 /* Provide an override for the host id */ 210 sc->sc_ncr5380.sc_channel.chan_id = 7; 211 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname); 212 (void)get_bootconf_option(boot_args, hi_option, 213 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id); 214 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys; 215 216 printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id); 217 218 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 219 self->dv_xname, "intr"); 220 sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr, 221 sc, &sc->sc_intrcnt); 222 223 ncr5380_attach(&sc->sc_ncr5380); 224 } 225 226 #ifndef HCSC_TSIZE_OUT 227 #define HCSC_TSIZE_OUT 512 228 #endif 229 230 #ifndef HCSC_TSIZE_IN 231 #define HCSC_TSIZE_IN 512 232 #endif 233 234 #define TIMEOUT 1000000 235 236 static __inline int 237 hcsc_ready(struct ncr5380_softc *sc) 238 { 239 int i; 240 241 for (i = TIMEOUT; i > 0; i--) { 242 if ((NCR5380_READ(sc,sci_csr) & 243 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) == 244 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) 245 return(1); 246 247 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 248 SCI_BUSY(sc) == 0) 249 return(0); 250 } 251 printf("%s: ready timeout\n", sc->sc_dev.dv_xname); 252 return(0); 253 } 254 255 256 257 /* Return zero on success. */ 258 static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc) 259 { 260 int timo; 261 for (timo = TIMEOUT; timo; timo--) { 262 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 || 263 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 || 264 SCI_BUSY(sc) == 0) { 265 return; 266 } 267 } 268 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname); 269 } 270 271 static int 272 hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen, 273 u_char *data) 274 { 275 struct hcsc_softc *sc = (void *)ncr_sc; 276 bus_space_tag_t pdmat = sc->sc_pdmat; 277 bus_space_handle_t pdmah = sc->sc_pdmah; 278 int s, resid, len; 279 280 s = splbio(); 281 282 NCR5380_WRITE(ncr_sc, sci_mode, 283 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 284 NCR5380_WRITE(ncr_sc, sci_irecv, 0); 285 286 resid = datalen; 287 while (resid > 0) { 288 len = min(resid, HCSC_TSIZE_IN); 289 if (hcsc_ready(ncr_sc) == 0) 290 goto interrupt; 291 bus_space_read_multi_1(pdmat, pdmah, 0, data, len); 292 data += len; 293 resid -= len; 294 } 295 296 hcsc_wait_not_req(ncr_sc); 297 298 interrupt: 299 SCI_CLR_INTR(ncr_sc); 300 NCR5380_WRITE(ncr_sc, sci_mode, 301 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 302 splx(s); 303 return datalen - resid; 304 } 305 306 static int 307 hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen, 308 u_char *data) 309 { 310 struct hcsc_softc *sc = (void *)ncr_sc; 311 bus_space_tag_t pdmat = sc->sc_pdmat; 312 bus_space_handle_t pdmah = sc->sc_pdmah; 313 int i, s, icmd, resid; 314 315 s = splbio(); 316 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK; 317 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA); 318 NCR5380_WRITE(ncr_sc, sci_mode, 319 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA); 320 NCR5380_WRITE(ncr_sc, sci_dma_send, 0); 321 322 resid = datalen; 323 if (hcsc_ready(ncr_sc) == 0) 324 goto interrupt; 325 326 if (resid > HCSC_TSIZE_OUT) { 327 /* 328 * Because of the chips DMA prefetch, phase changes 329 * etc, won't be detected until we have written at 330 * least one byte more. We pre-write 4 bytes so 331 * subsequent transfers will be aligned to a 4 byte 332 * boundary. Assuming disconects will only occur on 333 * block boundaries, we then correct for the pre-write 334 * when and if we get a phase change. If the chip had 335 * DMA byte counting hardware, the assumption would not 336 * be necessary. 337 */ 338 bus_space_write_multi_1(pdmat, pdmah, 0, data, 4); 339 data += 4; 340 resid -= 4; 341 342 for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) { 343 if (hcsc_ready(ncr_sc) == 0) { 344 resid += 4; /* Overshot */ 345 goto interrupt; 346 } 347 bus_space_write_multi_1(pdmat, pdmah, 0, data, 348 HCSC_TSIZE_OUT); 349 data += HCSC_TSIZE_OUT; 350 } 351 if (hcsc_ready(ncr_sc) == 0) { 352 resid += 4; /* Overshot */ 353 goto interrupt; 354 } 355 } 356 357 if (resid) { 358 bus_space_write_multi_1(pdmat, pdmah, 0, data, resid); 359 resid = 0; 360 } 361 for (i = TIMEOUT; i > 0; i--) { 362 if ((NCR5380_READ(ncr_sc, sci_csr) 363 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) 364 != SCI_CSR_DREQ) 365 break; 366 } 367 if (i != 0) 368 bus_space_write_1(pdmat, pdmah, 0, 0); 369 else 370 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n", 371 ncr_sc->sc_dev.dv_xname); 372 373 hcsc_wait_not_req(ncr_sc); 374 interrupt: 375 SCI_CLR_INTR(ncr_sc); 376 NCR5380_WRITE(ncr_sc, sci_mode, 377 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA); 378 NCR5380_WRITE(ncr_sc, sci_icmd, icmd); 379 splx(s); 380 return(datalen - resid); 381 } 382
Indexes created Tue Sep 30 11:09:46 GMT 2025