oak.c revision 1.11 1 1.11 thorpej /* $NetBSD: oak.c,v 1.11 2002/09/30 22:33:19 thorpej Exp $ */
2 1.1 bjh21
3 1.1 bjh21 /*
4 1.1 bjh21 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.1 bjh21 * All rights reserved.
6 1.1 bjh21 *
7 1.1 bjh21 * This code is derived from software contributed to The NetBSD Foundation
8 1.1 bjh21 * by Mark Brinicombe of Causality Limited.
9 1.1 bjh21 *
10 1.1 bjh21 * Redistribution and use in source and binary forms, with or without
11 1.1 bjh21 * modification, are permitted provided that the following conditions
12 1.1 bjh21 * are met:
13 1.1 bjh21 * 1. Redistributions of source code must retain the above copyright
14 1.1 bjh21 * notice, this list of conditions and the following disclaimer.
15 1.1 bjh21 * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 bjh21 * notice, this list of conditions and the following disclaimer in the
17 1.1 bjh21 * documentation and/or other materials provided with the distribution.
18 1.1 bjh21 * 3. All advertising materials mentioning features or use of this software
19 1.1 bjh21 * must display the following acknowledgement:
20 1.1 bjh21 * This product includes software developed by the NetBSD
21 1.1 bjh21 * Foundation, Inc. and its contributors.
22 1.1 bjh21 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 bjh21 * contributors may be used to endorse or promote products derived
24 1.1 bjh21 * from this software without specific prior written permission.
25 1.1 bjh21 *
26 1.1 bjh21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 bjh21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 bjh21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 bjh21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 bjh21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 bjh21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 bjh21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 bjh21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 bjh21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 bjh21 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 bjh21 * POSSIBILITY OF SUCH DAMAGE.
37 1.1 bjh21 */
38 1.1 bjh21
39 1.1 bjh21 /*
40 1.7 bjh21 * Oak Solutions SCSI 1 driver using the generic NCR5380 driver.
41 1.2 bjh21 *
42 1.7 bjh21 * From <URL:http://foldoc.doc.ic.ac.uk/acorn/doc/scsi>:
43 1.7 bjh21 * --------8<--------
44 1.7 bjh21 * From: Hugo Fiennes
45 1.7 bjh21 * [...]
46 1.7 bjh21 * The oak scsi plays some other tricks to get max around 2.2Mb/sec:
47 1.7 bjh21 * it is a 16- bit interface (using their own hardware and an 8-bit
48 1.7 bjh21 * scsi controller to 'double-up' the data). What it does is: every
49 1.7 bjh21 * 128 bytes it uses a polling loop (see above) to check data is
50 1.7 bjh21 * present and the drive has reported no errors, etc. Inside each 128
51 1.7 bjh21 * byte block it just reads data as fast as it can: on a normal card
52 1.7 bjh21 * this would result in disaster if the drive wasn't fast enough to
53 1.7 bjh21 * feed the machine: on the oak card however, the hardware will not
54 1.7 bjh21 * assert IOGT (IO grant), so hanging the machine in a wait state
55 1.7 bjh21 * until data is ready. This can have problems: if the drive is to
56 1.7 bjh21 * slow (unlikely) the machine will completely stiff as the ARM3 can't
57 1.7 bjh21 * be kept in such a state for more than 10(?) us.
58 1.7 bjh21 * -------->8--------
59 1.7 bjh21 *
60 1.7 bjh21 * So far, my attempts at doing this have failed, though.
61 1.2 bjh21 *
62 1.2 bjh21 * This card has to be polled: it doesn't have anything connected to
63 1.2 bjh21 * PIRQ*. This seems to be a common failing of Archimedes disc
64 1.2 bjh21 * controllers.
65 1.1 bjh21 */
66 1.1 bjh21
67 1.6 lukem #include <sys/cdefs.h>
68 1.11 thorpej __KERNEL_RCSID(0, "$NetBSD: oak.c,v 1.11 2002/09/30 22:33:19 thorpej Exp $");
69 1.6 lukem
70 1.1 bjh21 #include <sys/param.h>
71 1.2 bjh21
72 1.1 bjh21 #include <sys/systm.h>
73 1.1 bjh21 #include <sys/kernel.h>
74 1.1 bjh21 #include <sys/device.h>
75 1.1 bjh21 #include <sys/buf.h>
76 1.1 bjh21 #include <dev/scsipi/scsi_all.h>
77 1.1 bjh21 #include <dev/scsipi/scsipi_all.h>
78 1.1 bjh21 #include <dev/scsipi/scsiconf.h>
79 1.1 bjh21
80 1.1 bjh21 #include <dev/ic/ncr5380reg.h>
81 1.1 bjh21 #include <dev/ic/ncr5380var.h>
82 1.1 bjh21
83 1.1 bjh21 #include <machine/bootconfig.h>
84 1.1 bjh21
85 1.1 bjh21 #include <dev/podulebus/podulebus.h>
86 1.1 bjh21 #include <dev/podulebus/podules.h>
87 1.4 bjh21 #include <dev/podulebus/powerromreg.h>
88 1.1 bjh21
89 1.7 bjh21 #include <dev/podulebus/oakreg.h>
90 1.7 bjh21
91 1.1 bjh21 void oak_attach (struct device *, struct device *, void *);
92 1.1 bjh21 int oak_match (struct device *, struct cfdata *, void *);
93 1.1 bjh21
94 1.7 bjh21 #if 0
95 1.7 bjh21 static int oak_pdma_in(struct ncr5380_softc *, int, int, u_char *);
96 1.7 bjh21 static int oak_pdma_out(struct ncr5380_softc *, int, int, u_char *);
97 1.7 bjh21 #endif
98 1.7 bjh21
99 1.1 bjh21 /*
100 1.1 bjh21 * Oak SCSI 1 softc structure.
101 1.1 bjh21 *
102 1.1 bjh21 * Contains the generic ncr5380 device node, podule information and
103 1.1 bjh21 * global information required by the driver.
104 1.1 bjh21 */
105 1.1 bjh21
106 1.1 bjh21 struct oak_softc {
107 1.1 bjh21 struct ncr5380_softc sc_ncr5380;
108 1.7 bjh21 bus_space_tag_t sc_pdmat;
109 1.7 bjh21 bus_space_handle_t sc_pdmah;
110 1.1 bjh21 };
111 1.1 bjh21
112 1.11 thorpej CFATTACH_DECL(oak, sizeof(struct oak_softc),
113 1.11 thorpej oak_match, oak_attach, NULL, NULL)
114 1.1 bjh21
115 1.1 bjh21 /*
116 1.1 bjh21 * Card probe function
117 1.1 bjh21 *
118 1.1 bjh21 * Just match the manufacturer and podule ID's
119 1.1 bjh21 */
120 1.1 bjh21
121 1.1 bjh21 int
122 1.1 bjh21 oak_match(struct device *parent, struct cfdata *cf, void *aux)
123 1.1 bjh21 {
124 1.1 bjh21 struct podulebus_attach_args *pa = aux;
125 1.1 bjh21
126 1.9 bjh21 if (pa->pa_product == PODULE_OAK_SCSI)
127 1.3 bjh21 return 1;
128 1.3 bjh21
129 1.3 bjh21 /* PowerROM */
130 1.3 bjh21 if (pa->pa_product == PODULE_ALSYSTEMS_SCSI &&
131 1.3 bjh21 podulebus_initloader(pa) == 0 &&
132 1.3 bjh21 podloader_callloader(pa, 0, 0) == PRID_OAK_SCSI1)
133 1.3 bjh21 return 1;
134 1.1 bjh21
135 1.5 bjh21 return 0;
136 1.1 bjh21 }
137 1.1 bjh21
138 1.1 bjh21 /*
139 1.1 bjh21 * Card attach function
140 1.1 bjh21 *
141 1.1 bjh21 */
142 1.1 bjh21
143 1.1 bjh21 void
144 1.1 bjh21 oak_attach(struct device *parent, struct device *self, void *aux)
145 1.1 bjh21 {
146 1.1 bjh21 struct oak_softc *sc = (struct oak_softc *)self;
147 1.1 bjh21 struct podulebus_attach_args *pa = aux;
148 1.8 bjh21 #ifndef NCR5380_USE_BUS_SPACE
149 1.1 bjh21 u_char *iobase;
150 1.8 bjh21 #endif
151 1.1 bjh21 char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8];
152 1.1 bjh21
153 1.1 bjh21 sc->sc_ncr5380.sc_flags |= NCR5380_FORCE_POLLING;
154 1.1 bjh21 sc->sc_ncr5380.sc_min_dma_len = 0;
155 1.1 bjh21 sc->sc_ncr5380.sc_no_disconnect = 0xff;
156 1.7 bjh21 sc->sc_ncr5380.sc_parity_disable = 0;
157 1.1 bjh21
158 1.1 bjh21 sc->sc_ncr5380.sc_dma_alloc = NULL;
159 1.1 bjh21 sc->sc_ncr5380.sc_dma_free = NULL;
160 1.1 bjh21 sc->sc_ncr5380.sc_dma_poll = NULL;
161 1.1 bjh21 sc->sc_ncr5380.sc_dma_setup = NULL;
162 1.1 bjh21 sc->sc_ncr5380.sc_dma_start = NULL;
163 1.1 bjh21 sc->sc_ncr5380.sc_dma_eop = NULL;
164 1.1 bjh21 sc->sc_ncr5380.sc_dma_stop = NULL;
165 1.1 bjh21 sc->sc_ncr5380.sc_intr_on = NULL;
166 1.1 bjh21 sc->sc_ncr5380.sc_intr_off = NULL;
167 1.1 bjh21
168 1.2 bjh21 #ifdef NCR5380_USE_BUS_SPACE
169 1.2 bjh21 sc->sc_ncr5380.sc_regt = pa->pa_mod_t;
170 1.2 bjh21 bus_space_map(sc->sc_ncr5380.sc_regt, pa->pa_mod_base, 8, 0,
171 1.2 bjh21 &sc->sc_ncr5380.sc_regh);
172 1.2 bjh21 sc->sc_ncr5380.sci_r0 = 0;
173 1.2 bjh21 sc->sc_ncr5380.sci_r1 = 1;
174 1.2 bjh21 sc->sc_ncr5380.sci_r2 = 2;
175 1.2 bjh21 sc->sc_ncr5380.sci_r3 = 3;
176 1.2 bjh21 sc->sc_ncr5380.sci_r4 = 4;
177 1.2 bjh21 sc->sc_ncr5380.sci_r5 = 5;
178 1.2 bjh21 sc->sc_ncr5380.sci_r6 = 6;
179 1.2 bjh21 sc->sc_ncr5380.sci_r7 = 7;
180 1.2 bjh21 #else
181 1.1 bjh21 iobase = (u_char *)pa->pa_mod_base;
182 1.1 bjh21 sc->sc_ncr5380.sci_r0 = iobase + 0;
183 1.1 bjh21 sc->sc_ncr5380.sci_r1 = iobase + 4;
184 1.1 bjh21 sc->sc_ncr5380.sci_r2 = iobase + 8;
185 1.1 bjh21 sc->sc_ncr5380.sci_r3 = iobase + 12;
186 1.1 bjh21 sc->sc_ncr5380.sci_r4 = iobase + 16;
187 1.1 bjh21 sc->sc_ncr5380.sci_r5 = iobase + 20;
188 1.1 bjh21 sc->sc_ncr5380.sci_r6 = iobase + 24;
189 1.1 bjh21 sc->sc_ncr5380.sci_r7 = iobase + 28;
190 1.2 bjh21 #endif
191 1.7 bjh21 sc->sc_pdmat = pa->pa_mod_t;
192 1.7 bjh21 bus_space_map(sc->sc_pdmat, pa->pa_mod_base + OAK_PDMA_OFFSET, 0x20, 0,
193 1.7 bjh21 &sc->sc_pdmah);
194 1.1 bjh21
195 1.1 bjh21 sc->sc_ncr5380.sc_rev = NCR_VARIANT_NCR5380;
196 1.1 bjh21
197 1.1 bjh21 sc->sc_ncr5380.sc_pio_in = ncr5380_pio_in;
198 1.1 bjh21 sc->sc_ncr5380.sc_pio_out = ncr5380_pio_out;
199 1.1 bjh21
200 1.1 bjh21 /* Provide an override for the host id */
201 1.1 bjh21 sc->sc_ncr5380.sc_channel.chan_id = 7;
202 1.1 bjh21 sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname);
203 1.1 bjh21 (void)get_bootconf_option(boot_args, hi_option,
204 1.1 bjh21 BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id);
205 1.1 bjh21 sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys;
206 1.1 bjh21
207 1.1 bjh21 printf(": host=%d, using 8 bit PIO\n",
208 1.1 bjh21 sc->sc_ncr5380.sc_channel.chan_id);
209 1.1 bjh21
210 1.1 bjh21 ncr5380_attach(&sc->sc_ncr5380);
211 1.1 bjh21 }
212 1.7 bjh21
213 1.7 bjh21 /*
214 1.7 bjh21 * XXX The code below doesn't work correctly. I probably need more
215 1.7 bjh21 * details on how the card works. [bjh21 20011202]
216 1.7 bjh21 */
217 1.7 bjh21 #if 0
218 1.7 bjh21
219 1.7 bjh21 #ifndef OAK_TSIZE_OUT
220 1.7 bjh21 #define OAK_TSIZE_OUT 128
221 1.7 bjh21 #endif
222 1.7 bjh21
223 1.7 bjh21 #ifndef OAK_TSIZE_IN
224 1.7 bjh21 #define OAK_TSIZE_IN 128
225 1.7 bjh21 #endif
226 1.7 bjh21
227 1.7 bjh21 #define TIMEOUT 1000000
228 1.7 bjh21
229 1.7 bjh21 static __inline int
230 1.7 bjh21 oak_ready(struct ncr5380_softc *sc)
231 1.7 bjh21 {
232 1.7 bjh21 int i;
233 1.7 bjh21 int status;
234 1.7 bjh21
235 1.7 bjh21 for (i = TIMEOUT; i > 0; i--) {
236 1.7 bjh21 status = NCR5380_READ(sc, sci_csr);
237 1.7 bjh21 if ((status & (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) ==
238 1.7 bjh21 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH))
239 1.7 bjh21 return(1);
240 1.7 bjh21
241 1.7 bjh21 if ((status & SCI_CSR_PHASE_MATCH) == 0 ||
242 1.7 bjh21 SCI_BUSY(sc) == 0)
243 1.7 bjh21 return(0);
244 1.7 bjh21 }
245 1.7 bjh21 printf("%s: ready timeout\n", sc->sc_dev.dv_xname);
246 1.7 bjh21 return(0);
247 1.7 bjh21
248 1.7 bjh21 #if 0 /* The Linux driver does this: */
249 1.7 bjh21 struct oak_softc *sc = (void *)ncr_sc;
250 1.7 bjh21 bus_space_tag_t pdmat = sc->sc_pdmat;
251 1.7 bjh21 bus_space_handle_t pdmah = sc->sc_pdmah;
252 1.7 bjh21 int i, status;
253 1.7 bjh21
254 1.7 bjh21 for (i = TIMEOUT; i > 0; i--) {
255 1.7 bjh21 status = bus_space_read_2(pdmat, pdmah, OAK_PDMA_STATUS);
256 1.7 bjh21 if (status & 0x200)
257 1.7 bjh21 return(0);
258 1.7 bjh21 if (status & 0x100)
259 1.7 bjh21 return(1);
260 1.7 bjh21 }
261 1.7 bjh21 printf("%s: ready timeout, status = 0x%x\n", ncr_sc->sc_dev.dv_xname,
262 1.7 bjh21 status);
263 1.7 bjh21 return(0);
264 1.7 bjh21 #endif
265 1.7 bjh21 }
266 1.7 bjh21
267 1.7 bjh21
268 1.7 bjh21
269 1.7 bjh21 /* Return zero on success. */
270 1.7 bjh21 static __inline void oak_wait_not_req(struct ncr5380_softc *sc)
271 1.7 bjh21 {
272 1.7 bjh21 int timo;
273 1.7 bjh21 for (timo = TIMEOUT; timo; timo--) {
274 1.7 bjh21 if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 ||
275 1.7 bjh21 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
276 1.7 bjh21 SCI_BUSY(sc) == 0) {
277 1.7 bjh21 return;
278 1.7 bjh21 }
279 1.7 bjh21 }
280 1.7 bjh21 printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname);
281 1.7 bjh21 }
282 1.7 bjh21
283 1.7 bjh21 static int
284 1.7 bjh21 oak_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen,
285 1.7 bjh21 u_char *data)
286 1.7 bjh21 {
287 1.7 bjh21 struct oak_softc *sc = (void *)ncr_sc;
288 1.7 bjh21 bus_space_tag_t pdmat = sc->sc_pdmat;
289 1.7 bjh21 bus_space_handle_t pdmah = sc->sc_pdmah;
290 1.7 bjh21 int s, resid, len;
291 1.7 bjh21
292 1.7 bjh21 s = splbio();
293 1.7 bjh21
294 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_mode,
295 1.7 bjh21 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
296 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_irecv, 0);
297 1.7 bjh21
298 1.7 bjh21 resid = datalen;
299 1.7 bjh21 while (resid > 0) {
300 1.7 bjh21 len = min(resid, OAK_TSIZE_IN);
301 1.7 bjh21 if (oak_ready(ncr_sc) == 0)
302 1.7 bjh21 goto interrupt;
303 1.7 bjh21 KASSERT(BUS_SPACE_ALIGNED_POINTER(data, u_int16_t));
304 1.7 bjh21 bus_space_read_multi_2(pdmat, pdmah, OAK_PDMA_READ,
305 1.7 bjh21 (u_int16_t *)data, len/2);
306 1.7 bjh21 data += len;
307 1.7 bjh21 resid -= len;
308 1.7 bjh21 }
309 1.7 bjh21
310 1.7 bjh21 oak_wait_not_req(ncr_sc);
311 1.7 bjh21
312 1.7 bjh21 interrupt:
313 1.7 bjh21 SCI_CLR_INTR(ncr_sc);
314 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_mode,
315 1.7 bjh21 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
316 1.7 bjh21 splx(s);
317 1.7 bjh21 return datalen - resid;
318 1.7 bjh21 }
319 1.7 bjh21
320 1.7 bjh21 static int
321 1.7 bjh21 oak_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen,
322 1.7 bjh21 u_char *data)
323 1.7 bjh21 {
324 1.7 bjh21 struct oak_softc *sc = (void *)ncr_sc;
325 1.7 bjh21 bus_space_tag_t pdmat = sc->sc_pdmat;
326 1.7 bjh21 bus_space_handle_t pdmah = sc->sc_pdmah;
327 1.7 bjh21 int i, s, icmd, resid;
328 1.7 bjh21
329 1.7 bjh21 s = splbio();
330 1.7 bjh21 icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK;
331 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
332 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_mode,
333 1.7 bjh21 NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
334 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
335 1.7 bjh21
336 1.7 bjh21 resid = datalen;
337 1.7 bjh21 if (oak_ready(ncr_sc) == 0)
338 1.7 bjh21 goto interrupt;
339 1.7 bjh21
340 1.7 bjh21 if (resid > OAK_TSIZE_OUT) {
341 1.7 bjh21 /*
342 1.7 bjh21 * Because of the chips DMA prefetch, phase changes
343 1.7 bjh21 * etc, won't be detected until we have written at
344 1.7 bjh21 * least one byte more. We pre-write 4 bytes so
345 1.7 bjh21 * subsequent transfers will be aligned to a 4 byte
346 1.7 bjh21 * boundary. Assuming disconects will only occur on
347 1.7 bjh21 * block boundaries, we then correct for the pre-write
348 1.7 bjh21 * when and if we get a phase change. If the chip had
349 1.7 bjh21 * DMA byte counting hardware, the assumption would not
350 1.7 bjh21 * be necessary.
351 1.7 bjh21 */
352 1.7 bjh21 KASSERT(BUS_SPACE_ALIGNED_POINTER(data, u_int16_t));
353 1.7 bjh21 bus_space_write_multi_2(pdmat, pdmah, OAK_PDMA_WRITE,
354 1.7 bjh21 (u_int16_t *)data, 4/2);
355 1.7 bjh21 data += 4;
356 1.7 bjh21 resid -= 4;
357 1.7 bjh21
358 1.7 bjh21 for (; resid >= OAK_TSIZE_OUT; resid -= OAK_TSIZE_OUT) {
359 1.7 bjh21 if (oak_ready(ncr_sc) == 0) {
360 1.7 bjh21 resid += 4; /* Overshot */
361 1.7 bjh21 goto interrupt;
362 1.7 bjh21 }
363 1.7 bjh21 bus_space_write_multi_2(pdmat, pdmah, OAK_PDMA_WRITE,
364 1.7 bjh21 (u_int16_t *)data, OAK_TSIZE_OUT/2);
365 1.7 bjh21 data += OAK_TSIZE_OUT;
366 1.7 bjh21 }
367 1.7 bjh21 if (oak_ready(ncr_sc) == 0) {
368 1.7 bjh21 resid += 4; /* Overshot */
369 1.7 bjh21 goto interrupt;
370 1.7 bjh21 }
371 1.7 bjh21 }
372 1.7 bjh21
373 1.7 bjh21 if (resid) {
374 1.7 bjh21 bus_space_write_multi_2(pdmat, pdmah, OAK_PDMA_WRITE,
375 1.7 bjh21 (u_int16_t *)data, resid/2);
376 1.7 bjh21 resid = 0;
377 1.7 bjh21 }
378 1.7 bjh21 for (i = TIMEOUT; i > 0; i--) {
379 1.7 bjh21 if ((NCR5380_READ(ncr_sc, sci_csr)
380 1.7 bjh21 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
381 1.7 bjh21 != SCI_CSR_DREQ)
382 1.7 bjh21 break;
383 1.7 bjh21 }
384 1.7 bjh21 if (i != 0)
385 1.7 bjh21 bus_space_write_2(pdmat, pdmah, OAK_PDMA_WRITE, 0);
386 1.7 bjh21 else
387 1.7 bjh21 printf("%s: timeout waiting for final SCI_DSR_DREQ.\n",
388 1.7 bjh21 ncr_sc->sc_dev.dv_xname);
389 1.7 bjh21
390 1.7 bjh21 oak_wait_not_req(ncr_sc);
391 1.7 bjh21 interrupt:
392 1.7 bjh21 SCI_CLR_INTR(ncr_sc);
393 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_mode,
394 1.7 bjh21 NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
395 1.7 bjh21 NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
396 1.7 bjh21 splx(s);
397 1.7 bjh21 return(datalen - resid);
398 1.7 bjh21 }
399 1.7 bjh21 #endif
400