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secreg.h revision 1.1
      1  1.1  bjh21 /* $NetBSD: secreg.h,v 1.1 2006/10/01 12:39:35 bjh21 Exp $ */
      2  1.1  bjh21 
      3  1.1  bjh21 /*
      4  1.1  bjh21  * Ben Harris 2006
      5  1.1  bjh21  *
      6  1.1  bjh21  * This file is in the public domain.
      7  1.1  bjh21  */
      8  1.1  bjh21 
      9  1.1  bjh21 /*
     10  1.1  bjh21  * Register definitions for Acorn SCSI expansion cards (AKA30, AKA31, AKA32)
     11  1.1  bjh21  */
     12  1.1  bjh21 
     13  1.1  bjh21 /*
     14  1.1  bjh21  * Offsets are in bus_space units (words)
     15  1.1  bjh21  */
     16  1.1  bjh21 
     17  1.1  bjh21 /* Podule "fast" space */
     18  1.1  bjh21 #define SEC_ROM		0x000
     19  1.1  bjh21 #define SEC_ISR		0x800 /* Interrupt status (read-only) */
     20  1.1  bjh21 #define SEC_ISR_SBIC	0x08  /* Interrupt from WD33C93A SBIC */
     21  1.1  bjh21 #define SEC_ISR_DMAC	0x02  /* TC uPD71071 DMAC */
     22  1.1  bjh21 #define SEC_ISR_IRQ	0x01  /* OR of the above */
     23  1.1  bjh21 #define SEC_CLRINT	0x800 /* Clear TC interrupt (write-only) */
     24  1.1  bjh21 #define SEC_MPR		0xc00 /* Memory page register */
     25  1.1  bjh21 #define SEC_MPR_UR	0x80  /* User reset */
     26  1.1  bjh21 #define SEC_MPR_IE	0x40  /* Interrupts enabled */
     27  1.1  bjh21 #define SEC_MPR_PAGE	0x3f  /* EPROM/SRAM page address */
     28  1.1  bjh21 
     29  1.1  bjh21 /* Module space */
     30  1.1  bjh21 #define SEC_SRAM	0x000
     31  1.1  bjh21 #define SEC_SBIC	0x800
     32  1.1  bjh21 #define SEC_DMAC	0xc00
     33  1.1  bjh21 
     34  1.1  bjh21 /* The address lines of the DMAC are permuted. */
     35  1.1  bjh21 #define DMAC(addr) ((addr) >> 1 | ((addr) & 1) << 7)
     36  1.1  bjh21 
     37  1.1  bjh21 #define SEC_CLKFREQ	80	/* Clock speed in 100 kHz */
     38  1.1  bjh21 #define SEC_NPAGES	16
     39  1.1  bjh21 #define SEC_PAGESIZE	4096
     40  1.1  bjh21 #define SEC_MEMSIZE	(SEC_PAGESIZE * SEC_NPAGES)
     41