Home | History | Annotate | Line # | Download | only in ppbus
      1  1.3  thorpej /* $NetBSD: ppbus_gpio.c,v 1.3 2021/08/07 16:19:15 thorpej Exp $ */
      2  1.1   cegger 
      3  1.1   cegger /*
      4  1.1   cegger  *  Copyright (c) 2008, Hans Rosenfeld <rosenfeld (at) grumpf.hope-2000.org>
      5  1.1   cegger  *  All rights reserved.
      6  1.1   cegger  *
      7  1.1   cegger  *  Redistribution and use in source and binary forms, with or without
      8  1.1   cegger  *  modification, are permitted provided that the following conditions
      9  1.1   cegger  *  are met:
     10  1.1   cegger  *  1. Redistributions of source code must retain the above copyright
     11  1.1   cegger  *     notice, this list of conditions and the following disclaimer.
     12  1.1   cegger  *  2. Redistributions in binary form must reproduce the above copyright
     13  1.1   cegger  *     notice, this list of conditions and the following disclaimer in the
     14  1.1   cegger  *     documentation and/or other materials provided with the distribution.
     15  1.1   cegger  *
     16  1.1   cegger  *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
     17  1.1   cegger  *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     18  1.1   cegger  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     19  1.1   cegger  *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
     20  1.1   cegger  *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     21  1.1   cegger  *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     22  1.1   cegger  *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     23  1.1   cegger  *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     24  1.1   cegger  *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1   cegger  *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1   cegger  *  SUCH DAMAGE.
     27  1.1   cegger  */
     28  1.1   cegger 
     29  1.1   cegger #include <sys/cdefs.h>
     30  1.3  thorpej __KERNEL_RCSID(0, "$NetBSD: ppbus_gpio.c,v 1.3 2021/08/07 16:19:15 thorpej Exp $");
     31  1.1   cegger 
     32  1.1   cegger #include <sys/param.h>
     33  1.1   cegger #include <sys/systm.h>
     34  1.1   cegger #include <sys/device.h>
     35  1.1   cegger #include <sys/gpio.h>
     36  1.1   cegger #include <sys/kernel.h>
     37  1.1   cegger 
     38  1.1   cegger #include <dev/gpio/gpiovar.h>
     39  1.1   cegger 
     40  1.1   cegger #include <dev/ppbus/ppbus_conf.h>
     41  1.1   cegger #include <dev/ppbus/ppbus_base.h>
     42  1.1   cegger #include <dev/ppbus/ppbus_io.h>
     43  1.1   cegger 
     44  1.1   cegger static int  gpio_ppbus_open(void *, device_t);
     45  1.1   cegger static void gpio_ppbus_close(void *, device_t);
     46  1.1   cegger static int  gpio_ppbus_pin_read(void *, int);
     47  1.1   cegger static void gpio_ppbus_pin_write(void *, int, int);
     48  1.1   cegger static void gpio_ppbus_pin_ctl(void *, int, int);
     49  1.1   cegger 
     50  1.1   cegger 
     51  1.1   cegger #define PORT(r, b, i) { PPBUS_R##r##TR, PPBUS_W##r##TR, b, i}
     52  1.1   cegger static const struct {
     53  1.1   cegger 	u_char rreg;
     54  1.1   cegger 	u_char wreg;
     55  1.1   cegger 	u_char bit;
     56  1.1   cegger 	u_char inv;
     57  1.1   cegger } ppbus_port[PPBUS_NPINS] = {	/* parallel port wiring: */
     58  1.1   cegger 	PORT(C, 0, 1),		/*     1: /C0  Output    */
     59  1.1   cegger 	PORT(D, 0, 0),		/*     2:  D0  Output    */
     60  1.1   cegger 	PORT(D, 1, 0),		/*     3:  D1  Output    */
     61  1.1   cegger 	PORT(D, 2, 0),		/*     4:  D2  Output    */
     62  1.1   cegger 	PORT(D, 3, 0),		/*     5:  D3  Output    */
     63  1.1   cegger 	PORT(D, 4, 0),		/*     6:  D4  Output    */
     64  1.1   cegger 	PORT(D, 5, 0),		/*     7:  D5  Output    */
     65  1.1   cegger 	PORT(D, 6, 0),		/*     8:  D6  Output    */
     66  1.1   cegger 	PORT(D, 7, 0),		/*     9:  D7  Output    */
     67  1.1   cegger 	PORT(S, 6, 0),		/*    10:  S6  Input     */
     68  1.1   cegger 	PORT(S, 7, 1),		/*    11: /S7  Input     */
     69  1.1   cegger 	PORT(S, 5, 0),		/*    12:  S5  Input     */
     70  1.1   cegger 	PORT(S, 4, 0),		/*    13:  S4  Input     */
     71  1.1   cegger 	PORT(C, 1, 1),		/*    14: /C1  Output    */
     72  1.1   cegger 	PORT(S, 3, 0),		/*    15:  S3  Input     */
     73  1.1   cegger 	PORT(C, 2, 0),		/*    16:  C2  Output    */
     74  1.1   cegger 	PORT(C, 3, 1),		/*    17: /C3  Output    */
     75  1.1   cegger };				/* 18-25: GND            */
     76  1.1   cegger 
     77  1.1   cegger void
     78  1.1   cegger gpio_ppbus_attach(struct ppbus_softc *sc)
     79  1.1   cegger {
     80  1.1   cegger 	struct gpiobus_attach_args gba;
     81  1.1   cegger 	gpio_pin_t *pin;
     82  1.1   cegger 	int i;
     83  1.1   cegger 
     84  1.1   cegger 	for (pin = &sc->sc_gpio_pins[0], i = 0; i < PPBUS_NPINS; pin++, i++) {
     85  1.1   cegger 		pin->pin_num = i;
     86  1.1   cegger 
     87  1.1   cegger 		if (((i >= 9) && (i <= 12)) || (i == 14)) {
     88  1.1   cegger 			pin->pin_caps = GPIO_PIN_INPUT;
     89  1.1   cegger 			pin->pin_flags = GPIO_PIN_INPUT;
     90  1.1   cegger 			pin->pin_state = gpio_ppbus_pin_read(sc, i);
     91  1.1   cegger 		} else {
     92  1.1   cegger 			pin->pin_caps = GPIO_PIN_OUTPUT;
     93  1.1   cegger 			pin->pin_flags = GPIO_PIN_OUTPUT;
     94  1.1   cegger 			pin->pin_state = GPIO_PIN_LOW;
     95  1.1   cegger 			gpio_ppbus_pin_write(sc, i, pin->pin_state);
     96  1.1   cegger 		}
     97  1.1   cegger 
     98  1.1   cegger 		gpio_ppbus_pin_ctl(sc, i, pin->pin_flags);
     99  1.1   cegger 	}
    100  1.1   cegger 
    101  1.1   cegger 	sc->sc_gpio_gc.gp_cookie = sc;
    102  1.1   cegger 	sc->sc_gpio_gc.gp_gc_open = gpio_ppbus_open;
    103  1.1   cegger 	sc->sc_gpio_gc.gp_gc_close = gpio_ppbus_close;
    104  1.1   cegger 	sc->sc_gpio_gc.gp_pin_read = gpio_ppbus_pin_read;
    105  1.1   cegger 	sc->sc_gpio_gc.gp_pin_write = gpio_ppbus_pin_write;
    106  1.1   cegger 	sc->sc_gpio_gc.gp_pin_ctl = gpio_ppbus_pin_ctl;
    107  1.1   cegger 
    108  1.1   cegger 	gba.gba_gc = &sc->sc_gpio_gc;
    109  1.1   cegger 	gba.gba_pins = sc->sc_gpio_pins;
    110  1.1   cegger 	gba.gba_npins = PPBUS_NPINS;
    111  1.1   cegger 
    112  1.2  thorpej 	config_found(sc->sc_dev, &gba, gpiobus_print,
    113  1.3  thorpej 	    CFARGS(.iattr = "gpiobus"));
    114  1.1   cegger }
    115  1.1   cegger 
    116  1.1   cegger static int
    117  1.1   cegger gpio_ppbus_open(void *arg, device_t dev)
    118  1.1   cegger {
    119  1.1   cegger 	struct ppbus_softc *sc = arg;
    120  1.1   cegger 
    121  1.1   cegger 	return ppbus_request_bus(sc->sc_dev, dev, PPBUS_WAIT|PPBUS_INTR, (hz));
    122  1.1   cegger }
    123  1.1   cegger 
    124  1.1   cegger static void
    125  1.1   cegger gpio_ppbus_close(void *arg, device_t dev)
    126  1.1   cegger {
    127  1.1   cegger 	struct ppbus_softc *sc = arg;
    128  1.1   cegger 
    129  1.1   cegger 	(void) ppbus_release_bus(sc->sc_dev, dev, PPBUS_WAIT|PPBUS_INTR, (hz));
    130  1.1   cegger }
    131  1.1   cegger 
    132  1.1   cegger static int
    133  1.1   cegger gpio_ppbus_pin_read(void *arg, int pin)
    134  1.1   cegger {
    135  1.1   cegger 	struct ppbus_softc *sc = arg;
    136  1.1   cegger 	u_char port = ppbus_io(sc->sc_dev, ppbus_port[pin].rreg, NULL, 0, 0);
    137  1.1   cegger 
    138  1.1   cegger 	return ((port >> ppbus_port[pin].bit) & 1) ^ ppbus_port[pin].inv;
    139  1.1   cegger }
    140  1.1   cegger 
    141  1.1   cegger static void
    142  1.1   cegger gpio_ppbus_pin_write(void *arg, int pin, int value)
    143  1.1   cegger {
    144  1.1   cegger 	struct ppbus_softc *sc = arg;
    145  1.1   cegger 	u_char port = ppbus_io(sc->sc_dev, ppbus_port[pin].rreg, NULL, 0, 0);
    146  1.1   cegger 
    147  1.1   cegger 	value ^= ppbus_port[pin].inv;
    148  1.1   cegger 	value <<= ppbus_port[pin].bit;
    149  1.1   cegger 	port &= ~(1 << ppbus_port[pin].bit);
    150  1.1   cegger 	port |= value;
    151  1.1   cegger 
    152  1.1   cegger 	ppbus_io(sc->sc_dev, ppbus_port[pin].wreg, NULL, 0, port);
    153  1.1   cegger }
    154  1.1   cegger 
    155  1.1   cegger static void
    156  1.1   cegger gpio_ppbus_pin_ctl(void *arg, int pin, int flags)
    157  1.1   cegger {
    158  1.1   cegger 	/* can't change parallel port pin configuration */
    159  1.1   cegger }
    160