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dhu.c revision 1.21.2.7
      1  1.21.2.7   nathanw /*	$NetBSD: dhu.c,v 1.21.2.7 2002/07/10 17:27:24 nathanw Exp $	*/
      2       1.1     ragge /*
      3       1.1     ragge  * Copyright (c) 1996  Ken C. Wellsch.  All rights reserved.
      4       1.1     ragge  * Copyright (c) 1992, 1993
      5       1.1     ragge  *	The Regents of the University of California.  All rights reserved.
      6       1.1     ragge  *
      7       1.1     ragge  * This code is derived from software contributed to Berkeley by
      8       1.1     ragge  * Ralph Campbell and Rick Macklem.
      9       1.1     ragge  *
     10       1.1     ragge  * Redistribution and use in source and binary forms, with or without
     11       1.1     ragge  * modification, are permitted provided that the following conditions
     12       1.1     ragge  * are met:
     13       1.1     ragge  * 1. Redistributions of source code must retain the above copyright
     14       1.1     ragge  *    notice, this list of conditions and the following disclaimer.
     15       1.1     ragge  * 2. Redistributions in binary form must reproduce the above copyright
     16       1.1     ragge  *    notice, this list of conditions and the following disclaimer in the
     17       1.1     ragge  *    documentation and/or other materials provided with the distribution.
     18       1.1     ragge  * 3. All advertising materials mentioning features or use of this software
     19       1.1     ragge  *    must display the following acknowledgement:
     20       1.1     ragge  *	This product includes software developed by the University of
     21       1.1     ragge  *	California, Berkeley and its contributors.
     22       1.1     ragge  * 4. Neither the name of the University nor the names of its contributors
     23       1.1     ragge  *    may be used to endorse or promote products derived from this software
     24       1.1     ragge  *    without specific prior written permission.
     25       1.1     ragge  *
     26       1.1     ragge  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27       1.1     ragge  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28       1.1     ragge  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29       1.1     ragge  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30       1.1     ragge  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31       1.1     ragge  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32       1.1     ragge  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33       1.1     ragge  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34       1.1     ragge  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35       1.1     ragge  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36       1.1     ragge  * SUCH DAMAGE.
     37       1.1     ragge  */
     38  1.21.2.3   nathanw 
     39  1.21.2.3   nathanw #include <sys/cdefs.h>
     40  1.21.2.7   nathanw __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.21.2.7 2002/07/10 17:27:24 nathanw Exp $");
     41       1.1     ragge 
     42       1.1     ragge #include <sys/param.h>
     43       1.1     ragge #include <sys/systm.h>
     44       1.1     ragge #include <sys/ioctl.h>
     45       1.1     ragge #include <sys/tty.h>
     46       1.1     ragge #include <sys/proc.h>
     47  1.21.2.4     ragge #include <sys/lwp.h>
     48       1.1     ragge #include <sys/map.h>
     49       1.1     ragge #include <sys/buf.h>
     50       1.1     ragge #include <sys/conf.h>
     51       1.1     ragge #include <sys/file.h>
     52       1.1     ragge #include <sys/uio.h>
     53       1.1     ragge #include <sys/kernel.h>
     54       1.1     ragge #include <sys/syslog.h>
     55       1.1     ragge #include <sys/device.h>
     56       1.1     ragge 
     57      1.15     ragge #include <machine/bus.h>
     58      1.13     ragge #include <machine/scb.h>
     59       1.1     ragge 
     60      1.15     ragge #include <dev/qbus/ubavar.h>
     61      1.15     ragge 
     62      1.15     ragge #include <dev/qbus/dhureg.h>
     63      1.15     ragge 
     64      1.15     ragge #include "ioconf.h"
     65       1.1     ragge 
     66       1.5     ragge /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */
     67       1.1     ragge 
     68       1.5     ragge #define	NDHULINE 	16
     69       1.2     ragge 
     70       1.5     ragge #define DHU_M2U(c)	((c)>>4)	/* convert minor(dev) to unit # */
     71       1.5     ragge #define DHU_LINE(u)	((u)&0xF)	/* extract line # from minor(dev) */
     72       1.2     ragge 
     73       1.5     ragge struct	dhu_softc {
     74       1.5     ragge 	struct	device	sc_dev;		/* Device struct used by config */
     75      1.19      matt 	struct	evcnt	sc_rintrcnt;	/* Interrupt statistics */
     76      1.19      matt 	struct	evcnt	sc_tintrcnt;	/* Interrupt statistics */
     77       1.5     ragge 	int		sc_type;	/* controller type, DHU or DHV */
     78      1.15     ragge 	bus_space_tag_t	sc_iot;
     79      1.15     ragge 	bus_space_handle_t sc_ioh;
     80      1.16     ragge 	bus_dma_tag_t	sc_dmat;
     81       1.5     ragge 	struct {
     82       1.5     ragge 		struct	tty *dhu_tty;	/* what we work on */
     83      1.16     ragge 		bus_dmamap_t dhu_dmah;
     84       1.5     ragge 		int	dhu_state;	/* to manage TX output status */
     85       1.5     ragge 		short	dhu_cc;		/* character count on TX */
     86       1.5     ragge 		short	dhu_modem;	/* modem bits state */
     87       1.5     ragge 	} sc_dhu[NDHULINE];
     88       1.1     ragge };
     89       1.1     ragge 
     90       1.5     ragge #define IS_DHU			16	/* Unibus DHU-11 board linecount */
     91       1.5     ragge #define IS_DHV			 8	/* Q-bus DHV-11 or DHQ-11 */
     92       1.2     ragge 
     93       1.2     ragge #define STATE_IDLE		000	/* no current output in progress */
     94       1.2     ragge #define STATE_DMA_RUNNING	001	/* DMA TX in progress */
     95       1.2     ragge #define STATE_DMA_STOPPED	002	/* DMA TX was aborted */
     96       1.2     ragge #define STATE_TX_ONE_CHAR	004	/* did a single char directly */
     97       1.2     ragge 
     98       1.2     ragge /* Flags used to monitor modem bits, make them understood outside driver */
     99       1.2     ragge 
    100       1.2     ragge #define DML_DTR		TIOCM_DTR
    101       1.2     ragge #define DML_RTS		TIOCM_RTS
    102       1.2     ragge #define DML_CTS		TIOCM_CTS
    103       1.2     ragge #define DML_DCD		TIOCM_CD
    104       1.2     ragge #define DML_RI		TIOCM_RI
    105       1.2     ragge #define DML_DSR		TIOCM_DSR
    106       1.2     ragge #define DML_BRK		0100000		/* no equivalent, we will mask */
    107       1.2     ragge 
    108      1.15     ragge #define DHU_READ_WORD(reg) \
    109      1.15     ragge 	bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
    110      1.15     ragge #define DHU_WRITE_WORD(reg, val) \
    111      1.15     ragge 	bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
    112      1.15     ragge #define DHU_READ_BYTE(reg) \
    113      1.15     ragge 	bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg)
    114      1.15     ragge #define DHU_WRITE_BYTE(reg, val) \
    115      1.15     ragge 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)
    116      1.15     ragge 
    117      1.15     ragge 
    118       1.1     ragge /*  On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */
    119       1.1     ragge /* a baud rate from the same group.  So limiting to B is likely */
    120       1.1     ragge /* best, although clone boards like the ABLE QHV allow all settings. */
    121       1.1     ragge 
    122       1.5     ragge static struct speedtab dhuspeedtab[] = {
    123       1.1     ragge   {       0,	0		},	/* Groups  */
    124       1.1     ragge   {      50,	DHU_LPR_B50	},	/* A	   */
    125       1.1     ragge   {      75,	DHU_LPR_B75	},	/* 	 B */
    126       1.1     ragge   {     110,	DHU_LPR_B110	},	/* A and B */
    127       1.1     ragge   {     134,	DHU_LPR_B134	},	/* A and B */
    128       1.1     ragge   {     150,	DHU_LPR_B150	},	/* 	 B */
    129       1.1     ragge   {     300,	DHU_LPR_B300	},	/* A and B */
    130       1.1     ragge   {     600,	DHU_LPR_B600	},	/* A and B */
    131       1.1     ragge   {    1200,	DHU_LPR_B1200	},	/* A and B */
    132       1.1     ragge   {    1800,	DHU_LPR_B1800	},	/* 	 B */
    133       1.1     ragge   {    2000,	DHU_LPR_B2000	},	/* 	 B */
    134       1.1     ragge   {    2400,	DHU_LPR_B2400	},	/* A and B */
    135       1.1     ragge   {    4800,	DHU_LPR_B4800	},	/* A and B */
    136       1.1     ragge   {    7200,	DHU_LPR_B7200	},	/* A	   */
    137       1.1     ragge   {    9600,	DHU_LPR_B9600	},	/* A and B */
    138       1.1     ragge   {   19200,	DHU_LPR_B19200	},	/* 	 B */
    139       1.1     ragge   {   38400,	DHU_LPR_B38400	},	/* A	   */
    140       1.1     ragge   {      -1,	-1		}
    141       1.1     ragge };
    142       1.1     ragge 
    143      1.11     ragge static int	dhu_match __P((struct device *, struct cfdata *, void *));
    144       1.1     ragge static void	dhu_attach __P((struct device *, struct device *, void *));
    145      1.17      matt static	void	dhurint __P((void *));
    146      1.17      matt static	void	dhuxint __P((void *));
    147       1.2     ragge static	void	dhustart __P((struct tty *));
    148       1.2     ragge static	int	dhuparam __P((struct tty *, struct termios *));
    149       1.2     ragge static	int	dhuiflow __P((struct tty *, int));
    150       1.5     ragge static unsigned	dhumctl __P((struct dhu_softc *,int, int, int));
    151  1.21.2.2   nathanw 
    152  1.21.2.2   nathanw cdev_decl(dhu);
    153       1.1     ragge 
    154       1.5     ragge struct	cfattach dhu_ca = {
    155       1.5     ragge 	sizeof(struct dhu_softc), dhu_match, dhu_attach
    156       1.5     ragge };
    157      1.10   thorpej 
    158       1.1     ragge /* Autoconfig handles: setup the controller to interrupt, */
    159       1.1     ragge /* then complete the housecleaning for full operation */
    160       1.1     ragge 
    161       1.1     ragge static int
    162      1.11     ragge dhu_match(parent, cf, aux)
    163       1.1     ragge         struct device *parent;
    164      1.11     ragge 	struct cfdata *cf;
    165      1.11     ragge         void *aux;
    166       1.1     ragge {
    167       1.1     ragge 	struct uba_attach_args *ua = aux;
    168      1.18  augustss 	int n;
    169       1.1     ragge 
    170       1.2     ragge 	/* Reset controller to initialize, enable TX/RX interrupts */
    171       1.1     ragge 	/* to catch floating vector info elsewhere when completed */
    172       1.1     ragge 
    173      1.15     ragge 	bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR,
    174      1.15     ragge 	    DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE);
    175       1.1     ragge 
    176       1.1     ragge 	/* Now wait up to 3 seconds for self-test to complete. */
    177       1.1     ragge 
    178       1.1     ragge 	for (n = 0; n < 300; n++) {
    179       1.1     ragge 		DELAY(10000);
    180      1.15     ragge 		if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) &
    181      1.15     ragge 		    DHU_CSR_MASTER_RESET) == 0)
    182       1.1     ragge 			break;
    183       1.1     ragge 	}
    184       1.1     ragge 
    185       1.1     ragge 	/* If the RESET did not clear after 3 seconds, */
    186       1.1     ragge 	/* the controller must be broken. */
    187       1.1     ragge 
    188       1.2     ragge 	if (n >= 300)
    189       1.1     ragge 		return 0;
    190       1.1     ragge 
    191       1.1     ragge 	/* Check whether diagnostic run has signalled a failure. */
    192       1.1     ragge 
    193      1.15     ragge 	if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) &
    194      1.15     ragge 	    DHU_CSR_DIAG_FAIL) != 0)
    195       1.1     ragge 		return 0;
    196       1.1     ragge 
    197       1.1     ragge        	return 1;
    198       1.1     ragge }
    199       1.1     ragge 
    200       1.1     ragge static void
    201       1.5     ragge dhu_attach(parent, self, aux)
    202       1.1     ragge         struct device *parent, *self;
    203       1.1     ragge         void *aux;
    204       1.1     ragge {
    205      1.18  augustss 	struct dhu_softc *sc = (void *)self;
    206      1.18  augustss 	struct uba_attach_args *ua = aux;
    207      1.18  augustss 	unsigned c;
    208      1.18  augustss 	int n, i;
    209       1.1     ragge 
    210      1.15     ragge 	sc->sc_iot = ua->ua_iot;
    211      1.15     ragge 	sc->sc_ioh = ua->ua_ioh;
    212      1.16     ragge 	sc->sc_dmat = ua->ua_dmat;
    213       1.1     ragge 	/* Process the 8 bytes of diagnostic info put into */
    214       1.1     ragge 	/* the FIFO following the master reset operation. */
    215       1.1     ragge 
    216       1.8  christos 	printf("\n%s:", self->dv_xname);
    217       1.1     ragge 	for (n = 0; n < 8; n++) {
    218      1.15     ragge 		c = DHU_READ_WORD(DHU_UBA_RBUF);
    219       1.1     ragge 
    220       1.2     ragge 		if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) {
    221       1.2     ragge 			if ((c&0200) == 0000)
    222       1.8  christos 				printf(" rom(%d) version %d",
    223       1.1     ragge 					((c>>1)&01), ((c>>2)&037));
    224       1.2     ragge 			else if (((c>>2)&07) != 0)
    225       1.8  christos 				printf(" diag-error(proc%d)=%x",
    226       1.1     ragge 					((c>>1)&01), ((c>>2)&07));
    227       1.1     ragge 		}
    228       1.1     ragge 	}
    229       1.1     ragge 
    230      1.15     ragge 	c = DHU_READ_WORD(DHU_UBA_STAT);
    231       1.2     ragge 
    232       1.5     ragge 	sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV;
    233      1.15     ragge 	printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V");
    234       1.1     ragge 
    235      1.16     ragge 	for (i = 0; i < sc->sc_type; i++) {
    236      1.16     ragge 		struct tty *tp;
    237      1.16     ragge 		tp = sc->sc_dhu[i].dhu_tty = ttymalloc();
    238      1.16     ragge 		sc->sc_dhu[i].dhu_state = STATE_IDLE;
    239      1.16     ragge 		bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1,
    240      1.16     ragge 		    tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT,
    241      1.16     ragge 		    &sc->sc_dhu[i].dhu_dmah);
    242      1.16     ragge 		bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah,
    243      1.16     ragge 		    tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT);
    244      1.16     ragge 
    245      1.16     ragge 	}
    246      1.16     ragge 
    247      1.17      matt 	/* Now establish RX & TX interrupt handlers */
    248      1.17      matt 
    249      1.19      matt 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
    250      1.19      matt 		dhurint, sc, &sc->sc_rintrcnt);
    251      1.19      matt 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4,
    252      1.19      matt 		dhuxint, sc, &sc->sc_tintrcnt);
    253      1.20      matt 	evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
    254      1.20      matt 		sc->sc_dev.dv_xname, "rintr");
    255      1.20      matt 	evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
    256      1.20      matt 		sc->sc_dev.dv_xname, "tintr");
    257       1.1     ragge }
    258       1.1     ragge 
    259       1.2     ragge /* Receiver Interrupt */
    260       1.2     ragge 
    261       1.1     ragge static void
    262      1.17      matt dhurint(arg)
    263      1.17      matt 	void *arg;
    264       1.1     ragge {
    265      1.17      matt 	struct	dhu_softc *sc = arg;
    266      1.18  augustss 	struct tty *tp;
    267      1.18  augustss 	int cc, line;
    268      1.18  augustss 	unsigned c, delta;
    269       1.1     ragge 	int overrun = 0;
    270       1.2     ragge 
    271      1.15     ragge 	while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) {
    272       1.1     ragge 
    273       1.1     ragge 		/* Ignore diagnostic FIFO entries. */
    274       1.1     ragge 
    275       1.5     ragge 		if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE)
    276       1.1     ragge 			continue;
    277       1.1     ragge 
    278       1.5     ragge 		cc = c & 0xFF;
    279       1.5     ragge 		line = DHU_LINE(c>>8);
    280       1.5     ragge 		tp = sc->sc_dhu[line].dhu_tty;
    281       1.1     ragge 
    282       1.1     ragge 		/* LINK.TYPE is set so we get modem control FIFO entries */
    283       1.1     ragge 
    284       1.1     ragge 		if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) {
    285       1.2     ragge 			c = (c << 8);
    286       1.1     ragge 			/* Do MDMBUF flow control, wakeup sleeping opens */
    287       1.1     ragge 			if (c & DHU_STAT_DCD) {
    288       1.1     ragge 				if (!(tp->t_state & TS_CARR_ON))
    289      1.21       eeh 				    (void)(*tp->t_linesw->l_modem)(tp, 1);
    290       1.1     ragge 			}
    291       1.1     ragge 			else if ((tp->t_state & TS_CARR_ON) &&
    292      1.21       eeh 				(*tp->t_linesw->l_modem)(tp, 0) == 0)
    293       1.5     ragge 					(void) dhumctl(sc, line, 0, DMSET);
    294       1.2     ragge 
    295       1.2     ragge 			/* Do CRTSCTS flow control */
    296       1.5     ragge 			delta = c ^ sc->sc_dhu[line].dhu_modem;
    297       1.5     ragge 			sc->sc_dhu[line].dhu_modem = c;
    298       1.2     ragge 			if ((delta & DHU_STAT_CTS) &&
    299       1.2     ragge 			    (tp->t_state & TS_ISOPEN) &&
    300       1.2     ragge 			    (tp->t_cflag & CRTSCTS)) {
    301       1.2     ragge 				if (c & DHU_STAT_CTS) {
    302       1.2     ragge 					tp->t_state &= ~TS_TTSTOP;
    303       1.5     ragge 					ttstart(tp);
    304       1.2     ragge 				} else {
    305       1.2     ragge 					tp->t_state |= TS_TTSTOP;
    306       1.5     ragge 					dhustop(tp, 0);
    307       1.2     ragge 				}
    308       1.2     ragge 			}
    309       1.2     ragge 			continue;
    310       1.1     ragge 		}
    311       1.1     ragge 
    312       1.5     ragge 		if (!(tp->t_state & TS_ISOPEN)) {
    313       1.5     ragge 			wakeup((caddr_t)&tp->t_rawq);
    314       1.5     ragge 			continue;
    315       1.5     ragge 		}
    316       1.5     ragge 
    317       1.1     ragge 		if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) {
    318       1.5     ragge 			log(LOG_WARNING, "%s: silo overflow, line %d\n",
    319       1.5     ragge 				sc->sc_dev.dv_xname, line);
    320       1.1     ragge 			overrun = 1;
    321       1.1     ragge 		}
    322       1.1     ragge 		/* A BREAK key will appear as a NULL with a framing error */
    323       1.1     ragge 		if (c & DHU_RBUF_FRAMING_ERR)
    324       1.1     ragge 			cc |= TTY_FE;
    325       1.1     ragge 		if (c & DHU_RBUF_PARITY_ERR)
    326       1.1     ragge 			cc |= TTY_PE;
    327       1.1     ragge 
    328      1.21       eeh 		(*tp->t_linesw->l_rint)(cc, tp);
    329       1.1     ragge 	}
    330       1.1     ragge }
    331       1.1     ragge 
    332       1.1     ragge /* Transmitter Interrupt */
    333       1.1     ragge 
    334       1.1     ragge static void
    335      1.17      matt dhuxint(arg)
    336      1.17      matt 	void *arg;
    337       1.1     ragge {
    338      1.18  augustss 	struct	dhu_softc *sc = arg;
    339      1.18  augustss 	struct tty *tp;
    340      1.18  augustss 	int line;
    341       1.2     ragge 
    342      1.15     ragge 	line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI));
    343       1.1     ragge 
    344       1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    345       1.2     ragge 
    346       1.1     ragge 	tp->t_state &= ~TS_BUSY;
    347       1.1     ragge 	if (tp->t_state & TS_FLUSH)
    348       1.1     ragge 		tp->t_state &= ~TS_FLUSH;
    349       1.1     ragge 	else {
    350       1.5     ragge 		if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED)
    351      1.15     ragge 			sc->sc_dhu[line].dhu_cc -=
    352      1.15     ragge 			DHU_READ_WORD(DHU_UBA_TBUFCNT);
    353       1.5     ragge 		ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc);
    354       1.5     ragge 		sc->sc_dhu[line].dhu_cc = 0;
    355       1.1     ragge 	}
    356       1.1     ragge 
    357       1.5     ragge 	sc->sc_dhu[line].dhu_state = STATE_IDLE;
    358       1.2     ragge 
    359  1.21.2.1   nathanw 	(*tp->t_linesw->l_start)(tp);
    360       1.1     ragge }
    361       1.1     ragge 
    362       1.1     ragge int
    363       1.5     ragge dhuopen(dev, flag, mode, p)
    364       1.1     ragge 	dev_t dev;
    365       1.1     ragge 	int flag, mode;
    366       1.1     ragge 	struct proc *p;
    367       1.1     ragge {
    368      1.18  augustss 	struct tty *tp;
    369      1.18  augustss 	int unit, line;
    370       1.5     ragge 	struct dhu_softc *sc;
    371       1.1     ragge 	int s, error = 0;
    372       1.1     ragge 
    373       1.5     ragge 	unit = DHU_M2U(minor(dev));
    374       1.5     ragge 	line = DHU_LINE(minor(dev));
    375       1.5     ragge 
    376       1.5     ragge 	if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL)
    377       1.1     ragge 		return (ENXIO);
    378       1.5     ragge 
    379       1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    380       1.5     ragge 
    381       1.5     ragge 	if (line >= sc->sc_type)
    382       1.5     ragge 		return ENXIO;
    383       1.5     ragge 
    384      1.16     ragge 	s = spltty();
    385      1.16     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    386      1.16     ragge 	sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT);
    387      1.16     ragge 	(void) splx(s);
    388      1.16     ragge 
    389       1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    390       1.5     ragge 
    391       1.2     ragge 	tp->t_oproc   = dhustart;
    392       1.2     ragge 	tp->t_param   = dhuparam;
    393       1.2     ragge 	tp->t_hwiflow = dhuiflow;
    394       1.1     ragge 	tp->t_dev = dev;
    395       1.1     ragge 	if ((tp->t_state & TS_ISOPEN) == 0) {
    396       1.1     ragge 		ttychars(tp);
    397       1.2     ragge 		if (tp->t_ispeed == 0) {
    398       1.2     ragge 			tp->t_iflag = TTYDEF_IFLAG;
    399       1.2     ragge 			tp->t_oflag = TTYDEF_OFLAG;
    400       1.2     ragge 			tp->t_cflag = TTYDEF_CFLAG;
    401       1.2     ragge 			tp->t_lflag = TTYDEF_LFLAG;
    402       1.2     ragge 			tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
    403       1.2     ragge 		}
    404       1.1     ragge 		(void) dhuparam(tp, &tp->t_termios);
    405       1.1     ragge 		ttsetwater(tp);
    406  1.21.2.7   nathanw 	} else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0)
    407       1.1     ragge 		return (EBUSY);
    408       1.1     ragge 	/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
    409       1.5     ragge 	if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD)
    410       1.1     ragge 		tp->t_state |= TS_CARR_ON;
    411       1.1     ragge 	s = spltty();
    412       1.1     ragge 	while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
    413       1.1     ragge 	       !(tp->t_state & TS_CARR_ON)) {
    414      1.12     ragge 		tp->t_wopen++;
    415       1.1     ragge 		error = ttysleep(tp, (caddr_t)&tp->t_rawq,
    416       1.1     ragge 				TTIPRI | PCATCH, ttopen, 0);
    417      1.12     ragge 		tp->t_wopen--;
    418       1.1     ragge 		if (error)
    419       1.1     ragge 			break;
    420       1.1     ragge 	}
    421       1.1     ragge 	(void) splx(s);
    422       1.1     ragge 	if (error)
    423       1.1     ragge 		return (error);
    424      1.21       eeh 	return ((*tp->t_linesw->l_open)(dev, tp));
    425       1.1     ragge }
    426       1.1     ragge 
    427       1.1     ragge /*ARGSUSED*/
    428       1.1     ragge int
    429       1.5     ragge dhuclose(dev, flag, mode, p)
    430       1.1     ragge 	dev_t dev;
    431       1.1     ragge 	int flag, mode;
    432       1.1     ragge 	struct proc *p;
    433       1.1     ragge {
    434      1.18  augustss 	struct tty *tp;
    435      1.18  augustss 	int unit, line;
    436       1.5     ragge 	struct dhu_softc *sc;
    437       1.5     ragge 
    438       1.5     ragge 	unit = DHU_M2U(minor(dev));
    439       1.5     ragge 	line = DHU_LINE(minor(dev));
    440       1.1     ragge 
    441       1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    442       1.5     ragge 
    443       1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    444       1.1     ragge 
    445      1.21       eeh 	(*tp->t_linesw->l_close)(tp, flag);
    446       1.1     ragge 
    447       1.1     ragge 	/* Make sure a BREAK state is not left enabled. */
    448       1.1     ragge 
    449       1.5     ragge 	(void) dhumctl(sc, line, DML_BRK, DMBIC);
    450       1.1     ragge 
    451       1.1     ragge 	/* Do a hangup if so required. */
    452       1.1     ragge 
    453      1.12     ragge 	if ((tp->t_cflag & HUPCL) || tp->t_wopen ||
    454       1.1     ragge 	    !(tp->t_state & TS_ISOPEN))
    455       1.5     ragge 		(void) dhumctl(sc, line, 0, DMSET);
    456       1.1     ragge 
    457       1.1     ragge 	return (ttyclose(tp));
    458       1.1     ragge }
    459       1.1     ragge 
    460       1.1     ragge int
    461       1.5     ragge dhuread(dev, uio, flag)
    462       1.1     ragge 	dev_t dev;
    463       1.1     ragge 	struct uio *uio;
    464       1.1     ragge {
    465      1.18  augustss 	struct dhu_softc *sc;
    466      1.18  augustss 	struct tty *tp;
    467       1.1     ragge 
    468       1.5     ragge 	sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    469       1.5     ragge 
    470       1.5     ragge 	tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    471      1.21       eeh 	return ((*tp->t_linesw->l_read)(tp, uio, flag));
    472       1.1     ragge }
    473       1.1     ragge 
    474       1.1     ragge int
    475       1.5     ragge dhuwrite(dev, uio, flag)
    476       1.1     ragge 	dev_t dev;
    477       1.1     ragge 	struct uio *uio;
    478       1.1     ragge {
    479      1.18  augustss 	struct dhu_softc *sc;
    480      1.18  augustss 	struct tty *tp;
    481       1.1     ragge 
    482       1.5     ragge 	sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    483       1.5     ragge 
    484       1.5     ragge 	tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    485      1.21       eeh 	return ((*tp->t_linesw->l_write)(tp, uio, flag));
    486  1.21.2.2   nathanw }
    487  1.21.2.2   nathanw 
    488  1.21.2.2   nathanw int
    489  1.21.2.2   nathanw dhupoll(dev, events, p)
    490  1.21.2.2   nathanw 	dev_t dev;
    491  1.21.2.2   nathanw 	int events;
    492  1.21.2.2   nathanw 	struct proc *p;
    493  1.21.2.2   nathanw {
    494  1.21.2.2   nathanw 	struct dhu_softc *sc;
    495  1.21.2.2   nathanw 	struct tty *tp;
    496  1.21.2.2   nathanw 
    497  1.21.2.2   nathanw 	sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    498  1.21.2.2   nathanw 
    499  1.21.2.2   nathanw 	tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    500  1.21.2.2   nathanw 	return ((*tp->t_linesw->l_poll)(tp, events, p));
    501       1.1     ragge }
    502       1.1     ragge 
    503       1.1     ragge /*ARGSUSED*/
    504       1.1     ragge int
    505       1.5     ragge dhuioctl(dev, cmd, data, flag, p)
    506       1.1     ragge 	dev_t dev;
    507       1.4     ragge 	u_long cmd;
    508       1.1     ragge 	caddr_t data;
    509       1.1     ragge 	int flag;
    510       1.1     ragge 	struct proc *p;
    511       1.1     ragge {
    512      1.18  augustss 	struct dhu_softc *sc;
    513      1.18  augustss 	struct tty *tp;
    514      1.18  augustss 	int unit, line;
    515       1.1     ragge 	int error;
    516       1.1     ragge 
    517       1.5     ragge 	unit = DHU_M2U(minor(dev));
    518       1.5     ragge 	line = DHU_LINE(minor(dev));
    519       1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    520       1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    521       1.5     ragge 
    522      1.21       eeh 	error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
    523  1.21.2.5   nathanw 	if (error != EPASSTHROUGH)
    524       1.1     ragge 		return (error);
    525  1.21.2.5   nathanw 
    526       1.1     ragge 	error = ttioctl(tp, cmd, data, flag, p);
    527  1.21.2.5   nathanw 	if (error != EPASSTHROUGH)
    528       1.1     ragge 		return (error);
    529       1.1     ragge 
    530       1.1     ragge 	switch (cmd) {
    531       1.1     ragge 
    532       1.1     ragge 	case TIOCSBRK:
    533       1.5     ragge 		(void) dhumctl(sc, line, DML_BRK, DMBIS);
    534       1.1     ragge 		break;
    535       1.1     ragge 
    536       1.1     ragge 	case TIOCCBRK:
    537       1.5     ragge 		(void) dhumctl(sc, line, DML_BRK, DMBIC);
    538       1.1     ragge 		break;
    539       1.1     ragge 
    540       1.1     ragge 	case TIOCSDTR:
    541       1.5     ragge 		(void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS);
    542       1.1     ragge 		break;
    543       1.1     ragge 
    544       1.1     ragge 	case TIOCCDTR:
    545       1.5     ragge 		(void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC);
    546       1.1     ragge 		break;
    547       1.1     ragge 
    548       1.1     ragge 	case TIOCMSET:
    549       1.5     ragge 		(void) dhumctl(sc, line, *(int *)data, DMSET);
    550       1.1     ragge 		break;
    551       1.1     ragge 
    552       1.1     ragge 	case TIOCMBIS:
    553       1.5     ragge 		(void) dhumctl(sc, line, *(int *)data, DMBIS);
    554       1.1     ragge 		break;
    555       1.1     ragge 
    556       1.1     ragge 	case TIOCMBIC:
    557       1.5     ragge 		(void) dhumctl(sc, line, *(int *)data, DMBIC);
    558       1.1     ragge 		break;
    559       1.1     ragge 
    560       1.1     ragge 	case TIOCMGET:
    561       1.5     ragge 		*(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK);
    562       1.1     ragge 		break;
    563       1.1     ragge 
    564       1.1     ragge 	default:
    565  1.21.2.5   nathanw 		return (EPASSTHROUGH);
    566       1.1     ragge 	}
    567       1.1     ragge 	return (0);
    568       1.1     ragge }
    569       1.1     ragge 
    570       1.2     ragge struct tty *
    571       1.5     ragge dhutty(dev)
    572       1.2     ragge         dev_t dev;
    573       1.2     ragge {
    574       1.5     ragge 	struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    575       1.5     ragge 	struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    576       1.2     ragge         return (tp);
    577       1.2     ragge }
    578       1.2     ragge 
    579       1.1     ragge /*ARGSUSED*/
    580       1.6   mycroft void
    581       1.5     ragge dhustop(tp, flag)
    582      1.18  augustss 	struct tty *tp;
    583       1.1     ragge {
    584      1.18  augustss 	struct dhu_softc *sc;
    585      1.18  augustss 	int line;
    586       1.1     ragge 	int s;
    587       1.1     ragge 
    588       1.1     ragge 	s = spltty();
    589       1.1     ragge 
    590       1.5     ragge 	if (tp->t_state & TS_BUSY) {
    591       1.5     ragge 
    592       1.5     ragge 		sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
    593       1.5     ragge 		line = DHU_LINE(minor(tp->t_dev));
    594       1.5     ragge 
    595       1.5     ragge 		if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) {
    596       1.5     ragge 
    597       1.5     ragge 			sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED;
    598       1.2     ragge 
    599      1.15     ragge 			DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    600      1.15     ragge 			DHU_WRITE_WORD(DHU_UBA_LNCTRL,
    601      1.15     ragge 			    DHU_READ_WORD(DHU_UBA_LNCTRL) |
    602      1.15     ragge 			    DHU_LNCTRL_DMA_ABORT);
    603       1.2     ragge 		}
    604       1.1     ragge 
    605       1.1     ragge 		if (!(tp->t_state & TS_TTSTOP))
    606       1.1     ragge 			tp->t_state |= TS_FLUSH;
    607       1.1     ragge 	}
    608       1.1     ragge 	(void) splx(s);
    609       1.1     ragge }
    610       1.1     ragge 
    611       1.1     ragge static void
    612       1.5     ragge dhustart(tp)
    613      1.18  augustss 	struct tty *tp;
    614       1.1     ragge {
    615      1.18  augustss 	struct dhu_softc *sc;
    616      1.18  augustss 	int line, cc;
    617      1.18  augustss 	int addr;
    618       1.1     ragge 	int s;
    619       1.1     ragge 
    620       1.1     ragge 	s = spltty();
    621       1.1     ragge 	if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
    622       1.1     ragge 		goto out;
    623       1.1     ragge 	if (tp->t_outq.c_cc <= tp->t_lowat) {
    624       1.1     ragge 		if (tp->t_state & TS_ASLEEP) {
    625       1.1     ragge 			tp->t_state &= ~TS_ASLEEP;
    626       1.1     ragge 			wakeup((caddr_t)&tp->t_outq);
    627       1.1     ragge 		}
    628       1.1     ragge 		selwakeup(&tp->t_wsel);
    629       1.1     ragge 	}
    630       1.1     ragge 	if (tp->t_outq.c_cc == 0)
    631       1.1     ragge 		goto out;
    632       1.1     ragge 	cc = ndqb(&tp->t_outq, 0);
    633       1.1     ragge 	if (cc == 0)
    634       1.1     ragge 		goto out;
    635       1.1     ragge 
    636       1.1     ragge 	tp->t_state |= TS_BUSY;
    637       1.1     ragge 
    638       1.5     ragge 	sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
    639       1.5     ragge 
    640       1.5     ragge 	line = DHU_LINE(minor(tp->t_dev));
    641       1.1     ragge 
    642      1.15     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    643       1.5     ragge 
    644       1.5     ragge 	sc->sc_dhu[line].dhu_cc = cc;
    645       1.2     ragge 
    646       1.5     ragge 	if (cc == 1) {
    647       1.2     ragge 
    648       1.5     ragge 		sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR;
    649      1.15     ragge 
    650      1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TXCHAR,
    651      1.15     ragge 		    DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf);
    652       1.2     ragge 
    653       1.5     ragge 	} else {
    654       1.5     ragge 
    655       1.5     ragge 		sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING;
    656       1.5     ragge 
    657      1.16     ragge 		addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr +
    658       1.2     ragge 			(tp->t_outq.c_cf - tp->t_outq.c_cs);
    659       1.2     ragge 
    660      1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc);
    661      1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF);
    662      1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) |
    663      1.15     ragge 		    DHU_TBUFAD2_TX_ENABLE);
    664      1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_LNCTRL,
    665      1.15     ragge 		    DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT);
    666      1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFAD2,
    667      1.15     ragge 		    DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START);
    668       1.2     ragge 	}
    669       1.1     ragge out:
    670       1.1     ragge 	(void) splx(s);
    671       1.1     ragge 	return;
    672       1.1     ragge }
    673       1.1     ragge 
    674       1.1     ragge static int
    675       1.5     ragge dhuparam(tp, t)
    676      1.18  augustss 	struct tty *tp;
    677      1.18  augustss 	struct termios *t;
    678       1.1     ragge {
    679       1.5     ragge 	struct dhu_softc *sc;
    680      1.18  augustss 	int cflag = t->c_cflag;
    681       1.1     ragge 	int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab);
    682       1.1     ragge 	int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab);
    683      1.18  augustss 	unsigned lpr, lnctrl;
    684       1.5     ragge 	int unit, line;
    685       1.1     ragge 	int s;
    686       1.1     ragge 
    687       1.5     ragge 	unit = DHU_M2U(minor(tp->t_dev));
    688       1.5     ragge 	line = DHU_LINE(minor(tp->t_dev));
    689       1.5     ragge 
    690       1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    691       1.5     ragge 
    692       1.1     ragge 	/* check requested parameters */
    693       1.1     ragge         if (ospeed < 0 || ispeed < 0)
    694       1.1     ragge                 return (EINVAL);
    695       1.1     ragge 
    696       1.1     ragge         tp->t_ispeed = t->c_ispeed;
    697       1.1     ragge         tp->t_ospeed = t->c_ospeed;
    698       1.1     ragge         tp->t_cflag = cflag;
    699       1.1     ragge 
    700       1.1     ragge 	if (ospeed == 0) {
    701       1.5     ragge 		(void) dhumctl(sc, line, 0, DMSET);	/* hang up line */
    702       1.1     ragge 		return (0);
    703       1.1     ragge 	}
    704       1.1     ragge 
    705       1.1     ragge 	s = spltty();
    706      1.15     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    707       1.1     ragge 
    708       1.1     ragge 	lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ;
    709       1.1     ragge 
    710       1.5     ragge 	switch (cflag & CSIZE) {
    711       1.5     ragge 
    712       1.5     ragge 	case CS5:
    713       1.1     ragge 		lpr |= DHU_LPR_5_BIT_CHAR;
    714       1.1     ragge 		break;
    715       1.5     ragge 
    716       1.5     ragge 	case CS6:
    717       1.1     ragge 		lpr |= DHU_LPR_6_BIT_CHAR;
    718       1.1     ragge 		break;
    719       1.5     ragge 
    720       1.5     ragge 	case CS7:
    721       1.1     ragge 		lpr |= DHU_LPR_7_BIT_CHAR;
    722       1.1     ragge 		break;
    723       1.5     ragge 
    724       1.5     ragge 	default:
    725       1.1     ragge 		lpr |= DHU_LPR_8_BIT_CHAR;
    726       1.1     ragge 		break;
    727       1.1     ragge 	}
    728       1.5     ragge 
    729       1.1     ragge 	if (cflag & PARENB)
    730       1.1     ragge 		lpr |= DHU_LPR_PARENB;
    731       1.1     ragge 	if (!(cflag & PARODD))
    732       1.1     ragge 		lpr |= DHU_LPR_EPAR;
    733       1.1     ragge 	if (cflag & CSTOPB)
    734       1.1     ragge 		lpr |= DHU_LPR_2_STOP;
    735       1.1     ragge 
    736      1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_LPR, lpr);
    737       1.1     ragge 
    738      1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_TBUFAD2,
    739      1.15     ragge 	    DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE);
    740       1.2     ragge 
    741      1.15     ragge 	lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL);
    742       1.2     ragge 
    743       1.1     ragge 	/* Setting LINK.TYPE enables modem signal change interrupts. */
    744       1.1     ragge 
    745       1.2     ragge 	lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE);
    746       1.2     ragge 
    747       1.5     ragge 	/* Enable the auto XON/XOFF feature on the controller */
    748       1.5     ragge 
    749       1.2     ragge 	if (t->c_iflag & IXON)
    750       1.2     ragge 		lnctrl |= DHU_LNCTRL_OAUTO;
    751       1.2     ragge 	else
    752       1.2     ragge 		lnctrl &= ~DHU_LNCTRL_OAUTO;
    753       1.2     ragge 
    754       1.2     ragge 	if (t->c_iflag & IXOFF)
    755       1.2     ragge 		lnctrl |= DHU_LNCTRL_IAUTO;
    756       1.2     ragge 	else
    757       1.2     ragge 		lnctrl &= ~DHU_LNCTRL_IAUTO;
    758       1.2     ragge 
    759      1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl);
    760       1.2     ragge 
    761       1.1     ragge 	(void) splx(s);
    762       1.1     ragge 	return (0);
    763       1.1     ragge }
    764       1.1     ragge 
    765       1.1     ragge static int
    766       1.5     ragge dhuiflow(tp, flag)
    767       1.2     ragge 	struct tty *tp;
    768       1.2     ragge 	int flag;
    769       1.2     ragge {
    770      1.18  augustss 	struct dhu_softc *sc;
    771      1.18  augustss 	int line = DHU_LINE(minor(tp->t_dev));
    772       1.2     ragge 
    773       1.2     ragge 	if (tp->t_cflag & CRTSCTS) {
    774       1.5     ragge 		sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
    775       1.5     ragge 		(void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS));
    776       1.2     ragge 		return (1);
    777       1.2     ragge 	}
    778       1.2     ragge 	return (0);
    779       1.2     ragge }
    780       1.2     ragge 
    781       1.2     ragge static unsigned
    782       1.5     ragge dhumctl(sc, line, bits, how)
    783       1.5     ragge 	struct dhu_softc *sc;
    784       1.5     ragge 	int line, bits, how;
    785       1.1     ragge {
    786      1.18  augustss 	unsigned status;
    787      1.18  augustss 	unsigned lnctrl;
    788      1.18  augustss 	unsigned mbits;
    789       1.1     ragge 	int s;
    790       1.1     ragge 
    791       1.1     ragge 	s = spltty();
    792       1.1     ragge 
    793      1.15     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    794       1.1     ragge 
    795       1.1     ragge 	mbits = 0;
    796       1.1     ragge 
    797       1.1     ragge 	/* external signals as seen from the port */
    798       1.1     ragge 
    799      1.15     ragge 	status = DHU_READ_WORD(DHU_UBA_STAT);
    800       1.1     ragge 
    801       1.2     ragge 	if (status & DHU_STAT_CTS)
    802       1.1     ragge 		mbits |= DML_CTS;
    803       1.1     ragge 
    804       1.2     ragge 	if (status & DHU_STAT_DCD)
    805       1.1     ragge 		mbits |= DML_DCD;
    806       1.1     ragge 
    807       1.2     ragge 	if (status & DHU_STAT_DSR)
    808       1.1     ragge 		mbits |= DML_DSR;
    809       1.1     ragge 
    810       1.2     ragge 	if (status & DHU_STAT_RI)
    811       1.1     ragge 		mbits |= DML_RI;
    812       1.1     ragge 
    813       1.1     ragge 	/* internal signals/state delivered to port */
    814       1.1     ragge 
    815      1.15     ragge 	lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL);
    816       1.1     ragge 
    817       1.2     ragge 	if (lnctrl & DHU_LNCTRL_RTS)
    818       1.1     ragge 		mbits |= DML_RTS;
    819       1.1     ragge 
    820       1.2     ragge 	if (lnctrl & DHU_LNCTRL_DTR)
    821       1.1     ragge 		mbits |= DML_DTR;
    822       1.1     ragge 
    823       1.2     ragge 	if (lnctrl & DHU_LNCTRL_BREAK)
    824       1.1     ragge 		mbits |= DML_BRK;
    825       1.1     ragge 
    826       1.5     ragge 	switch (how) {
    827       1.5     ragge 
    828       1.5     ragge 	case DMSET:
    829       1.1     ragge 		mbits = bits;
    830       1.1     ragge 		break;
    831       1.1     ragge 
    832       1.5     ragge 	case DMBIS:
    833       1.1     ragge 		mbits |= bits;
    834       1.1     ragge 		break;
    835       1.1     ragge 
    836       1.5     ragge 	case DMBIC:
    837       1.1     ragge 		mbits &= ~bits;
    838       1.1     ragge 		break;
    839       1.1     ragge 
    840       1.5     ragge 	case DMGET:
    841       1.1     ragge 		(void) splx(s);
    842       1.1     ragge 		return (mbits);
    843       1.1     ragge 	}
    844       1.1     ragge 
    845       1.1     ragge 	if (mbits & DML_RTS)
    846       1.2     ragge 		lnctrl |= DHU_LNCTRL_RTS;
    847       1.1     ragge 	else
    848       1.2     ragge 		lnctrl &= ~DHU_LNCTRL_RTS;
    849       1.1     ragge 
    850       1.1     ragge 	if (mbits & DML_DTR)
    851       1.2     ragge 		lnctrl |= DHU_LNCTRL_DTR;
    852       1.1     ragge 	else
    853       1.2     ragge 		lnctrl &= ~DHU_LNCTRL_DTR;
    854       1.1     ragge 
    855       1.1     ragge 	if (mbits & DML_BRK)
    856       1.2     ragge 		lnctrl |= DHU_LNCTRL_BREAK;
    857       1.1     ragge 	else
    858       1.2     ragge 		lnctrl &= ~DHU_LNCTRL_BREAK;
    859       1.2     ragge 
    860      1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl);
    861       1.1     ragge 
    862       1.1     ragge 	(void) splx(s);
    863       1.1     ragge 	return (mbits);
    864       1.1     ragge }
    865