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dhu.c revision 1.26
      1  1.26    atatat /*	$NetBSD: dhu.c,v 1.26 2002/03/17 19:41:01 atatat Exp $	*/
      2   1.1     ragge /*
      3   1.1     ragge  * Copyright (c) 1996  Ken C. Wellsch.  All rights reserved.
      4   1.1     ragge  * Copyright (c) 1992, 1993
      5   1.1     ragge  *	The Regents of the University of California.  All rights reserved.
      6   1.1     ragge  *
      7   1.1     ragge  * This code is derived from software contributed to Berkeley by
      8   1.1     ragge  * Ralph Campbell and Rick Macklem.
      9   1.1     ragge  *
     10   1.1     ragge  * Redistribution and use in source and binary forms, with or without
     11   1.1     ragge  * modification, are permitted provided that the following conditions
     12   1.1     ragge  * are met:
     13   1.1     ragge  * 1. Redistributions of source code must retain the above copyright
     14   1.1     ragge  *    notice, this list of conditions and the following disclaimer.
     15   1.1     ragge  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1     ragge  *    notice, this list of conditions and the following disclaimer in the
     17   1.1     ragge  *    documentation and/or other materials provided with the distribution.
     18   1.1     ragge  * 3. All advertising materials mentioning features or use of this software
     19   1.1     ragge  *    must display the following acknowledgement:
     20   1.1     ragge  *	This product includes software developed by the University of
     21   1.1     ragge  *	California, Berkeley and its contributors.
     22   1.1     ragge  * 4. Neither the name of the University nor the names of its contributors
     23   1.1     ragge  *    may be used to endorse or promote products derived from this software
     24   1.1     ragge  *    without specific prior written permission.
     25   1.1     ragge  *
     26   1.1     ragge  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27   1.1     ragge  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28   1.1     ragge  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29   1.1     ragge  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30   1.1     ragge  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31   1.1     ragge  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32   1.1     ragge  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33   1.1     ragge  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34   1.1     ragge  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35   1.1     ragge  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36   1.1     ragge  * SUCH DAMAGE.
     37   1.1     ragge  */
     38  1.25     lukem 
     39  1.25     lukem #include <sys/cdefs.h>
     40  1.26    atatat __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.26 2002/03/17 19:41:01 atatat Exp $");
     41   1.1     ragge 
     42   1.1     ragge #include <sys/param.h>
     43   1.1     ragge #include <sys/systm.h>
     44   1.1     ragge #include <sys/ioctl.h>
     45   1.1     ragge #include <sys/tty.h>
     46   1.1     ragge #include <sys/proc.h>
     47   1.1     ragge #include <sys/map.h>
     48   1.1     ragge #include <sys/buf.h>
     49   1.1     ragge #include <sys/conf.h>
     50   1.1     ragge #include <sys/file.h>
     51   1.1     ragge #include <sys/uio.h>
     52   1.1     ragge #include <sys/kernel.h>
     53   1.1     ragge #include <sys/syslog.h>
     54   1.1     ragge #include <sys/device.h>
     55   1.1     ragge 
     56  1.15     ragge #include <machine/bus.h>
     57  1.13     ragge #include <machine/scb.h>
     58   1.1     ragge 
     59  1.15     ragge #include <dev/qbus/ubavar.h>
     60  1.15     ragge 
     61  1.15     ragge #include <dev/qbus/dhureg.h>
     62  1.15     ragge 
     63  1.15     ragge #include "ioconf.h"
     64   1.1     ragge 
     65   1.5     ragge /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */
     66   1.1     ragge 
     67   1.5     ragge #define	NDHULINE 	16
     68   1.2     ragge 
     69   1.5     ragge #define DHU_M2U(c)	((c)>>4)	/* convert minor(dev) to unit # */
     70   1.5     ragge #define DHU_LINE(u)	((u)&0xF)	/* extract line # from minor(dev) */
     71   1.2     ragge 
     72   1.5     ragge struct	dhu_softc {
     73   1.5     ragge 	struct	device	sc_dev;		/* Device struct used by config */
     74  1.19      matt 	struct	evcnt	sc_rintrcnt;	/* Interrupt statistics */
     75  1.19      matt 	struct	evcnt	sc_tintrcnt;	/* Interrupt statistics */
     76   1.5     ragge 	int		sc_type;	/* controller type, DHU or DHV */
     77  1.15     ragge 	bus_space_tag_t	sc_iot;
     78  1.15     ragge 	bus_space_handle_t sc_ioh;
     79  1.16     ragge 	bus_dma_tag_t	sc_dmat;
     80   1.5     ragge 	struct {
     81   1.5     ragge 		struct	tty *dhu_tty;	/* what we work on */
     82  1.16     ragge 		bus_dmamap_t dhu_dmah;
     83   1.5     ragge 		int	dhu_state;	/* to manage TX output status */
     84   1.5     ragge 		short	dhu_cc;		/* character count on TX */
     85   1.5     ragge 		short	dhu_modem;	/* modem bits state */
     86   1.5     ragge 	} sc_dhu[NDHULINE];
     87   1.1     ragge };
     88   1.1     ragge 
     89   1.5     ragge #define IS_DHU			16	/* Unibus DHU-11 board linecount */
     90   1.5     ragge #define IS_DHV			 8	/* Q-bus DHV-11 or DHQ-11 */
     91   1.2     ragge 
     92   1.2     ragge #define STATE_IDLE		000	/* no current output in progress */
     93   1.2     ragge #define STATE_DMA_RUNNING	001	/* DMA TX in progress */
     94   1.2     ragge #define STATE_DMA_STOPPED	002	/* DMA TX was aborted */
     95   1.2     ragge #define STATE_TX_ONE_CHAR	004	/* did a single char directly */
     96   1.2     ragge 
     97   1.2     ragge /* Flags used to monitor modem bits, make them understood outside driver */
     98   1.2     ragge 
     99   1.2     ragge #define DML_DTR		TIOCM_DTR
    100   1.2     ragge #define DML_RTS		TIOCM_RTS
    101   1.2     ragge #define DML_CTS		TIOCM_CTS
    102   1.2     ragge #define DML_DCD		TIOCM_CD
    103   1.2     ragge #define DML_RI		TIOCM_RI
    104   1.2     ragge #define DML_DSR		TIOCM_DSR
    105   1.2     ragge #define DML_BRK		0100000		/* no equivalent, we will mask */
    106   1.2     ragge 
    107  1.15     ragge #define DHU_READ_WORD(reg) \
    108  1.15     ragge 	bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg)
    109  1.15     ragge #define DHU_WRITE_WORD(reg, val) \
    110  1.15     ragge 	bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val)
    111  1.15     ragge #define DHU_READ_BYTE(reg) \
    112  1.15     ragge 	bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg)
    113  1.15     ragge #define DHU_WRITE_BYTE(reg, val) \
    114  1.15     ragge 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val)
    115  1.15     ragge 
    116  1.15     ragge 
    117   1.1     ragge /*  On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */
    118   1.1     ragge /* a baud rate from the same group.  So limiting to B is likely */
    119   1.1     ragge /* best, although clone boards like the ABLE QHV allow all settings. */
    120   1.1     ragge 
    121   1.5     ragge static struct speedtab dhuspeedtab[] = {
    122   1.1     ragge   {       0,	0		},	/* Groups  */
    123   1.1     ragge   {      50,	DHU_LPR_B50	},	/* A	   */
    124   1.1     ragge   {      75,	DHU_LPR_B75	},	/* 	 B */
    125   1.1     ragge   {     110,	DHU_LPR_B110	},	/* A and B */
    126   1.1     ragge   {     134,	DHU_LPR_B134	},	/* A and B */
    127   1.1     ragge   {     150,	DHU_LPR_B150	},	/* 	 B */
    128   1.1     ragge   {     300,	DHU_LPR_B300	},	/* A and B */
    129   1.1     ragge   {     600,	DHU_LPR_B600	},	/* A and B */
    130   1.1     ragge   {    1200,	DHU_LPR_B1200	},	/* A and B */
    131   1.1     ragge   {    1800,	DHU_LPR_B1800	},	/* 	 B */
    132   1.1     ragge   {    2000,	DHU_LPR_B2000	},	/* 	 B */
    133   1.1     ragge   {    2400,	DHU_LPR_B2400	},	/* A and B */
    134   1.1     ragge   {    4800,	DHU_LPR_B4800	},	/* A and B */
    135   1.1     ragge   {    7200,	DHU_LPR_B7200	},	/* A	   */
    136   1.1     ragge   {    9600,	DHU_LPR_B9600	},	/* A and B */
    137   1.1     ragge   {   19200,	DHU_LPR_B19200	},	/* 	 B */
    138   1.1     ragge   {   38400,	DHU_LPR_B38400	},	/* A	   */
    139   1.1     ragge   {      -1,	-1		}
    140   1.1     ragge };
    141   1.1     ragge 
    142  1.11     ragge static int	dhu_match __P((struct device *, struct cfdata *, void *));
    143   1.1     ragge static void	dhu_attach __P((struct device *, struct device *, void *));
    144  1.17      matt static	void	dhurint __P((void *));
    145  1.17      matt static	void	dhuxint __P((void *));
    146   1.2     ragge static	void	dhustart __P((struct tty *));
    147   1.2     ragge static	int	dhuparam __P((struct tty *, struct termios *));
    148   1.2     ragge static	int	dhuiflow __P((struct tty *, int));
    149   1.5     ragge static unsigned	dhumctl __P((struct dhu_softc *,int, int, int));
    150  1.24     ragge 
    151  1.24     ragge cdev_decl(dhu);
    152   1.1     ragge 
    153   1.5     ragge struct	cfattach dhu_ca = {
    154   1.5     ragge 	sizeof(struct dhu_softc), dhu_match, dhu_attach
    155   1.5     ragge };
    156  1.10   thorpej 
    157   1.1     ragge /* Autoconfig handles: setup the controller to interrupt, */
    158   1.1     ragge /* then complete the housecleaning for full operation */
    159   1.1     ragge 
    160   1.1     ragge static int
    161  1.11     ragge dhu_match(parent, cf, aux)
    162   1.1     ragge         struct device *parent;
    163  1.11     ragge 	struct cfdata *cf;
    164  1.11     ragge         void *aux;
    165   1.1     ragge {
    166   1.1     ragge 	struct uba_attach_args *ua = aux;
    167  1.18  augustss 	int n;
    168   1.1     ragge 
    169   1.2     ragge 	/* Reset controller to initialize, enable TX/RX interrupts */
    170   1.1     ragge 	/* to catch floating vector info elsewhere when completed */
    171   1.1     ragge 
    172  1.15     ragge 	bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR,
    173  1.15     ragge 	    DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE);
    174   1.1     ragge 
    175   1.1     ragge 	/* Now wait up to 3 seconds for self-test to complete. */
    176   1.1     ragge 
    177   1.1     ragge 	for (n = 0; n < 300; n++) {
    178   1.1     ragge 		DELAY(10000);
    179  1.15     ragge 		if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) &
    180  1.15     ragge 		    DHU_CSR_MASTER_RESET) == 0)
    181   1.1     ragge 			break;
    182   1.1     ragge 	}
    183   1.1     ragge 
    184   1.1     ragge 	/* If the RESET did not clear after 3 seconds, */
    185   1.1     ragge 	/* the controller must be broken. */
    186   1.1     ragge 
    187   1.2     ragge 	if (n >= 300)
    188   1.1     ragge 		return 0;
    189   1.1     ragge 
    190   1.1     ragge 	/* Check whether diagnostic run has signalled a failure. */
    191   1.1     ragge 
    192  1.15     ragge 	if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) &
    193  1.15     ragge 	    DHU_CSR_DIAG_FAIL) != 0)
    194   1.1     ragge 		return 0;
    195   1.1     ragge 
    196   1.1     ragge        	return 1;
    197   1.1     ragge }
    198   1.1     ragge 
    199   1.1     ragge static void
    200   1.5     ragge dhu_attach(parent, self, aux)
    201   1.1     ragge         struct device *parent, *self;
    202   1.1     ragge         void *aux;
    203   1.1     ragge {
    204  1.18  augustss 	struct dhu_softc *sc = (void *)self;
    205  1.18  augustss 	struct uba_attach_args *ua = aux;
    206  1.18  augustss 	unsigned c;
    207  1.18  augustss 	int n, i;
    208   1.1     ragge 
    209  1.15     ragge 	sc->sc_iot = ua->ua_iot;
    210  1.15     ragge 	sc->sc_ioh = ua->ua_ioh;
    211  1.16     ragge 	sc->sc_dmat = ua->ua_dmat;
    212   1.1     ragge 	/* Process the 8 bytes of diagnostic info put into */
    213   1.1     ragge 	/* the FIFO following the master reset operation. */
    214   1.1     ragge 
    215   1.8  christos 	printf("\n%s:", self->dv_xname);
    216   1.1     ragge 	for (n = 0; n < 8; n++) {
    217  1.15     ragge 		c = DHU_READ_WORD(DHU_UBA_RBUF);
    218   1.1     ragge 
    219   1.2     ragge 		if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) {
    220   1.2     ragge 			if ((c&0200) == 0000)
    221   1.8  christos 				printf(" rom(%d) version %d",
    222   1.1     ragge 					((c>>1)&01), ((c>>2)&037));
    223   1.2     ragge 			else if (((c>>2)&07) != 0)
    224   1.8  christos 				printf(" diag-error(proc%d)=%x",
    225   1.1     ragge 					((c>>1)&01), ((c>>2)&07));
    226   1.1     ragge 		}
    227   1.1     ragge 	}
    228   1.1     ragge 
    229  1.15     ragge 	c = DHU_READ_WORD(DHU_UBA_STAT);
    230   1.2     ragge 
    231   1.5     ragge 	sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV;
    232  1.15     ragge 	printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V");
    233   1.1     ragge 
    234  1.16     ragge 	for (i = 0; i < sc->sc_type; i++) {
    235  1.16     ragge 		struct tty *tp;
    236  1.16     ragge 		tp = sc->sc_dhu[i].dhu_tty = ttymalloc();
    237  1.16     ragge 		sc->sc_dhu[i].dhu_state = STATE_IDLE;
    238  1.16     ragge 		bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1,
    239  1.16     ragge 		    tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT,
    240  1.16     ragge 		    &sc->sc_dhu[i].dhu_dmah);
    241  1.16     ragge 		bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah,
    242  1.16     ragge 		    tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT);
    243  1.16     ragge 
    244  1.16     ragge 	}
    245  1.16     ragge 
    246  1.17      matt 	/* Now establish RX & TX interrupt handlers */
    247  1.17      matt 
    248  1.19      matt 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
    249  1.19      matt 		dhurint, sc, &sc->sc_rintrcnt);
    250  1.19      matt 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4,
    251  1.19      matt 		dhuxint, sc, &sc->sc_tintrcnt);
    252  1.20      matt 	evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
    253  1.20      matt 		sc->sc_dev.dv_xname, "rintr");
    254  1.20      matt 	evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
    255  1.20      matt 		sc->sc_dev.dv_xname, "tintr");
    256   1.1     ragge }
    257   1.1     ragge 
    258   1.2     ragge /* Receiver Interrupt */
    259   1.2     ragge 
    260   1.1     ragge static void
    261  1.17      matt dhurint(arg)
    262  1.17      matt 	void *arg;
    263   1.1     ragge {
    264  1.17      matt 	struct	dhu_softc *sc = arg;
    265  1.18  augustss 	struct tty *tp;
    266  1.18  augustss 	int cc, line;
    267  1.18  augustss 	unsigned c, delta;
    268   1.1     ragge 	int overrun = 0;
    269   1.2     ragge 
    270  1.15     ragge 	while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) {
    271   1.1     ragge 
    272   1.1     ragge 		/* Ignore diagnostic FIFO entries. */
    273   1.1     ragge 
    274   1.5     ragge 		if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE)
    275   1.1     ragge 			continue;
    276   1.1     ragge 
    277   1.5     ragge 		cc = c & 0xFF;
    278   1.5     ragge 		line = DHU_LINE(c>>8);
    279   1.5     ragge 		tp = sc->sc_dhu[line].dhu_tty;
    280   1.1     ragge 
    281   1.1     ragge 		/* LINK.TYPE is set so we get modem control FIFO entries */
    282   1.1     ragge 
    283   1.1     ragge 		if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) {
    284   1.2     ragge 			c = (c << 8);
    285   1.1     ragge 			/* Do MDMBUF flow control, wakeup sleeping opens */
    286   1.1     ragge 			if (c & DHU_STAT_DCD) {
    287   1.1     ragge 				if (!(tp->t_state & TS_CARR_ON))
    288  1.21       eeh 				    (void)(*tp->t_linesw->l_modem)(tp, 1);
    289   1.1     ragge 			}
    290   1.1     ragge 			else if ((tp->t_state & TS_CARR_ON) &&
    291  1.21       eeh 				(*tp->t_linesw->l_modem)(tp, 0) == 0)
    292   1.5     ragge 					(void) dhumctl(sc, line, 0, DMSET);
    293   1.2     ragge 
    294   1.2     ragge 			/* Do CRTSCTS flow control */
    295   1.5     ragge 			delta = c ^ sc->sc_dhu[line].dhu_modem;
    296   1.5     ragge 			sc->sc_dhu[line].dhu_modem = c;
    297   1.2     ragge 			if ((delta & DHU_STAT_CTS) &&
    298   1.2     ragge 			    (tp->t_state & TS_ISOPEN) &&
    299   1.2     ragge 			    (tp->t_cflag & CRTSCTS)) {
    300   1.2     ragge 				if (c & DHU_STAT_CTS) {
    301   1.2     ragge 					tp->t_state &= ~TS_TTSTOP;
    302   1.5     ragge 					ttstart(tp);
    303   1.2     ragge 				} else {
    304   1.2     ragge 					tp->t_state |= TS_TTSTOP;
    305   1.5     ragge 					dhustop(tp, 0);
    306   1.2     ragge 				}
    307   1.2     ragge 			}
    308   1.2     ragge 			continue;
    309   1.1     ragge 		}
    310   1.1     ragge 
    311   1.5     ragge 		if (!(tp->t_state & TS_ISOPEN)) {
    312   1.5     ragge 			wakeup((caddr_t)&tp->t_rawq);
    313   1.5     ragge 			continue;
    314   1.5     ragge 		}
    315   1.5     ragge 
    316   1.1     ragge 		if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) {
    317   1.5     ragge 			log(LOG_WARNING, "%s: silo overflow, line %d\n",
    318   1.5     ragge 				sc->sc_dev.dv_xname, line);
    319   1.1     ragge 			overrun = 1;
    320   1.1     ragge 		}
    321   1.1     ragge 		/* A BREAK key will appear as a NULL with a framing error */
    322   1.1     ragge 		if (c & DHU_RBUF_FRAMING_ERR)
    323   1.1     ragge 			cc |= TTY_FE;
    324   1.1     ragge 		if (c & DHU_RBUF_PARITY_ERR)
    325   1.1     ragge 			cc |= TTY_PE;
    326   1.1     ragge 
    327  1.21       eeh 		(*tp->t_linesw->l_rint)(cc, tp);
    328   1.1     ragge 	}
    329   1.1     ragge }
    330   1.1     ragge 
    331   1.1     ragge /* Transmitter Interrupt */
    332   1.1     ragge 
    333   1.1     ragge static void
    334  1.17      matt dhuxint(arg)
    335  1.17      matt 	void *arg;
    336   1.1     ragge {
    337  1.18  augustss 	struct	dhu_softc *sc = arg;
    338  1.18  augustss 	struct tty *tp;
    339  1.18  augustss 	int line;
    340   1.2     ragge 
    341  1.15     ragge 	line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI));
    342   1.1     ragge 
    343   1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    344   1.2     ragge 
    345   1.1     ragge 	tp->t_state &= ~TS_BUSY;
    346   1.1     ragge 	if (tp->t_state & TS_FLUSH)
    347   1.1     ragge 		tp->t_state &= ~TS_FLUSH;
    348   1.1     ragge 	else {
    349   1.5     ragge 		if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED)
    350  1.15     ragge 			sc->sc_dhu[line].dhu_cc -=
    351  1.15     ragge 			DHU_READ_WORD(DHU_UBA_TBUFCNT);
    352   1.5     ragge 		ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc);
    353   1.5     ragge 		sc->sc_dhu[line].dhu_cc = 0;
    354   1.1     ragge 	}
    355   1.1     ragge 
    356   1.5     ragge 	sc->sc_dhu[line].dhu_state = STATE_IDLE;
    357   1.2     ragge 
    358  1.22     enami 	(*tp->t_linesw->l_start)(tp);
    359   1.1     ragge }
    360   1.1     ragge 
    361   1.1     ragge int
    362   1.5     ragge dhuopen(dev, flag, mode, p)
    363   1.1     ragge 	dev_t dev;
    364   1.1     ragge 	int flag, mode;
    365   1.1     ragge 	struct proc *p;
    366   1.1     ragge {
    367  1.18  augustss 	struct tty *tp;
    368  1.18  augustss 	int unit, line;
    369   1.5     ragge 	struct dhu_softc *sc;
    370   1.1     ragge 	int s, error = 0;
    371   1.1     ragge 
    372   1.5     ragge 	unit = DHU_M2U(minor(dev));
    373   1.5     ragge 	line = DHU_LINE(minor(dev));
    374   1.5     ragge 
    375   1.5     ragge 	if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL)
    376   1.1     ragge 		return (ENXIO);
    377   1.5     ragge 
    378   1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    379   1.5     ragge 
    380   1.5     ragge 	if (line >= sc->sc_type)
    381   1.5     ragge 		return ENXIO;
    382   1.5     ragge 
    383  1.16     ragge 	s = spltty();
    384  1.16     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    385  1.16     ragge 	sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT);
    386  1.16     ragge 	(void) splx(s);
    387  1.16     ragge 
    388   1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    389   1.5     ragge 
    390   1.2     ragge 	tp->t_oproc   = dhustart;
    391   1.2     ragge 	tp->t_param   = dhuparam;
    392   1.2     ragge 	tp->t_hwiflow = dhuiflow;
    393   1.1     ragge 	tp->t_dev = dev;
    394   1.1     ragge 	if ((tp->t_state & TS_ISOPEN) == 0) {
    395   1.1     ragge 		ttychars(tp);
    396   1.2     ragge 		if (tp->t_ispeed == 0) {
    397   1.2     ragge 			tp->t_iflag = TTYDEF_IFLAG;
    398   1.2     ragge 			tp->t_oflag = TTYDEF_OFLAG;
    399   1.2     ragge 			tp->t_cflag = TTYDEF_CFLAG;
    400   1.2     ragge 			tp->t_lflag = TTYDEF_LFLAG;
    401   1.2     ragge 			tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
    402   1.2     ragge 		}
    403   1.1     ragge 		(void) dhuparam(tp, &tp->t_termios);
    404   1.1     ragge 		ttsetwater(tp);
    405   1.1     ragge 	} else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0)
    406   1.1     ragge 		return (EBUSY);
    407   1.1     ragge 	/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
    408   1.5     ragge 	if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD)
    409   1.1     ragge 		tp->t_state |= TS_CARR_ON;
    410   1.1     ragge 	s = spltty();
    411   1.1     ragge 	while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
    412   1.1     ragge 	       !(tp->t_state & TS_CARR_ON)) {
    413  1.12     ragge 		tp->t_wopen++;
    414   1.1     ragge 		error = ttysleep(tp, (caddr_t)&tp->t_rawq,
    415   1.1     ragge 				TTIPRI | PCATCH, ttopen, 0);
    416  1.12     ragge 		tp->t_wopen--;
    417   1.1     ragge 		if (error)
    418   1.1     ragge 			break;
    419   1.1     ragge 	}
    420   1.1     ragge 	(void) splx(s);
    421   1.1     ragge 	if (error)
    422   1.1     ragge 		return (error);
    423  1.21       eeh 	return ((*tp->t_linesw->l_open)(dev, tp));
    424   1.1     ragge }
    425   1.1     ragge 
    426   1.1     ragge /*ARGSUSED*/
    427   1.1     ragge int
    428   1.5     ragge dhuclose(dev, flag, mode, p)
    429   1.1     ragge 	dev_t dev;
    430   1.1     ragge 	int flag, mode;
    431   1.1     ragge 	struct proc *p;
    432   1.1     ragge {
    433  1.18  augustss 	struct tty *tp;
    434  1.18  augustss 	int unit, line;
    435   1.5     ragge 	struct dhu_softc *sc;
    436   1.5     ragge 
    437   1.5     ragge 	unit = DHU_M2U(minor(dev));
    438   1.5     ragge 	line = DHU_LINE(minor(dev));
    439   1.1     ragge 
    440   1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    441   1.5     ragge 
    442   1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    443   1.1     ragge 
    444  1.21       eeh 	(*tp->t_linesw->l_close)(tp, flag);
    445   1.1     ragge 
    446   1.1     ragge 	/* Make sure a BREAK state is not left enabled. */
    447   1.1     ragge 
    448   1.5     ragge 	(void) dhumctl(sc, line, DML_BRK, DMBIC);
    449   1.1     ragge 
    450   1.1     ragge 	/* Do a hangup if so required. */
    451   1.1     ragge 
    452  1.12     ragge 	if ((tp->t_cflag & HUPCL) || tp->t_wopen ||
    453   1.1     ragge 	    !(tp->t_state & TS_ISOPEN))
    454   1.5     ragge 		(void) dhumctl(sc, line, 0, DMSET);
    455   1.1     ragge 
    456   1.1     ragge 	return (ttyclose(tp));
    457   1.1     ragge }
    458   1.1     ragge 
    459   1.1     ragge int
    460   1.5     ragge dhuread(dev, uio, flag)
    461   1.1     ragge 	dev_t dev;
    462   1.1     ragge 	struct uio *uio;
    463   1.1     ragge {
    464  1.18  augustss 	struct dhu_softc *sc;
    465  1.18  augustss 	struct tty *tp;
    466   1.1     ragge 
    467   1.5     ragge 	sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    468   1.5     ragge 
    469   1.5     ragge 	tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    470  1.21       eeh 	return ((*tp->t_linesw->l_read)(tp, uio, flag));
    471   1.1     ragge }
    472   1.1     ragge 
    473   1.1     ragge int
    474   1.5     ragge dhuwrite(dev, uio, flag)
    475   1.1     ragge 	dev_t dev;
    476   1.1     ragge 	struct uio *uio;
    477   1.1     ragge {
    478  1.18  augustss 	struct dhu_softc *sc;
    479  1.18  augustss 	struct tty *tp;
    480   1.1     ragge 
    481   1.5     ragge 	sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    482   1.5     ragge 
    483   1.5     ragge 	tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    484  1.21       eeh 	return ((*tp->t_linesw->l_write)(tp, uio, flag));
    485  1.23       scw }
    486  1.23       scw 
    487  1.23       scw int
    488  1.23       scw dhupoll(dev, events, p)
    489  1.23       scw 	dev_t dev;
    490  1.23       scw 	int events;
    491  1.23       scw 	struct proc *p;
    492  1.23       scw {
    493  1.23       scw 	struct dhu_softc *sc;
    494  1.23       scw 	struct tty *tp;
    495  1.23       scw 
    496  1.23       scw 	sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    497  1.23       scw 
    498  1.23       scw 	tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    499  1.23       scw 	return ((*tp->t_linesw->l_poll)(tp, events, p));
    500   1.1     ragge }
    501   1.1     ragge 
    502   1.1     ragge /*ARGSUSED*/
    503   1.1     ragge int
    504   1.5     ragge dhuioctl(dev, cmd, data, flag, p)
    505   1.1     ragge 	dev_t dev;
    506   1.4     ragge 	u_long cmd;
    507   1.1     ragge 	caddr_t data;
    508   1.1     ragge 	int flag;
    509   1.1     ragge 	struct proc *p;
    510   1.1     ragge {
    511  1.18  augustss 	struct dhu_softc *sc;
    512  1.18  augustss 	struct tty *tp;
    513  1.18  augustss 	int unit, line;
    514   1.1     ragge 	int error;
    515   1.1     ragge 
    516   1.5     ragge 	unit = DHU_M2U(minor(dev));
    517   1.5     ragge 	line = DHU_LINE(minor(dev));
    518   1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    519   1.5     ragge 	tp = sc->sc_dhu[line].dhu_tty;
    520   1.5     ragge 
    521  1.21       eeh 	error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
    522  1.26    atatat 	if (error != EPASSTHROUGH)
    523   1.1     ragge 		return (error);
    524  1.26    atatat 
    525   1.1     ragge 	error = ttioctl(tp, cmd, data, flag, p);
    526  1.26    atatat 	if (error != EPASSTHROUGH)
    527   1.1     ragge 		return (error);
    528   1.1     ragge 
    529   1.1     ragge 	switch (cmd) {
    530   1.1     ragge 
    531   1.1     ragge 	case TIOCSBRK:
    532   1.5     ragge 		(void) dhumctl(sc, line, DML_BRK, DMBIS);
    533   1.1     ragge 		break;
    534   1.1     ragge 
    535   1.1     ragge 	case TIOCCBRK:
    536   1.5     ragge 		(void) dhumctl(sc, line, DML_BRK, DMBIC);
    537   1.1     ragge 		break;
    538   1.1     ragge 
    539   1.1     ragge 	case TIOCSDTR:
    540   1.5     ragge 		(void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS);
    541   1.1     ragge 		break;
    542   1.1     ragge 
    543   1.1     ragge 	case TIOCCDTR:
    544   1.5     ragge 		(void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC);
    545   1.1     ragge 		break;
    546   1.1     ragge 
    547   1.1     ragge 	case TIOCMSET:
    548   1.5     ragge 		(void) dhumctl(sc, line, *(int *)data, DMSET);
    549   1.1     ragge 		break;
    550   1.1     ragge 
    551   1.1     ragge 	case TIOCMBIS:
    552   1.5     ragge 		(void) dhumctl(sc, line, *(int *)data, DMBIS);
    553   1.1     ragge 		break;
    554   1.1     ragge 
    555   1.1     ragge 	case TIOCMBIC:
    556   1.5     ragge 		(void) dhumctl(sc, line, *(int *)data, DMBIC);
    557   1.1     ragge 		break;
    558   1.1     ragge 
    559   1.1     ragge 	case TIOCMGET:
    560   1.5     ragge 		*(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK);
    561   1.1     ragge 		break;
    562   1.1     ragge 
    563   1.1     ragge 	default:
    564  1.26    atatat 		return (EPASSTHROUGH);
    565   1.1     ragge 	}
    566   1.1     ragge 	return (0);
    567   1.1     ragge }
    568   1.1     ragge 
    569   1.2     ragge struct tty *
    570   1.5     ragge dhutty(dev)
    571   1.2     ragge         dev_t dev;
    572   1.2     ragge {
    573   1.5     ragge 	struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))];
    574   1.5     ragge 	struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty;
    575   1.2     ragge         return (tp);
    576   1.2     ragge }
    577   1.2     ragge 
    578   1.1     ragge /*ARGSUSED*/
    579   1.6   mycroft void
    580   1.5     ragge dhustop(tp, flag)
    581  1.18  augustss 	struct tty *tp;
    582   1.1     ragge {
    583  1.18  augustss 	struct dhu_softc *sc;
    584  1.18  augustss 	int line;
    585   1.1     ragge 	int s;
    586   1.1     ragge 
    587   1.1     ragge 	s = spltty();
    588   1.1     ragge 
    589   1.5     ragge 	if (tp->t_state & TS_BUSY) {
    590   1.5     ragge 
    591   1.5     ragge 		sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
    592   1.5     ragge 		line = DHU_LINE(minor(tp->t_dev));
    593   1.5     ragge 
    594   1.5     ragge 		if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) {
    595   1.5     ragge 
    596   1.5     ragge 			sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED;
    597   1.2     ragge 
    598  1.15     ragge 			DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    599  1.15     ragge 			DHU_WRITE_WORD(DHU_UBA_LNCTRL,
    600  1.15     ragge 			    DHU_READ_WORD(DHU_UBA_LNCTRL) |
    601  1.15     ragge 			    DHU_LNCTRL_DMA_ABORT);
    602   1.2     ragge 		}
    603   1.1     ragge 
    604   1.1     ragge 		if (!(tp->t_state & TS_TTSTOP))
    605   1.1     ragge 			tp->t_state |= TS_FLUSH;
    606   1.1     ragge 	}
    607   1.1     ragge 	(void) splx(s);
    608   1.1     ragge }
    609   1.1     ragge 
    610   1.1     ragge static void
    611   1.5     ragge dhustart(tp)
    612  1.18  augustss 	struct tty *tp;
    613   1.1     ragge {
    614  1.18  augustss 	struct dhu_softc *sc;
    615  1.18  augustss 	int line, cc;
    616  1.18  augustss 	int addr;
    617   1.1     ragge 	int s;
    618   1.1     ragge 
    619   1.1     ragge 	s = spltty();
    620   1.1     ragge 	if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
    621   1.1     ragge 		goto out;
    622   1.1     ragge 	if (tp->t_outq.c_cc <= tp->t_lowat) {
    623   1.1     ragge 		if (tp->t_state & TS_ASLEEP) {
    624   1.1     ragge 			tp->t_state &= ~TS_ASLEEP;
    625   1.1     ragge 			wakeup((caddr_t)&tp->t_outq);
    626   1.1     ragge 		}
    627   1.1     ragge 		selwakeup(&tp->t_wsel);
    628   1.1     ragge 	}
    629   1.1     ragge 	if (tp->t_outq.c_cc == 0)
    630   1.1     ragge 		goto out;
    631   1.1     ragge 	cc = ndqb(&tp->t_outq, 0);
    632   1.1     ragge 	if (cc == 0)
    633   1.1     ragge 		goto out;
    634   1.1     ragge 
    635   1.1     ragge 	tp->t_state |= TS_BUSY;
    636   1.1     ragge 
    637   1.5     ragge 	sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
    638   1.5     ragge 
    639   1.5     ragge 	line = DHU_LINE(minor(tp->t_dev));
    640   1.1     ragge 
    641  1.15     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    642   1.5     ragge 
    643   1.5     ragge 	sc->sc_dhu[line].dhu_cc = cc;
    644   1.2     ragge 
    645   1.5     ragge 	if (cc == 1) {
    646   1.2     ragge 
    647   1.5     ragge 		sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR;
    648  1.15     ragge 
    649  1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TXCHAR,
    650  1.15     ragge 		    DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf);
    651   1.2     ragge 
    652   1.5     ragge 	} else {
    653   1.5     ragge 
    654   1.5     ragge 		sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING;
    655   1.5     ragge 
    656  1.16     ragge 		addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr +
    657   1.2     ragge 			(tp->t_outq.c_cf - tp->t_outq.c_cs);
    658   1.2     ragge 
    659  1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc);
    660  1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF);
    661  1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) |
    662  1.15     ragge 		    DHU_TBUFAD2_TX_ENABLE);
    663  1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_LNCTRL,
    664  1.15     ragge 		    DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT);
    665  1.15     ragge 		DHU_WRITE_WORD(DHU_UBA_TBUFAD2,
    666  1.15     ragge 		    DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START);
    667   1.2     ragge 	}
    668   1.1     ragge out:
    669   1.1     ragge 	(void) splx(s);
    670   1.1     ragge 	return;
    671   1.1     ragge }
    672   1.1     ragge 
    673   1.1     ragge static int
    674   1.5     ragge dhuparam(tp, t)
    675  1.18  augustss 	struct tty *tp;
    676  1.18  augustss 	struct termios *t;
    677   1.1     ragge {
    678   1.5     ragge 	struct dhu_softc *sc;
    679  1.18  augustss 	int cflag = t->c_cflag;
    680   1.1     ragge 	int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab);
    681   1.1     ragge 	int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab);
    682  1.18  augustss 	unsigned lpr, lnctrl;
    683   1.5     ragge 	int unit, line;
    684   1.1     ragge 	int s;
    685   1.1     ragge 
    686   1.5     ragge 	unit = DHU_M2U(minor(tp->t_dev));
    687   1.5     ragge 	line = DHU_LINE(minor(tp->t_dev));
    688   1.5     ragge 
    689   1.5     ragge 	sc = dhu_cd.cd_devs[unit];
    690   1.5     ragge 
    691   1.1     ragge 	/* check requested parameters */
    692   1.1     ragge         if (ospeed < 0 || ispeed < 0)
    693   1.1     ragge                 return (EINVAL);
    694   1.1     ragge 
    695   1.1     ragge         tp->t_ispeed = t->c_ispeed;
    696   1.1     ragge         tp->t_ospeed = t->c_ospeed;
    697   1.1     ragge         tp->t_cflag = cflag;
    698   1.1     ragge 
    699   1.1     ragge 	if (ospeed == 0) {
    700   1.5     ragge 		(void) dhumctl(sc, line, 0, DMSET);	/* hang up line */
    701   1.1     ragge 		return (0);
    702   1.1     ragge 	}
    703   1.1     ragge 
    704   1.1     ragge 	s = spltty();
    705  1.15     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    706   1.1     ragge 
    707   1.1     ragge 	lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ;
    708   1.1     ragge 
    709   1.5     ragge 	switch (cflag & CSIZE) {
    710   1.5     ragge 
    711   1.5     ragge 	case CS5:
    712   1.1     ragge 		lpr |= DHU_LPR_5_BIT_CHAR;
    713   1.1     ragge 		break;
    714   1.5     ragge 
    715   1.5     ragge 	case CS6:
    716   1.1     ragge 		lpr |= DHU_LPR_6_BIT_CHAR;
    717   1.1     ragge 		break;
    718   1.5     ragge 
    719   1.5     ragge 	case CS7:
    720   1.1     ragge 		lpr |= DHU_LPR_7_BIT_CHAR;
    721   1.1     ragge 		break;
    722   1.5     ragge 
    723   1.5     ragge 	default:
    724   1.1     ragge 		lpr |= DHU_LPR_8_BIT_CHAR;
    725   1.1     ragge 		break;
    726   1.1     ragge 	}
    727   1.5     ragge 
    728   1.1     ragge 	if (cflag & PARENB)
    729   1.1     ragge 		lpr |= DHU_LPR_PARENB;
    730   1.1     ragge 	if (!(cflag & PARODD))
    731   1.1     ragge 		lpr |= DHU_LPR_EPAR;
    732   1.1     ragge 	if (cflag & CSTOPB)
    733   1.1     ragge 		lpr |= DHU_LPR_2_STOP;
    734   1.1     ragge 
    735  1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_LPR, lpr);
    736   1.1     ragge 
    737  1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_TBUFAD2,
    738  1.15     ragge 	    DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE);
    739   1.2     ragge 
    740  1.15     ragge 	lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL);
    741   1.2     ragge 
    742   1.1     ragge 	/* Setting LINK.TYPE enables modem signal change interrupts. */
    743   1.1     ragge 
    744   1.2     ragge 	lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE);
    745   1.2     ragge 
    746   1.5     ragge 	/* Enable the auto XON/XOFF feature on the controller */
    747   1.5     ragge 
    748   1.2     ragge 	if (t->c_iflag & IXON)
    749   1.2     ragge 		lnctrl |= DHU_LNCTRL_OAUTO;
    750   1.2     ragge 	else
    751   1.2     ragge 		lnctrl &= ~DHU_LNCTRL_OAUTO;
    752   1.2     ragge 
    753   1.2     ragge 	if (t->c_iflag & IXOFF)
    754   1.2     ragge 		lnctrl |= DHU_LNCTRL_IAUTO;
    755   1.2     ragge 	else
    756   1.2     ragge 		lnctrl &= ~DHU_LNCTRL_IAUTO;
    757   1.2     ragge 
    758  1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl);
    759   1.2     ragge 
    760   1.1     ragge 	(void) splx(s);
    761   1.1     ragge 	return (0);
    762   1.1     ragge }
    763   1.1     ragge 
    764   1.1     ragge static int
    765   1.5     ragge dhuiflow(tp, flag)
    766   1.2     ragge 	struct tty *tp;
    767   1.2     ragge 	int flag;
    768   1.2     ragge {
    769  1.18  augustss 	struct dhu_softc *sc;
    770  1.18  augustss 	int line = DHU_LINE(minor(tp->t_dev));
    771   1.2     ragge 
    772   1.2     ragge 	if (tp->t_cflag & CRTSCTS) {
    773   1.5     ragge 		sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))];
    774   1.5     ragge 		(void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS));
    775   1.2     ragge 		return (1);
    776   1.2     ragge 	}
    777   1.2     ragge 	return (0);
    778   1.2     ragge }
    779   1.2     ragge 
    780   1.2     ragge static unsigned
    781   1.5     ragge dhumctl(sc, line, bits, how)
    782   1.5     ragge 	struct dhu_softc *sc;
    783   1.5     ragge 	int line, bits, how;
    784   1.1     ragge {
    785  1.18  augustss 	unsigned status;
    786  1.18  augustss 	unsigned lnctrl;
    787  1.18  augustss 	unsigned mbits;
    788   1.1     ragge 	int s;
    789   1.1     ragge 
    790   1.1     ragge 	s = spltty();
    791   1.1     ragge 
    792  1.15     ragge 	DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line);
    793   1.1     ragge 
    794   1.1     ragge 	mbits = 0;
    795   1.1     ragge 
    796   1.1     ragge 	/* external signals as seen from the port */
    797   1.1     ragge 
    798  1.15     ragge 	status = DHU_READ_WORD(DHU_UBA_STAT);
    799   1.1     ragge 
    800   1.2     ragge 	if (status & DHU_STAT_CTS)
    801   1.1     ragge 		mbits |= DML_CTS;
    802   1.1     ragge 
    803   1.2     ragge 	if (status & DHU_STAT_DCD)
    804   1.1     ragge 		mbits |= DML_DCD;
    805   1.1     ragge 
    806   1.2     ragge 	if (status & DHU_STAT_DSR)
    807   1.1     ragge 		mbits |= DML_DSR;
    808   1.1     ragge 
    809   1.2     ragge 	if (status & DHU_STAT_RI)
    810   1.1     ragge 		mbits |= DML_RI;
    811   1.1     ragge 
    812   1.1     ragge 	/* internal signals/state delivered to port */
    813   1.1     ragge 
    814  1.15     ragge 	lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL);
    815   1.1     ragge 
    816   1.2     ragge 	if (lnctrl & DHU_LNCTRL_RTS)
    817   1.1     ragge 		mbits |= DML_RTS;
    818   1.1     ragge 
    819   1.2     ragge 	if (lnctrl & DHU_LNCTRL_DTR)
    820   1.1     ragge 		mbits |= DML_DTR;
    821   1.1     ragge 
    822   1.2     ragge 	if (lnctrl & DHU_LNCTRL_BREAK)
    823   1.1     ragge 		mbits |= DML_BRK;
    824   1.1     ragge 
    825   1.5     ragge 	switch (how) {
    826   1.5     ragge 
    827   1.5     ragge 	case DMSET:
    828   1.1     ragge 		mbits = bits;
    829   1.1     ragge 		break;
    830   1.1     ragge 
    831   1.5     ragge 	case DMBIS:
    832   1.1     ragge 		mbits |= bits;
    833   1.1     ragge 		break;
    834   1.1     ragge 
    835   1.5     ragge 	case DMBIC:
    836   1.1     ragge 		mbits &= ~bits;
    837   1.1     ragge 		break;
    838   1.1     ragge 
    839   1.5     ragge 	case DMGET:
    840   1.1     ragge 		(void) splx(s);
    841   1.1     ragge 		return (mbits);
    842   1.1     ragge 	}
    843   1.1     ragge 
    844   1.1     ragge 	if (mbits & DML_RTS)
    845   1.2     ragge 		lnctrl |= DHU_LNCTRL_RTS;
    846   1.1     ragge 	else
    847   1.2     ragge 		lnctrl &= ~DHU_LNCTRL_RTS;
    848   1.1     ragge 
    849   1.1     ragge 	if (mbits & DML_DTR)
    850   1.2     ragge 		lnctrl |= DHU_LNCTRL_DTR;
    851   1.1     ragge 	else
    852   1.2     ragge 		lnctrl &= ~DHU_LNCTRL_DTR;
    853   1.1     ragge 
    854   1.1     ragge 	if (mbits & DML_BRK)
    855   1.2     ragge 		lnctrl |= DHU_LNCTRL_BREAK;
    856   1.1     ragge 	else
    857   1.2     ragge 		lnctrl &= ~DHU_LNCTRL_BREAK;
    858   1.2     ragge 
    859  1.15     ragge 	DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl);
    860   1.1     ragge 
    861   1.1     ragge 	(void) splx(s);
    862   1.1     ragge 	return (mbits);
    863   1.1     ragge }
    864