dhu.c revision 1.14
1 /* $NetBSD: dhu.c,v 1.14 1999/05/28 18:56:41 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/trap.h> 54 #include <machine/scb.h> 55 56 #include <vax/uba/ubavar.h> 57 #include <vax/uba/dhureg.h> 58 59 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 60 61 #define NDHULINE 16 62 63 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 64 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 65 66 struct dhu_softc { 67 struct device sc_dev; /* Device struct used by config */ 68 dhuregs * sc_addr; /* controller reg address */ 69 int sc_type; /* controller type, DHU or DHV */ 70 struct { 71 struct tty *dhu_tty; /* what we work on */ 72 int dhu_state; /* to manage TX output status */ 73 int dhu_txaddr; /* UBA map address to TX buf */ 74 short dhu_cc; /* character count on TX */ 75 short dhu_modem; /* modem bits state */ 76 } sc_dhu[NDHULINE]; 77 }; 78 79 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 80 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 81 82 #define STATE_IDLE 000 /* no current output in progress */ 83 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 84 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 85 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 86 87 /* Flags used to monitor modem bits, make them understood outside driver */ 88 89 #define DML_DTR TIOCM_DTR 90 #define DML_RTS TIOCM_RTS 91 #define DML_CTS TIOCM_CTS 92 #define DML_DCD TIOCM_CD 93 #define DML_RI TIOCM_RI 94 #define DML_DSR TIOCM_DSR 95 #define DML_BRK 0100000 /* no equivalent, we will mask */ 96 97 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 98 /* a baud rate from the same group. So limiting to B is likely */ 99 /* best, although clone boards like the ABLE QHV allow all settings. */ 100 101 static struct speedtab dhuspeedtab[] = { 102 { 0, 0 }, /* Groups */ 103 { 50, DHU_LPR_B50 }, /* A */ 104 { 75, DHU_LPR_B75 }, /* B */ 105 { 110, DHU_LPR_B110 }, /* A and B */ 106 { 134, DHU_LPR_B134 }, /* A and B */ 107 { 150, DHU_LPR_B150 }, /* B */ 108 { 300, DHU_LPR_B300 }, /* A and B */ 109 { 600, DHU_LPR_B600 }, /* A and B */ 110 { 1200, DHU_LPR_B1200 }, /* A and B */ 111 { 1800, DHU_LPR_B1800 }, /* B */ 112 { 2000, DHU_LPR_B2000 }, /* B */ 113 { 2400, DHU_LPR_B2400 }, /* A and B */ 114 { 4800, DHU_LPR_B4800 }, /* A and B */ 115 { 7200, DHU_LPR_B7200 }, /* A */ 116 { 9600, DHU_LPR_B9600 }, /* A and B */ 117 { 19200, DHU_LPR_B19200 }, /* B */ 118 { 38400, DHU_LPR_B38400 }, /* A */ 119 { -1, -1 } 120 }; 121 122 static int dhu_match __P((struct device *, struct cfdata *, void *)); 123 static void dhu_attach __P((struct device *, struct device *, void *)); 124 static void dhurint __P((int)); 125 static void dhuxint __P((int)); 126 static void dhustart __P((struct tty *)); 127 static int dhuparam __P((struct tty *, struct termios *)); 128 static int dhuiflow __P((struct tty *, int)); 129 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 130 int dhuopen __P((dev_t, int, int, struct proc *)); 131 int dhuclose __P((dev_t, int, int, struct proc *)); 132 int dhuread __P((dev_t, struct uio *, int)); 133 int dhuwrite __P((dev_t, struct uio *, int)); 134 int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); 135 void dhustop __P((struct tty *, int)); 136 struct tty * dhutty __P((dev_t)); 137 138 struct cfattach dhu_ca = { 139 sizeof(struct dhu_softc), dhu_match, dhu_attach 140 }; 141 142 extern struct cfdriver dhu_cd; 143 144 /* Autoconfig handles: setup the controller to interrupt, */ 145 /* then complete the housecleaning for full operation */ 146 147 static int 148 dhu_match(parent, cf, aux) 149 struct device *parent; 150 struct cfdata *cf; 151 void *aux; 152 { 153 struct uba_attach_args *ua = aux; 154 register dhuregs *dhuaddr; 155 register int n; 156 157 dhuaddr = (dhuregs *) ua->ua_addr; 158 159 /* Reset controller to initialize, enable TX/RX interrupts */ 160 /* to catch floating vector info elsewhere when completed */ 161 162 dhuaddr->dhu_csr = (DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 163 164 /* Now wait up to 3 seconds for self-test to complete. */ 165 166 for (n = 0; n < 300; n++) { 167 DELAY(10000); 168 if ((dhuaddr->dhu_csr & DHU_CSR_MASTER_RESET) == 0) 169 break; 170 } 171 172 /* If the RESET did not clear after 3 seconds, */ 173 /* the controller must be broken. */ 174 175 if (n >= 300) 176 return 0; 177 178 /* Check whether diagnostic run has signalled a failure. */ 179 180 if ((dhuaddr->dhu_csr & DHU_CSR_DIAG_FAIL) != 0) 181 return 0; 182 183 /* Register the RX interrupt handler */ 184 185 ua->ua_ivec = dhurint; 186 187 return 1; 188 } 189 190 static void 191 dhu_attach(parent, self, aux) 192 struct device *parent, *self; 193 void *aux; 194 { 195 register struct dhu_softc *sc = (void *)self; 196 register struct uba_attach_args *ua = aux; 197 register dhuregs *dhuaddr; 198 register unsigned c; 199 register int n; 200 201 dhuaddr = (dhuregs *) ua->ua_addr; 202 203 /* Process the 8 bytes of diagnostic info put into */ 204 /* the FIFO following the master reset operation. */ 205 206 printf("\n%s:", self->dv_xname); 207 for (n = 0; n < 8; n++) { 208 c = dhuaddr->dhu_rbuf; 209 210 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 211 if ((c&0200) == 0000) 212 printf(" rom(%d) version %d", 213 ((c>>1)&01), ((c>>2)&037)); 214 else if (((c>>2)&07) != 0) 215 printf(" diag-error(proc%d)=%x", 216 ((c>>1)&01), ((c>>2)&07)); 217 } 218 } 219 printf("\n"); 220 221 c = dhuaddr->dhu_stat; /* get flag to distinguish DHU from DHV */ 222 223 sc->sc_addr = dhuaddr; 224 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 225 226 /* Now stuff TX interrupt handler in place */ 227 scb_vecalloc(ua->ua_cvec + 4, dhuxint, self->dv_unit, SCB_ISTACK); 228 } 229 230 /* Receiver Interrupt */ 231 232 static void 233 dhurint(unit) 234 int unit; 235 { 236 struct dhu_softc *sc = dhu_cd.cd_devs[unit]; 237 register dhuregs *dhuaddr; 238 register struct tty *tp; 239 register int cc, line; 240 register unsigned c, delta; 241 int overrun = 0; 242 243 dhuaddr = sc->sc_addr; 244 245 while ((c = dhuaddr->dhu_rbuf) & DHU_RBUF_DATA_VALID) { 246 247 /* Ignore diagnostic FIFO entries. */ 248 249 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 250 continue; 251 252 cc = c & 0xFF; 253 line = DHU_LINE(c>>8); 254 tp = sc->sc_dhu[line].dhu_tty; 255 256 /* LINK.TYPE is set so we get modem control FIFO entries */ 257 258 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 259 c = (c << 8); 260 /* Do MDMBUF flow control, wakeup sleeping opens */ 261 if (c & DHU_STAT_DCD) { 262 if (!(tp->t_state & TS_CARR_ON)) 263 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 264 } 265 else if ((tp->t_state & TS_CARR_ON) && 266 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) 267 (void) dhumctl(sc, line, 0, DMSET); 268 269 /* Do CRTSCTS flow control */ 270 delta = c ^ sc->sc_dhu[line].dhu_modem; 271 sc->sc_dhu[line].dhu_modem = c; 272 if ((delta & DHU_STAT_CTS) && 273 (tp->t_state & TS_ISOPEN) && 274 (tp->t_cflag & CRTSCTS)) { 275 if (c & DHU_STAT_CTS) { 276 tp->t_state &= ~TS_TTSTOP; 277 ttstart(tp); 278 } else { 279 tp->t_state |= TS_TTSTOP; 280 dhustop(tp, 0); 281 } 282 } 283 continue; 284 } 285 286 if (!(tp->t_state & TS_ISOPEN)) { 287 wakeup((caddr_t)&tp->t_rawq); 288 continue; 289 } 290 291 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 292 log(LOG_WARNING, "%s: silo overflow, line %d\n", 293 sc->sc_dev.dv_xname, line); 294 overrun = 1; 295 } 296 /* A BREAK key will appear as a NULL with a framing error */ 297 if (c & DHU_RBUF_FRAMING_ERR) 298 cc |= TTY_FE; 299 if (c & DHU_RBUF_PARITY_ERR) 300 cc |= TTY_PE; 301 302 (*linesw[tp->t_line].l_rint)(cc, tp); 303 } 304 return; 305 } 306 307 /* Transmitter Interrupt */ 308 309 static void 310 dhuxint(unit) 311 int unit; 312 { 313 register struct dhu_softc *sc = dhu_cd.cd_devs[unit]; 314 register dhuregs *dhuaddr; 315 register struct tty *tp; 316 register int line; 317 318 dhuaddr = sc->sc_addr; 319 320 line = DHU_LINE(dhuaddr->dhu_csr_hi); 321 322 tp = sc->sc_dhu[line].dhu_tty; 323 324 tp->t_state &= ~TS_BUSY; 325 if (tp->t_state & TS_FLUSH) 326 tp->t_state &= ~TS_FLUSH; 327 else { 328 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 329 sc->sc_dhu[line].dhu_cc -= dhuaddr->dhu_tbufcnt; 330 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 331 sc->sc_dhu[line].dhu_cc = 0; 332 } 333 334 sc->sc_dhu[line].dhu_state = STATE_IDLE; 335 336 if (tp->t_line) 337 (*linesw[tp->t_line].l_start)(tp); 338 else 339 dhustart(tp); 340 341 return; 342 } 343 344 int 345 dhuopen(dev, flag, mode, p) 346 dev_t dev; 347 int flag, mode; 348 struct proc *p; 349 { 350 register dhuregs *dhuaddr; 351 register struct tty *tp; 352 register int unit, line; 353 struct dhu_softc *sc; 354 int s, error = 0; 355 356 unit = DHU_M2U(minor(dev)); 357 line = DHU_LINE(minor(dev)); 358 359 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 360 return (ENXIO); 361 362 sc = dhu_cd.cd_devs[unit]; 363 364 if (line >= sc->sc_type) 365 return ENXIO; 366 367 tp = sc->sc_dhu[line].dhu_tty; 368 if (tp == NULL) { 369 370 tp = sc->sc_dhu[line].dhu_tty = ttymalloc(); 371 if (tp == NULL) 372 return ENXIO; 373 374 sc->sc_dhu[line].dhu_state = STATE_IDLE; 375 376 sc->sc_dhu[line].dhu_txaddr = 377 uballoc((struct uba_softc *)sc->sc_dev.dv_parent, 378 tp->t_outq.c_cs, tp->t_outq.c_cn, 0); 379 380 dhuaddr = sc->sc_addr; 381 382 s = spltty(); 383 dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line); 384 sc->sc_dhu[line].dhu_modem = dhuaddr->dhu_stat; 385 (void) splx(s); 386 } 387 388 tp->t_oproc = dhustart; 389 tp->t_param = dhuparam; 390 tp->t_hwiflow = dhuiflow; 391 tp->t_dev = dev; 392 if ((tp->t_state & TS_ISOPEN) == 0) { 393 ttychars(tp); 394 if (tp->t_ispeed == 0) { 395 tp->t_iflag = TTYDEF_IFLAG; 396 tp->t_oflag = TTYDEF_OFLAG; 397 tp->t_cflag = TTYDEF_CFLAG; 398 tp->t_lflag = TTYDEF_LFLAG; 399 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 400 } 401 (void) dhuparam(tp, &tp->t_termios); 402 ttsetwater(tp); 403 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 404 return (EBUSY); 405 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 406 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 407 tp->t_state |= TS_CARR_ON; 408 s = spltty(); 409 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 410 !(tp->t_state & TS_CARR_ON)) { 411 tp->t_wopen++; 412 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 413 TTIPRI | PCATCH, ttopen, 0); 414 tp->t_wopen--; 415 if (error) 416 break; 417 } 418 (void) splx(s); 419 if (error) 420 return (error); 421 return ((*linesw[tp->t_line].l_open)(dev, tp)); 422 } 423 424 /*ARGSUSED*/ 425 int 426 dhuclose(dev, flag, mode, p) 427 dev_t dev; 428 int flag, mode; 429 struct proc *p; 430 { 431 register struct tty *tp; 432 register int unit, line; 433 struct dhu_softc *sc; 434 435 unit = DHU_M2U(minor(dev)); 436 line = DHU_LINE(minor(dev)); 437 438 sc = dhu_cd.cd_devs[unit]; 439 440 tp = sc->sc_dhu[line].dhu_tty; 441 442 (*linesw[tp->t_line].l_close)(tp, flag); 443 444 /* Make sure a BREAK state is not left enabled. */ 445 446 (void) dhumctl(sc, line, DML_BRK, DMBIC); 447 448 /* Do a hangup if so required. */ 449 450 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 451 !(tp->t_state & TS_ISOPEN)) 452 (void) dhumctl(sc, line, 0, DMSET); 453 454 return (ttyclose(tp)); 455 } 456 457 int 458 dhuread(dev, uio, flag) 459 dev_t dev; 460 struct uio *uio; 461 { 462 register struct dhu_softc *sc; 463 register struct tty *tp; 464 465 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 466 467 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 468 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 469 } 470 471 int 472 dhuwrite(dev, uio, flag) 473 dev_t dev; 474 struct uio *uio; 475 { 476 register struct dhu_softc *sc; 477 register struct tty *tp; 478 479 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 480 481 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 482 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 483 } 484 485 /*ARGSUSED*/ 486 int 487 dhuioctl(dev, cmd, data, flag, p) 488 dev_t dev; 489 u_long cmd; 490 caddr_t data; 491 int flag; 492 struct proc *p; 493 { 494 register struct dhu_softc *sc; 495 register struct tty *tp; 496 register int unit, line; 497 int error; 498 499 unit = DHU_M2U(minor(dev)); 500 line = DHU_LINE(minor(dev)); 501 sc = dhu_cd.cd_devs[unit]; 502 tp = sc->sc_dhu[line].dhu_tty; 503 504 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 505 if (error >= 0) 506 return (error); 507 error = ttioctl(tp, cmd, data, flag, p); 508 if (error >= 0) 509 return (error); 510 511 switch (cmd) { 512 513 case TIOCSBRK: 514 (void) dhumctl(sc, line, DML_BRK, DMBIS); 515 break; 516 517 case TIOCCBRK: 518 (void) dhumctl(sc, line, DML_BRK, DMBIC); 519 break; 520 521 case TIOCSDTR: 522 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 523 break; 524 525 case TIOCCDTR: 526 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 527 break; 528 529 case TIOCMSET: 530 (void) dhumctl(sc, line, *(int *)data, DMSET); 531 break; 532 533 case TIOCMBIS: 534 (void) dhumctl(sc, line, *(int *)data, DMBIS); 535 break; 536 537 case TIOCMBIC: 538 (void) dhumctl(sc, line, *(int *)data, DMBIC); 539 break; 540 541 case TIOCMGET: 542 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 543 break; 544 545 default: 546 return (ENOTTY); 547 } 548 return (0); 549 } 550 551 struct tty * 552 dhutty(dev) 553 dev_t dev; 554 { 555 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 556 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 557 return (tp); 558 } 559 560 /*ARGSUSED*/ 561 void 562 dhustop(tp, flag) 563 register struct tty *tp; 564 { 565 register struct dhu_softc *sc; 566 register dhuregs *dhuaddr; 567 register int line; 568 int s; 569 570 s = spltty(); 571 572 if (tp->t_state & TS_BUSY) { 573 574 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 575 line = DHU_LINE(minor(tp->t_dev)); 576 577 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 578 579 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 580 581 dhuaddr = sc->sc_addr; 582 dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line); 583 dhuaddr->dhu_lnctrl |= DHU_LNCTRL_DMA_ABORT; 584 } 585 586 if (!(tp->t_state & TS_TTSTOP)) 587 tp->t_state |= TS_FLUSH; 588 } 589 (void) splx(s); 590 } 591 592 static void 593 dhustart(tp) 594 register struct tty *tp; 595 { 596 register struct dhu_softc *sc; 597 register dhuregs *dhuaddr; 598 register int line, cc; 599 register int addr; 600 int s; 601 602 s = spltty(); 603 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 604 goto out; 605 if (tp->t_outq.c_cc <= tp->t_lowat) { 606 if (tp->t_state & TS_ASLEEP) { 607 tp->t_state &= ~TS_ASLEEP; 608 wakeup((caddr_t)&tp->t_outq); 609 } 610 selwakeup(&tp->t_wsel); 611 } 612 if (tp->t_outq.c_cc == 0) 613 goto out; 614 cc = ndqb(&tp->t_outq, 0); 615 if (cc == 0) 616 goto out; 617 618 tp->t_state |= TS_BUSY; 619 620 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 621 622 line = DHU_LINE(minor(tp->t_dev)); 623 624 dhuaddr = sc->sc_addr; 625 dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line); 626 627 sc->sc_dhu[line].dhu_cc = cc; 628 629 if (cc == 1) { 630 631 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 632 dhuaddr->dhu_txchar = DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf; 633 634 } else { 635 636 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 637 638 addr = UBAI_ADDR(sc->sc_dhu[line].dhu_txaddr) + 639 (tp->t_outq.c_cf - tp->t_outq.c_cs); 640 641 dhuaddr->dhu_tbufcnt = cc; 642 dhuaddr->dhu_tbufad1 = (addr & 0xFFFF); 643 dhuaddr->dhu_tbufad2 = ((addr>>16) & 0x3F) | 644 DHU_TBUFAD2_TX_ENABLE; 645 646 dhuaddr->dhu_lnctrl &= ~DHU_LNCTRL_DMA_ABORT; 647 dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_DMA_START; 648 } 649 out: 650 (void) splx(s); 651 return; 652 } 653 654 static int 655 dhuparam(tp, t) 656 register struct tty *tp; 657 register struct termios *t; 658 { 659 struct dhu_softc *sc; 660 register dhuregs *dhuaddr; 661 register int cflag = t->c_cflag; 662 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 663 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 664 register unsigned lpr, lnctrl; 665 int unit, line; 666 int s; 667 668 unit = DHU_M2U(minor(tp->t_dev)); 669 line = DHU_LINE(minor(tp->t_dev)); 670 671 sc = dhu_cd.cd_devs[unit]; 672 673 /* check requested parameters */ 674 if (ospeed < 0 || ispeed < 0) 675 return (EINVAL); 676 677 tp->t_ispeed = t->c_ispeed; 678 tp->t_ospeed = t->c_ospeed; 679 tp->t_cflag = cflag; 680 681 if (ospeed == 0) { 682 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 683 return (0); 684 } 685 686 s = spltty(); 687 dhuaddr = sc->sc_addr; 688 dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line); 689 690 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 691 692 switch (cflag & CSIZE) { 693 694 case CS5: 695 lpr |= DHU_LPR_5_BIT_CHAR; 696 break; 697 698 case CS6: 699 lpr |= DHU_LPR_6_BIT_CHAR; 700 break; 701 702 case CS7: 703 lpr |= DHU_LPR_7_BIT_CHAR; 704 break; 705 706 default: 707 lpr |= DHU_LPR_8_BIT_CHAR; 708 break; 709 } 710 711 if (cflag & PARENB) 712 lpr |= DHU_LPR_PARENB; 713 if (!(cflag & PARODD)) 714 lpr |= DHU_LPR_EPAR; 715 if (cflag & CSTOPB) 716 lpr |= DHU_LPR_2_STOP; 717 718 dhuaddr->dhu_lpr = lpr; 719 720 dhuaddr->dhu_tbufad2 |= DHU_TBUFAD2_TX_ENABLE; 721 722 lnctrl = dhuaddr->dhu_lnctrl; 723 724 /* Setting LINK.TYPE enables modem signal change interrupts. */ 725 726 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 727 728 /* Enable the auto XON/XOFF feature on the controller */ 729 730 if (t->c_iflag & IXON) 731 lnctrl |= DHU_LNCTRL_OAUTO; 732 else 733 lnctrl &= ~DHU_LNCTRL_OAUTO; 734 735 if (t->c_iflag & IXOFF) 736 lnctrl |= DHU_LNCTRL_IAUTO; 737 else 738 lnctrl &= ~DHU_LNCTRL_IAUTO; 739 740 dhuaddr->dhu_lnctrl = lnctrl; 741 742 (void) splx(s); 743 return (0); 744 } 745 746 static int 747 dhuiflow(tp, flag) 748 struct tty *tp; 749 int flag; 750 { 751 register struct dhu_softc *sc; 752 register int line = DHU_LINE(minor(tp->t_dev)); 753 754 if (tp->t_cflag & CRTSCTS) { 755 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 756 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 757 return (1); 758 } 759 return (0); 760 } 761 762 static unsigned 763 dhumctl(sc, line, bits, how) 764 struct dhu_softc *sc; 765 int line, bits, how; 766 { 767 register dhuregs *dhuaddr; 768 register unsigned status; 769 register unsigned lnctrl; 770 register unsigned mbits; 771 int s; 772 773 s = spltty(); 774 775 dhuaddr = sc->sc_addr; 776 dhuaddr->dhu_csr_lo = (DHU_CSR_RXIE | line); 777 778 mbits = 0; 779 780 /* external signals as seen from the port */ 781 782 status = dhuaddr->dhu_stat; 783 784 if (status & DHU_STAT_CTS) 785 mbits |= DML_CTS; 786 787 if (status & DHU_STAT_DCD) 788 mbits |= DML_DCD; 789 790 if (status & DHU_STAT_DSR) 791 mbits |= DML_DSR; 792 793 if (status & DHU_STAT_RI) 794 mbits |= DML_RI; 795 796 /* internal signals/state delivered to port */ 797 798 lnctrl = dhuaddr->dhu_lnctrl; 799 800 if (lnctrl & DHU_LNCTRL_RTS) 801 mbits |= DML_RTS; 802 803 if (lnctrl & DHU_LNCTRL_DTR) 804 mbits |= DML_DTR; 805 806 if (lnctrl & DHU_LNCTRL_BREAK) 807 mbits |= DML_BRK; 808 809 switch (how) { 810 811 case DMSET: 812 mbits = bits; 813 break; 814 815 case DMBIS: 816 mbits |= bits; 817 break; 818 819 case DMBIC: 820 mbits &= ~bits; 821 break; 822 823 case DMGET: 824 (void) splx(s); 825 return (mbits); 826 } 827 828 if (mbits & DML_RTS) 829 lnctrl |= DHU_LNCTRL_RTS; 830 else 831 lnctrl &= ~DHU_LNCTRL_RTS; 832 833 if (mbits & DML_DTR) 834 lnctrl |= DHU_LNCTRL_DTR; 835 else 836 lnctrl &= ~DHU_LNCTRL_DTR; 837 838 if (mbits & DML_BRK) 839 lnctrl |= DHU_LNCTRL_BREAK; 840 else 841 lnctrl &= ~DHU_LNCTRL_BREAK; 842 843 dhuaddr->dhu_lnctrl = lnctrl; 844 845 (void) splx(s); 846 return (mbits); 847 } 848
Indexes created Sat Oct 18 23:09:54 GMT 2025