dhu.c revision 1.15
1 /* $NetBSD: dhu.c,v 1.15 1999/05/28 20:17:29 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 #include <machine/scb.h> 55 56 #include <dev/qbus/ubavar.h> 57 58 #include <dev/qbus/dhureg.h> 59 60 #include "ioconf.h" 61 62 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 63 64 #define NDHULINE 16 65 66 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 67 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 68 69 struct dhu_softc { 70 struct device sc_dev; /* Device struct used by config */ 71 int sc_type; /* controller type, DHU or DHV */ 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 struct { 75 struct tty *dhu_tty; /* what we work on */ 76 int dhu_state; /* to manage TX output status */ 77 int dhu_txaddr; /* UBA map address to TX buf */ 78 short dhu_cc; /* character count on TX */ 79 short dhu_modem; /* modem bits state */ 80 } sc_dhu[NDHULINE]; 81 }; 82 83 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 84 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 85 86 #define STATE_IDLE 000 /* no current output in progress */ 87 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 88 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 89 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 90 91 /* Flags used to monitor modem bits, make them understood outside driver */ 92 93 #define DML_DTR TIOCM_DTR 94 #define DML_RTS TIOCM_RTS 95 #define DML_CTS TIOCM_CTS 96 #define DML_DCD TIOCM_CD 97 #define DML_RI TIOCM_RI 98 #define DML_DSR TIOCM_DSR 99 #define DML_BRK 0100000 /* no equivalent, we will mask */ 100 101 #define DHU_READ_WORD(reg) \ 102 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 103 #define DHU_WRITE_WORD(reg, val) \ 104 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 105 #define DHU_READ_BYTE(reg) \ 106 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 107 #define DHU_WRITE_BYTE(reg, val) \ 108 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 109 110 111 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 112 /* a baud rate from the same group. So limiting to B is likely */ 113 /* best, although clone boards like the ABLE QHV allow all settings. */ 114 115 static struct speedtab dhuspeedtab[] = { 116 { 0, 0 }, /* Groups */ 117 { 50, DHU_LPR_B50 }, /* A */ 118 { 75, DHU_LPR_B75 }, /* B */ 119 { 110, DHU_LPR_B110 }, /* A and B */ 120 { 134, DHU_LPR_B134 }, /* A and B */ 121 { 150, DHU_LPR_B150 }, /* B */ 122 { 300, DHU_LPR_B300 }, /* A and B */ 123 { 600, DHU_LPR_B600 }, /* A and B */ 124 { 1200, DHU_LPR_B1200 }, /* A and B */ 125 { 1800, DHU_LPR_B1800 }, /* B */ 126 { 2000, DHU_LPR_B2000 }, /* B */ 127 { 2400, DHU_LPR_B2400 }, /* A and B */ 128 { 4800, DHU_LPR_B4800 }, /* A and B */ 129 { 7200, DHU_LPR_B7200 }, /* A */ 130 { 9600, DHU_LPR_B9600 }, /* A and B */ 131 { 19200, DHU_LPR_B19200 }, /* B */ 132 { 38400, DHU_LPR_B38400 }, /* A */ 133 { -1, -1 } 134 }; 135 136 static int dhu_match __P((struct device *, struct cfdata *, void *)); 137 static void dhu_attach __P((struct device *, struct device *, void *)); 138 static void dhurint __P((int)); 139 static void dhuxint __P((int)); 140 static void dhustart __P((struct tty *)); 141 static int dhuparam __P((struct tty *, struct termios *)); 142 static int dhuiflow __P((struct tty *, int)); 143 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 144 int dhuopen __P((dev_t, int, int, struct proc *)); 145 int dhuclose __P((dev_t, int, int, struct proc *)); 146 int dhuread __P((dev_t, struct uio *, int)); 147 int dhuwrite __P((dev_t, struct uio *, int)); 148 int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); 149 void dhustop __P((struct tty *, int)); 150 struct tty * dhutty __P((dev_t)); 151 152 struct cfattach dhu_ca = { 153 sizeof(struct dhu_softc), dhu_match, dhu_attach 154 }; 155 156 /* Autoconfig handles: setup the controller to interrupt, */ 157 /* then complete the housecleaning for full operation */ 158 159 static int 160 dhu_match(parent, cf, aux) 161 struct device *parent; 162 struct cfdata *cf; 163 void *aux; 164 { 165 struct uba_attach_args *ua = aux; 166 register int n; 167 168 /* Reset controller to initialize, enable TX/RX interrupts */ 169 /* to catch floating vector info elsewhere when completed */ 170 171 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 172 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 173 174 /* Now wait up to 3 seconds for self-test to complete. */ 175 176 for (n = 0; n < 300; n++) { 177 DELAY(10000); 178 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 179 DHU_CSR_MASTER_RESET) == 0) 180 break; 181 } 182 183 /* If the RESET did not clear after 3 seconds, */ 184 /* the controller must be broken. */ 185 186 if (n >= 300) 187 return 0; 188 189 /* Check whether diagnostic run has signalled a failure. */ 190 191 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 192 DHU_CSR_DIAG_FAIL) != 0) 193 return 0; 194 195 /* Register the RX interrupt handler */ 196 197 ua->ua_ivec = dhurint; 198 199 return 1; 200 } 201 202 static void 203 dhu_attach(parent, self, aux) 204 struct device *parent, *self; 205 void *aux; 206 { 207 register struct dhu_softc *sc = (void *)self; 208 register struct uba_attach_args *ua = aux; 209 register unsigned c; 210 register int n; 211 212 sc->sc_iot = ua->ua_iot; 213 sc->sc_ioh = ua->ua_ioh; 214 /* Process the 8 bytes of diagnostic info put into */ 215 /* the FIFO following the master reset operation. */ 216 217 printf("\n%s:", self->dv_xname); 218 for (n = 0; n < 8; n++) { 219 c = DHU_READ_WORD(DHU_UBA_RBUF); 220 221 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 222 if ((c&0200) == 0000) 223 printf(" rom(%d) version %d", 224 ((c>>1)&01), ((c>>2)&037)); 225 else if (((c>>2)&07) != 0) 226 printf(" diag-error(proc%d)=%x", 227 ((c>>1)&01), ((c>>2)&07)); 228 } 229 } 230 231 c = DHU_READ_WORD(DHU_UBA_STAT); 232 233 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 234 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 235 236 /* Now stuff TX interrupt handler in place */ 237 scb_vecalloc(ua->ua_cvec + 4, dhuxint, self->dv_unit, SCB_ISTACK); 238 } 239 240 /* Receiver Interrupt */ 241 242 static void 243 dhurint(unit) 244 int unit; 245 { 246 struct dhu_softc *sc = dhu_cd.cd_devs[unit]; 247 register struct tty *tp; 248 register int cc, line; 249 register unsigned c, delta; 250 int overrun = 0; 251 252 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 253 254 /* Ignore diagnostic FIFO entries. */ 255 256 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 257 continue; 258 259 cc = c & 0xFF; 260 line = DHU_LINE(c>>8); 261 tp = sc->sc_dhu[line].dhu_tty; 262 263 /* LINK.TYPE is set so we get modem control FIFO entries */ 264 265 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 266 c = (c << 8); 267 /* Do MDMBUF flow control, wakeup sleeping opens */ 268 if (c & DHU_STAT_DCD) { 269 if (!(tp->t_state & TS_CARR_ON)) 270 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 271 } 272 else if ((tp->t_state & TS_CARR_ON) && 273 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) 274 (void) dhumctl(sc, line, 0, DMSET); 275 276 /* Do CRTSCTS flow control */ 277 delta = c ^ sc->sc_dhu[line].dhu_modem; 278 sc->sc_dhu[line].dhu_modem = c; 279 if ((delta & DHU_STAT_CTS) && 280 (tp->t_state & TS_ISOPEN) && 281 (tp->t_cflag & CRTSCTS)) { 282 if (c & DHU_STAT_CTS) { 283 tp->t_state &= ~TS_TTSTOP; 284 ttstart(tp); 285 } else { 286 tp->t_state |= TS_TTSTOP; 287 dhustop(tp, 0); 288 } 289 } 290 continue; 291 } 292 293 if (!(tp->t_state & TS_ISOPEN)) { 294 wakeup((caddr_t)&tp->t_rawq); 295 continue; 296 } 297 298 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 299 log(LOG_WARNING, "%s: silo overflow, line %d\n", 300 sc->sc_dev.dv_xname, line); 301 overrun = 1; 302 } 303 /* A BREAK key will appear as a NULL with a framing error */ 304 if (c & DHU_RBUF_FRAMING_ERR) 305 cc |= TTY_FE; 306 if (c & DHU_RBUF_PARITY_ERR) 307 cc |= TTY_PE; 308 309 (*linesw[tp->t_line].l_rint)(cc, tp); 310 } 311 } 312 313 /* Transmitter Interrupt */ 314 315 static void 316 dhuxint(unit) 317 int unit; 318 { 319 register struct dhu_softc *sc = dhu_cd.cd_devs[unit]; 320 register struct tty *tp; 321 register int line; 322 323 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 324 325 tp = sc->sc_dhu[line].dhu_tty; 326 327 tp->t_state &= ~TS_BUSY; 328 if (tp->t_state & TS_FLUSH) 329 tp->t_state &= ~TS_FLUSH; 330 else { 331 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 332 sc->sc_dhu[line].dhu_cc -= 333 DHU_READ_WORD(DHU_UBA_TBUFCNT); 334 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 335 sc->sc_dhu[line].dhu_cc = 0; 336 } 337 338 sc->sc_dhu[line].dhu_state = STATE_IDLE; 339 340 if (tp->t_line) 341 (*linesw[tp->t_line].l_start)(tp); 342 else 343 dhustart(tp); 344 } 345 346 int 347 dhuopen(dev, flag, mode, p) 348 dev_t dev; 349 int flag, mode; 350 struct proc *p; 351 { 352 register struct tty *tp; 353 register int unit, line; 354 struct dhu_softc *sc; 355 int s, error = 0; 356 357 unit = DHU_M2U(minor(dev)); 358 line = DHU_LINE(minor(dev)); 359 360 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 361 return (ENXIO); 362 363 sc = dhu_cd.cd_devs[unit]; 364 365 if (line >= sc->sc_type) 366 return ENXIO; 367 368 tp = sc->sc_dhu[line].dhu_tty; 369 if (tp == NULL) { 370 371 tp = sc->sc_dhu[line].dhu_tty = ttymalloc(); 372 if (tp == NULL) 373 return ENXIO; 374 375 sc->sc_dhu[line].dhu_state = STATE_IDLE; 376 377 sc->sc_dhu[line].dhu_txaddr = 378 uballoc((struct uba_softc *)sc->sc_dev.dv_parent, 379 tp->t_outq.c_cs, tp->t_outq.c_cn, 0); 380 381 s = spltty(); 382 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 383 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 384 (void) splx(s); 385 } 386 387 tp->t_oproc = dhustart; 388 tp->t_param = dhuparam; 389 tp->t_hwiflow = dhuiflow; 390 tp->t_dev = dev; 391 if ((tp->t_state & TS_ISOPEN) == 0) { 392 ttychars(tp); 393 if (tp->t_ispeed == 0) { 394 tp->t_iflag = TTYDEF_IFLAG; 395 tp->t_oflag = TTYDEF_OFLAG; 396 tp->t_cflag = TTYDEF_CFLAG; 397 tp->t_lflag = TTYDEF_LFLAG; 398 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 399 } 400 (void) dhuparam(tp, &tp->t_termios); 401 ttsetwater(tp); 402 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 403 return (EBUSY); 404 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 405 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 406 tp->t_state |= TS_CARR_ON; 407 s = spltty(); 408 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 409 !(tp->t_state & TS_CARR_ON)) { 410 tp->t_wopen++; 411 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 412 TTIPRI | PCATCH, ttopen, 0); 413 tp->t_wopen--; 414 if (error) 415 break; 416 } 417 (void) splx(s); 418 if (error) 419 return (error); 420 return ((*linesw[tp->t_line].l_open)(dev, tp)); 421 } 422 423 /*ARGSUSED*/ 424 int 425 dhuclose(dev, flag, mode, p) 426 dev_t dev; 427 int flag, mode; 428 struct proc *p; 429 { 430 register struct tty *tp; 431 register int unit, line; 432 struct dhu_softc *sc; 433 434 unit = DHU_M2U(minor(dev)); 435 line = DHU_LINE(minor(dev)); 436 437 sc = dhu_cd.cd_devs[unit]; 438 439 tp = sc->sc_dhu[line].dhu_tty; 440 441 (*linesw[tp->t_line].l_close)(tp, flag); 442 443 /* Make sure a BREAK state is not left enabled. */ 444 445 (void) dhumctl(sc, line, DML_BRK, DMBIC); 446 447 /* Do a hangup if so required. */ 448 449 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 450 !(tp->t_state & TS_ISOPEN)) 451 (void) dhumctl(sc, line, 0, DMSET); 452 453 return (ttyclose(tp)); 454 } 455 456 int 457 dhuread(dev, uio, flag) 458 dev_t dev; 459 struct uio *uio; 460 { 461 register struct dhu_softc *sc; 462 register struct tty *tp; 463 464 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 465 466 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 467 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 468 } 469 470 int 471 dhuwrite(dev, uio, flag) 472 dev_t dev; 473 struct uio *uio; 474 { 475 register struct dhu_softc *sc; 476 register struct tty *tp; 477 478 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 479 480 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 481 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 482 } 483 484 /*ARGSUSED*/ 485 int 486 dhuioctl(dev, cmd, data, flag, p) 487 dev_t dev; 488 u_long cmd; 489 caddr_t data; 490 int flag; 491 struct proc *p; 492 { 493 register struct dhu_softc *sc; 494 register struct tty *tp; 495 register int unit, line; 496 int error; 497 498 unit = DHU_M2U(minor(dev)); 499 line = DHU_LINE(minor(dev)); 500 sc = dhu_cd.cd_devs[unit]; 501 tp = sc->sc_dhu[line].dhu_tty; 502 503 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 504 if (error >= 0) 505 return (error); 506 error = ttioctl(tp, cmd, data, flag, p); 507 if (error >= 0) 508 return (error); 509 510 switch (cmd) { 511 512 case TIOCSBRK: 513 (void) dhumctl(sc, line, DML_BRK, DMBIS); 514 break; 515 516 case TIOCCBRK: 517 (void) dhumctl(sc, line, DML_BRK, DMBIC); 518 break; 519 520 case TIOCSDTR: 521 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 522 break; 523 524 case TIOCCDTR: 525 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 526 break; 527 528 case TIOCMSET: 529 (void) dhumctl(sc, line, *(int *)data, DMSET); 530 break; 531 532 case TIOCMBIS: 533 (void) dhumctl(sc, line, *(int *)data, DMBIS); 534 break; 535 536 case TIOCMBIC: 537 (void) dhumctl(sc, line, *(int *)data, DMBIC); 538 break; 539 540 case TIOCMGET: 541 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 542 break; 543 544 default: 545 return (ENOTTY); 546 } 547 return (0); 548 } 549 550 struct tty * 551 dhutty(dev) 552 dev_t dev; 553 { 554 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 555 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 556 return (tp); 557 } 558 559 /*ARGSUSED*/ 560 void 561 dhustop(tp, flag) 562 register struct tty *tp; 563 { 564 register struct dhu_softc *sc; 565 register int line; 566 int s; 567 568 s = spltty(); 569 570 if (tp->t_state & TS_BUSY) { 571 572 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 573 line = DHU_LINE(minor(tp->t_dev)); 574 575 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 576 577 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 578 579 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 580 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 581 DHU_READ_WORD(DHU_UBA_LNCTRL) | 582 DHU_LNCTRL_DMA_ABORT); 583 } 584 585 if (!(tp->t_state & TS_TTSTOP)) 586 tp->t_state |= TS_FLUSH; 587 } 588 (void) splx(s); 589 } 590 591 static void 592 dhustart(tp) 593 register struct tty *tp; 594 { 595 register struct dhu_softc *sc; 596 register int line, cc; 597 register int addr; 598 int s; 599 600 s = spltty(); 601 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 602 goto out; 603 if (tp->t_outq.c_cc <= tp->t_lowat) { 604 if (tp->t_state & TS_ASLEEP) { 605 tp->t_state &= ~TS_ASLEEP; 606 wakeup((caddr_t)&tp->t_outq); 607 } 608 selwakeup(&tp->t_wsel); 609 } 610 if (tp->t_outq.c_cc == 0) 611 goto out; 612 cc = ndqb(&tp->t_outq, 0); 613 if (cc == 0) 614 goto out; 615 616 tp->t_state |= TS_BUSY; 617 618 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 619 620 line = DHU_LINE(minor(tp->t_dev)); 621 622 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 623 624 sc->sc_dhu[line].dhu_cc = cc; 625 626 if (cc == 1) { 627 628 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 629 630 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 631 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 632 633 } else { 634 635 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 636 637 addr = UBAI_ADDR(sc->sc_dhu[line].dhu_txaddr) + 638 (tp->t_outq.c_cf - tp->t_outq.c_cs); 639 640 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 641 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 642 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 643 DHU_TBUFAD2_TX_ENABLE); 644 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 645 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 646 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 647 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 648 } 649 out: 650 (void) splx(s); 651 return; 652 } 653 654 static int 655 dhuparam(tp, t) 656 register struct tty *tp; 657 register struct termios *t; 658 { 659 struct dhu_softc *sc; 660 register int cflag = t->c_cflag; 661 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 662 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 663 register unsigned lpr, lnctrl; 664 int unit, line; 665 int s; 666 667 unit = DHU_M2U(minor(tp->t_dev)); 668 line = DHU_LINE(minor(tp->t_dev)); 669 670 sc = dhu_cd.cd_devs[unit]; 671 672 /* check requested parameters */ 673 if (ospeed < 0 || ispeed < 0) 674 return (EINVAL); 675 676 tp->t_ispeed = t->c_ispeed; 677 tp->t_ospeed = t->c_ospeed; 678 tp->t_cflag = cflag; 679 680 if (ospeed == 0) { 681 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 682 return (0); 683 } 684 685 s = spltty(); 686 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 687 688 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 689 690 switch (cflag & CSIZE) { 691 692 case CS5: 693 lpr |= DHU_LPR_5_BIT_CHAR; 694 break; 695 696 case CS6: 697 lpr |= DHU_LPR_6_BIT_CHAR; 698 break; 699 700 case CS7: 701 lpr |= DHU_LPR_7_BIT_CHAR; 702 break; 703 704 default: 705 lpr |= DHU_LPR_8_BIT_CHAR; 706 break; 707 } 708 709 if (cflag & PARENB) 710 lpr |= DHU_LPR_PARENB; 711 if (!(cflag & PARODD)) 712 lpr |= DHU_LPR_EPAR; 713 if (cflag & CSTOPB) 714 lpr |= DHU_LPR_2_STOP; 715 716 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 717 718 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 719 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 720 721 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 722 723 /* Setting LINK.TYPE enables modem signal change interrupts. */ 724 725 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 726 727 /* Enable the auto XON/XOFF feature on the controller */ 728 729 if (t->c_iflag & IXON) 730 lnctrl |= DHU_LNCTRL_OAUTO; 731 else 732 lnctrl &= ~DHU_LNCTRL_OAUTO; 733 734 if (t->c_iflag & IXOFF) 735 lnctrl |= DHU_LNCTRL_IAUTO; 736 else 737 lnctrl &= ~DHU_LNCTRL_IAUTO; 738 739 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 740 741 (void) splx(s); 742 return (0); 743 } 744 745 static int 746 dhuiflow(tp, flag) 747 struct tty *tp; 748 int flag; 749 { 750 register struct dhu_softc *sc; 751 register int line = DHU_LINE(minor(tp->t_dev)); 752 753 if (tp->t_cflag & CRTSCTS) { 754 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 755 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 756 return (1); 757 } 758 return (0); 759 } 760 761 static unsigned 762 dhumctl(sc, line, bits, how) 763 struct dhu_softc *sc; 764 int line, bits, how; 765 { 766 register unsigned status; 767 register unsigned lnctrl; 768 register unsigned mbits; 769 int s; 770 771 s = spltty(); 772 773 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 774 775 mbits = 0; 776 777 /* external signals as seen from the port */ 778 779 status = DHU_READ_WORD(DHU_UBA_STAT); 780 781 if (status & DHU_STAT_CTS) 782 mbits |= DML_CTS; 783 784 if (status & DHU_STAT_DCD) 785 mbits |= DML_DCD; 786 787 if (status & DHU_STAT_DSR) 788 mbits |= DML_DSR; 789 790 if (status & DHU_STAT_RI) 791 mbits |= DML_RI; 792 793 /* internal signals/state delivered to port */ 794 795 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 796 797 if (lnctrl & DHU_LNCTRL_RTS) 798 mbits |= DML_RTS; 799 800 if (lnctrl & DHU_LNCTRL_DTR) 801 mbits |= DML_DTR; 802 803 if (lnctrl & DHU_LNCTRL_BREAK) 804 mbits |= DML_BRK; 805 806 switch (how) { 807 808 case DMSET: 809 mbits = bits; 810 break; 811 812 case DMBIS: 813 mbits |= bits; 814 break; 815 816 case DMBIC: 817 mbits &= ~bits; 818 break; 819 820 case DMGET: 821 (void) splx(s); 822 return (mbits); 823 } 824 825 if (mbits & DML_RTS) 826 lnctrl |= DHU_LNCTRL_RTS; 827 else 828 lnctrl &= ~DHU_LNCTRL_RTS; 829 830 if (mbits & DML_DTR) 831 lnctrl |= DHU_LNCTRL_DTR; 832 else 833 lnctrl &= ~DHU_LNCTRL_DTR; 834 835 if (mbits & DML_BRK) 836 lnctrl |= DHU_LNCTRL_BREAK; 837 else 838 lnctrl &= ~DHU_LNCTRL_BREAK; 839 840 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 841 842 (void) splx(s); 843 return (mbits); 844 } 845
Indexes created Sat Nov 01 05:10:12 GMT 2025