dhu.c revision 1.16
1 /* $NetBSD: dhu.c,v 1.16 1999/06/06 19:14:48 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 #include <machine/scb.h> 55 56 #include <dev/qbus/ubavar.h> 57 58 #include <dev/qbus/dhureg.h> 59 60 #include "ioconf.h" 61 62 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 63 64 #define NDHULINE 16 65 66 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 67 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 68 69 struct dhu_softc { 70 struct device sc_dev; /* Device struct used by config */ 71 int sc_type; /* controller type, DHU or DHV */ 72 bus_space_tag_t sc_iot; 73 bus_space_handle_t sc_ioh; 74 bus_dma_tag_t sc_dmat; 75 struct { 76 struct tty *dhu_tty; /* what we work on */ 77 bus_dmamap_t dhu_dmah; 78 int dhu_state; /* to manage TX output status */ 79 short dhu_cc; /* character count on TX */ 80 short dhu_modem; /* modem bits state */ 81 } sc_dhu[NDHULINE]; 82 }; 83 84 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 85 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 86 87 #define STATE_IDLE 000 /* no current output in progress */ 88 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 89 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 90 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 91 92 /* Flags used to monitor modem bits, make them understood outside driver */ 93 94 #define DML_DTR TIOCM_DTR 95 #define DML_RTS TIOCM_RTS 96 #define DML_CTS TIOCM_CTS 97 #define DML_DCD TIOCM_CD 98 #define DML_RI TIOCM_RI 99 #define DML_DSR TIOCM_DSR 100 #define DML_BRK 0100000 /* no equivalent, we will mask */ 101 102 #define DHU_READ_WORD(reg) \ 103 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 104 #define DHU_WRITE_WORD(reg, val) \ 105 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 106 #define DHU_READ_BYTE(reg) \ 107 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 108 #define DHU_WRITE_BYTE(reg, val) \ 109 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 110 111 112 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 113 /* a baud rate from the same group. So limiting to B is likely */ 114 /* best, although clone boards like the ABLE QHV allow all settings. */ 115 116 static struct speedtab dhuspeedtab[] = { 117 { 0, 0 }, /* Groups */ 118 { 50, DHU_LPR_B50 }, /* A */ 119 { 75, DHU_LPR_B75 }, /* B */ 120 { 110, DHU_LPR_B110 }, /* A and B */ 121 { 134, DHU_LPR_B134 }, /* A and B */ 122 { 150, DHU_LPR_B150 }, /* B */ 123 { 300, DHU_LPR_B300 }, /* A and B */ 124 { 600, DHU_LPR_B600 }, /* A and B */ 125 { 1200, DHU_LPR_B1200 }, /* A and B */ 126 { 1800, DHU_LPR_B1800 }, /* B */ 127 { 2000, DHU_LPR_B2000 }, /* B */ 128 { 2400, DHU_LPR_B2400 }, /* A and B */ 129 { 4800, DHU_LPR_B4800 }, /* A and B */ 130 { 7200, DHU_LPR_B7200 }, /* A */ 131 { 9600, DHU_LPR_B9600 }, /* A and B */ 132 { 19200, DHU_LPR_B19200 }, /* B */ 133 { 38400, DHU_LPR_B38400 }, /* A */ 134 { -1, -1 } 135 }; 136 137 static int dhu_match __P((struct device *, struct cfdata *, void *)); 138 static void dhu_attach __P((struct device *, struct device *, void *)); 139 static void dhurint __P((int)); 140 static void dhuxint __P((int)); 141 static void dhustart __P((struct tty *)); 142 static int dhuparam __P((struct tty *, struct termios *)); 143 static int dhuiflow __P((struct tty *, int)); 144 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 145 int dhuopen __P((dev_t, int, int, struct proc *)); 146 int dhuclose __P((dev_t, int, int, struct proc *)); 147 int dhuread __P((dev_t, struct uio *, int)); 148 int dhuwrite __P((dev_t, struct uio *, int)); 149 int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); 150 void dhustop __P((struct tty *, int)); 151 struct tty * dhutty __P((dev_t)); 152 153 struct cfattach dhu_ca = { 154 sizeof(struct dhu_softc), dhu_match, dhu_attach 155 }; 156 157 /* Autoconfig handles: setup the controller to interrupt, */ 158 /* then complete the housecleaning for full operation */ 159 160 static int 161 dhu_match(parent, cf, aux) 162 struct device *parent; 163 struct cfdata *cf; 164 void *aux; 165 { 166 struct uba_attach_args *ua = aux; 167 register int n; 168 169 /* Reset controller to initialize, enable TX/RX interrupts */ 170 /* to catch floating vector info elsewhere when completed */ 171 172 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 173 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 174 175 /* Now wait up to 3 seconds for self-test to complete. */ 176 177 for (n = 0; n < 300; n++) { 178 DELAY(10000); 179 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 180 DHU_CSR_MASTER_RESET) == 0) 181 break; 182 } 183 184 /* If the RESET did not clear after 3 seconds, */ 185 /* the controller must be broken. */ 186 187 if (n >= 300) 188 return 0; 189 190 /* Check whether diagnostic run has signalled a failure. */ 191 192 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 193 DHU_CSR_DIAG_FAIL) != 0) 194 return 0; 195 196 /* Register the RX interrupt handler */ 197 198 ua->ua_ivec = dhurint; 199 200 return 1; 201 } 202 203 static void 204 dhu_attach(parent, self, aux) 205 struct device *parent, *self; 206 void *aux; 207 { 208 register struct dhu_softc *sc = (void *)self; 209 register struct uba_attach_args *ua = aux; 210 register unsigned c; 211 register int n, i; 212 213 sc->sc_iot = ua->ua_iot; 214 sc->sc_ioh = ua->ua_ioh; 215 sc->sc_dmat = ua->ua_dmat; 216 /* Process the 8 bytes of diagnostic info put into */ 217 /* the FIFO following the master reset operation. */ 218 219 printf("\n%s:", self->dv_xname); 220 for (n = 0; n < 8; n++) { 221 c = DHU_READ_WORD(DHU_UBA_RBUF); 222 223 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 224 if ((c&0200) == 0000) 225 printf(" rom(%d) version %d", 226 ((c>>1)&01), ((c>>2)&037)); 227 else if (((c>>2)&07) != 0) 228 printf(" diag-error(proc%d)=%x", 229 ((c>>1)&01), ((c>>2)&07)); 230 } 231 } 232 233 c = DHU_READ_WORD(DHU_UBA_STAT); 234 235 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 236 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 237 238 for (i = 0; i < sc->sc_type; i++) { 239 struct tty *tp; 240 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 241 sc->sc_dhu[i].dhu_state = STATE_IDLE; 242 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 243 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 244 &sc->sc_dhu[i].dhu_dmah); 245 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 246 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 247 248 } 249 250 /* Now stuff TX interrupt handler in place */ 251 scb_vecalloc(ua->ua_cvec + 4, dhuxint, self->dv_unit, SCB_ISTACK); 252 } 253 254 /* Receiver Interrupt */ 255 256 static void 257 dhurint(unit) 258 int unit; 259 { 260 struct dhu_softc *sc = dhu_cd.cd_devs[unit]; 261 register struct tty *tp; 262 register int cc, line; 263 register unsigned c, delta; 264 int overrun = 0; 265 266 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 267 268 /* Ignore diagnostic FIFO entries. */ 269 270 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 271 continue; 272 273 cc = c & 0xFF; 274 line = DHU_LINE(c>>8); 275 tp = sc->sc_dhu[line].dhu_tty; 276 277 /* LINK.TYPE is set so we get modem control FIFO entries */ 278 279 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 280 c = (c << 8); 281 /* Do MDMBUF flow control, wakeup sleeping opens */ 282 if (c & DHU_STAT_DCD) { 283 if (!(tp->t_state & TS_CARR_ON)) 284 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 285 } 286 else if ((tp->t_state & TS_CARR_ON) && 287 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) 288 (void) dhumctl(sc, line, 0, DMSET); 289 290 /* Do CRTSCTS flow control */ 291 delta = c ^ sc->sc_dhu[line].dhu_modem; 292 sc->sc_dhu[line].dhu_modem = c; 293 if ((delta & DHU_STAT_CTS) && 294 (tp->t_state & TS_ISOPEN) && 295 (tp->t_cflag & CRTSCTS)) { 296 if (c & DHU_STAT_CTS) { 297 tp->t_state &= ~TS_TTSTOP; 298 ttstart(tp); 299 } else { 300 tp->t_state |= TS_TTSTOP; 301 dhustop(tp, 0); 302 } 303 } 304 continue; 305 } 306 307 if (!(tp->t_state & TS_ISOPEN)) { 308 wakeup((caddr_t)&tp->t_rawq); 309 continue; 310 } 311 312 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 313 log(LOG_WARNING, "%s: silo overflow, line %d\n", 314 sc->sc_dev.dv_xname, line); 315 overrun = 1; 316 } 317 /* A BREAK key will appear as a NULL with a framing error */ 318 if (c & DHU_RBUF_FRAMING_ERR) 319 cc |= TTY_FE; 320 if (c & DHU_RBUF_PARITY_ERR) 321 cc |= TTY_PE; 322 323 (*linesw[tp->t_line].l_rint)(cc, tp); 324 } 325 } 326 327 /* Transmitter Interrupt */ 328 329 static void 330 dhuxint(unit) 331 int unit; 332 { 333 register struct dhu_softc *sc = dhu_cd.cd_devs[unit]; 334 register struct tty *tp; 335 register int line; 336 337 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 338 339 tp = sc->sc_dhu[line].dhu_tty; 340 341 tp->t_state &= ~TS_BUSY; 342 if (tp->t_state & TS_FLUSH) 343 tp->t_state &= ~TS_FLUSH; 344 else { 345 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 346 sc->sc_dhu[line].dhu_cc -= 347 DHU_READ_WORD(DHU_UBA_TBUFCNT); 348 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 349 sc->sc_dhu[line].dhu_cc = 0; 350 } 351 352 sc->sc_dhu[line].dhu_state = STATE_IDLE; 353 354 if (tp->t_line) 355 (*linesw[tp->t_line].l_start)(tp); 356 else 357 dhustart(tp); 358 } 359 360 int 361 dhuopen(dev, flag, mode, p) 362 dev_t dev; 363 int flag, mode; 364 struct proc *p; 365 { 366 register struct tty *tp; 367 register int unit, line; 368 struct dhu_softc *sc; 369 int s, error = 0; 370 371 unit = DHU_M2U(minor(dev)); 372 line = DHU_LINE(minor(dev)); 373 374 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 375 return (ENXIO); 376 377 sc = dhu_cd.cd_devs[unit]; 378 379 if (line >= sc->sc_type) 380 return ENXIO; 381 382 s = spltty(); 383 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 384 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 385 (void) splx(s); 386 387 tp = sc->sc_dhu[line].dhu_tty; 388 389 tp->t_oproc = dhustart; 390 tp->t_param = dhuparam; 391 tp->t_hwiflow = dhuiflow; 392 tp->t_dev = dev; 393 if ((tp->t_state & TS_ISOPEN) == 0) { 394 ttychars(tp); 395 if (tp->t_ispeed == 0) { 396 tp->t_iflag = TTYDEF_IFLAG; 397 tp->t_oflag = TTYDEF_OFLAG; 398 tp->t_cflag = TTYDEF_CFLAG; 399 tp->t_lflag = TTYDEF_LFLAG; 400 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 401 } 402 (void) dhuparam(tp, &tp->t_termios); 403 ttsetwater(tp); 404 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 405 return (EBUSY); 406 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 407 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 408 tp->t_state |= TS_CARR_ON; 409 s = spltty(); 410 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 411 !(tp->t_state & TS_CARR_ON)) { 412 tp->t_wopen++; 413 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 414 TTIPRI | PCATCH, ttopen, 0); 415 tp->t_wopen--; 416 if (error) 417 break; 418 } 419 (void) splx(s); 420 if (error) 421 return (error); 422 return ((*linesw[tp->t_line].l_open)(dev, tp)); 423 } 424 425 /*ARGSUSED*/ 426 int 427 dhuclose(dev, flag, mode, p) 428 dev_t dev; 429 int flag, mode; 430 struct proc *p; 431 { 432 register struct tty *tp; 433 register int unit, line; 434 struct dhu_softc *sc; 435 436 unit = DHU_M2U(minor(dev)); 437 line = DHU_LINE(minor(dev)); 438 439 sc = dhu_cd.cd_devs[unit]; 440 441 tp = sc->sc_dhu[line].dhu_tty; 442 443 (*linesw[tp->t_line].l_close)(tp, flag); 444 445 /* Make sure a BREAK state is not left enabled. */ 446 447 (void) dhumctl(sc, line, DML_BRK, DMBIC); 448 449 /* Do a hangup if so required. */ 450 451 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 452 !(tp->t_state & TS_ISOPEN)) 453 (void) dhumctl(sc, line, 0, DMSET); 454 455 return (ttyclose(tp)); 456 } 457 458 int 459 dhuread(dev, uio, flag) 460 dev_t dev; 461 struct uio *uio; 462 { 463 register struct dhu_softc *sc; 464 register struct tty *tp; 465 466 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 467 468 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 469 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 470 } 471 472 int 473 dhuwrite(dev, uio, flag) 474 dev_t dev; 475 struct uio *uio; 476 { 477 register struct dhu_softc *sc; 478 register struct tty *tp; 479 480 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 481 482 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 483 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 484 } 485 486 /*ARGSUSED*/ 487 int 488 dhuioctl(dev, cmd, data, flag, p) 489 dev_t dev; 490 u_long cmd; 491 caddr_t data; 492 int flag; 493 struct proc *p; 494 { 495 register struct dhu_softc *sc; 496 register struct tty *tp; 497 register int unit, line; 498 int error; 499 500 unit = DHU_M2U(minor(dev)); 501 line = DHU_LINE(minor(dev)); 502 sc = dhu_cd.cd_devs[unit]; 503 tp = sc->sc_dhu[line].dhu_tty; 504 505 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 506 if (error >= 0) 507 return (error); 508 error = ttioctl(tp, cmd, data, flag, p); 509 if (error >= 0) 510 return (error); 511 512 switch (cmd) { 513 514 case TIOCSBRK: 515 (void) dhumctl(sc, line, DML_BRK, DMBIS); 516 break; 517 518 case TIOCCBRK: 519 (void) dhumctl(sc, line, DML_BRK, DMBIC); 520 break; 521 522 case TIOCSDTR: 523 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 524 break; 525 526 case TIOCCDTR: 527 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 528 break; 529 530 case TIOCMSET: 531 (void) dhumctl(sc, line, *(int *)data, DMSET); 532 break; 533 534 case TIOCMBIS: 535 (void) dhumctl(sc, line, *(int *)data, DMBIS); 536 break; 537 538 case TIOCMBIC: 539 (void) dhumctl(sc, line, *(int *)data, DMBIC); 540 break; 541 542 case TIOCMGET: 543 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 544 break; 545 546 default: 547 return (ENOTTY); 548 } 549 return (0); 550 } 551 552 struct tty * 553 dhutty(dev) 554 dev_t dev; 555 { 556 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 557 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 558 return (tp); 559 } 560 561 /*ARGSUSED*/ 562 void 563 dhustop(tp, flag) 564 register struct tty *tp; 565 { 566 register struct dhu_softc *sc; 567 register int line; 568 int s; 569 570 s = spltty(); 571 572 if (tp->t_state & TS_BUSY) { 573 574 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 575 line = DHU_LINE(minor(tp->t_dev)); 576 577 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 578 579 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 580 581 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 582 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 583 DHU_READ_WORD(DHU_UBA_LNCTRL) | 584 DHU_LNCTRL_DMA_ABORT); 585 } 586 587 if (!(tp->t_state & TS_TTSTOP)) 588 tp->t_state |= TS_FLUSH; 589 } 590 (void) splx(s); 591 } 592 593 static void 594 dhustart(tp) 595 register struct tty *tp; 596 { 597 register struct dhu_softc *sc; 598 register int line, cc; 599 register int addr; 600 int s; 601 602 s = spltty(); 603 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 604 goto out; 605 if (tp->t_outq.c_cc <= tp->t_lowat) { 606 if (tp->t_state & TS_ASLEEP) { 607 tp->t_state &= ~TS_ASLEEP; 608 wakeup((caddr_t)&tp->t_outq); 609 } 610 selwakeup(&tp->t_wsel); 611 } 612 if (tp->t_outq.c_cc == 0) 613 goto out; 614 cc = ndqb(&tp->t_outq, 0); 615 if (cc == 0) 616 goto out; 617 618 tp->t_state |= TS_BUSY; 619 620 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 621 622 line = DHU_LINE(minor(tp->t_dev)); 623 624 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 625 626 sc->sc_dhu[line].dhu_cc = cc; 627 628 if (cc == 1) { 629 630 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 631 632 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 633 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 634 635 } else { 636 637 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 638 639 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 640 (tp->t_outq.c_cf - tp->t_outq.c_cs); 641 642 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 643 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 644 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 645 DHU_TBUFAD2_TX_ENABLE); 646 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 647 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 648 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 649 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 650 } 651 out: 652 (void) splx(s); 653 return; 654 } 655 656 static int 657 dhuparam(tp, t) 658 register struct tty *tp; 659 register struct termios *t; 660 { 661 struct dhu_softc *sc; 662 register int cflag = t->c_cflag; 663 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 664 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 665 register unsigned lpr, lnctrl; 666 int unit, line; 667 int s; 668 669 unit = DHU_M2U(minor(tp->t_dev)); 670 line = DHU_LINE(minor(tp->t_dev)); 671 672 sc = dhu_cd.cd_devs[unit]; 673 674 /* check requested parameters */ 675 if (ospeed < 0 || ispeed < 0) 676 return (EINVAL); 677 678 tp->t_ispeed = t->c_ispeed; 679 tp->t_ospeed = t->c_ospeed; 680 tp->t_cflag = cflag; 681 682 if (ospeed == 0) { 683 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 684 return (0); 685 } 686 687 s = spltty(); 688 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 689 690 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 691 692 switch (cflag & CSIZE) { 693 694 case CS5: 695 lpr |= DHU_LPR_5_BIT_CHAR; 696 break; 697 698 case CS6: 699 lpr |= DHU_LPR_6_BIT_CHAR; 700 break; 701 702 case CS7: 703 lpr |= DHU_LPR_7_BIT_CHAR; 704 break; 705 706 default: 707 lpr |= DHU_LPR_8_BIT_CHAR; 708 break; 709 } 710 711 if (cflag & PARENB) 712 lpr |= DHU_LPR_PARENB; 713 if (!(cflag & PARODD)) 714 lpr |= DHU_LPR_EPAR; 715 if (cflag & CSTOPB) 716 lpr |= DHU_LPR_2_STOP; 717 718 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 719 720 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 721 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 722 723 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 724 725 /* Setting LINK.TYPE enables modem signal change interrupts. */ 726 727 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 728 729 /* Enable the auto XON/XOFF feature on the controller */ 730 731 if (t->c_iflag & IXON) 732 lnctrl |= DHU_LNCTRL_OAUTO; 733 else 734 lnctrl &= ~DHU_LNCTRL_OAUTO; 735 736 if (t->c_iflag & IXOFF) 737 lnctrl |= DHU_LNCTRL_IAUTO; 738 else 739 lnctrl &= ~DHU_LNCTRL_IAUTO; 740 741 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 742 743 (void) splx(s); 744 return (0); 745 } 746 747 static int 748 dhuiflow(tp, flag) 749 struct tty *tp; 750 int flag; 751 { 752 register struct dhu_softc *sc; 753 register int line = DHU_LINE(minor(tp->t_dev)); 754 755 if (tp->t_cflag & CRTSCTS) { 756 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 757 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 758 return (1); 759 } 760 return (0); 761 } 762 763 static unsigned 764 dhumctl(sc, line, bits, how) 765 struct dhu_softc *sc; 766 int line, bits, how; 767 { 768 register unsigned status; 769 register unsigned lnctrl; 770 register unsigned mbits; 771 int s; 772 773 s = spltty(); 774 775 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 776 777 mbits = 0; 778 779 /* external signals as seen from the port */ 780 781 status = DHU_READ_WORD(DHU_UBA_STAT); 782 783 if (status & DHU_STAT_CTS) 784 mbits |= DML_CTS; 785 786 if (status & DHU_STAT_DCD) 787 mbits |= DML_DCD; 788 789 if (status & DHU_STAT_DSR) 790 mbits |= DML_DSR; 791 792 if (status & DHU_STAT_RI) 793 mbits |= DML_RI; 794 795 /* internal signals/state delivered to port */ 796 797 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 798 799 if (lnctrl & DHU_LNCTRL_RTS) 800 mbits |= DML_RTS; 801 802 if (lnctrl & DHU_LNCTRL_DTR) 803 mbits |= DML_DTR; 804 805 if (lnctrl & DHU_LNCTRL_BREAK) 806 mbits |= DML_BRK; 807 808 switch (how) { 809 810 case DMSET: 811 mbits = bits; 812 break; 813 814 case DMBIS: 815 mbits |= bits; 816 break; 817 818 case DMBIC: 819 mbits &= ~bits; 820 break; 821 822 case DMGET: 823 (void) splx(s); 824 return (mbits); 825 } 826 827 if (mbits & DML_RTS) 828 lnctrl |= DHU_LNCTRL_RTS; 829 else 830 lnctrl &= ~DHU_LNCTRL_RTS; 831 832 if (mbits & DML_DTR) 833 lnctrl |= DHU_LNCTRL_DTR; 834 else 835 lnctrl &= ~DHU_LNCTRL_DTR; 836 837 if (mbits & DML_BRK) 838 lnctrl |= DHU_LNCTRL_BREAK; 839 else 840 lnctrl &= ~DHU_LNCTRL_BREAK; 841 842 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 843 844 (void) splx(s); 845 return (mbits); 846 } 847
Indexes created Tue Sep 23 07:09:52 GMT 2025