dhu.c revision 1.19
1 /* $NetBSD: dhu.c,v 1.19 2000/06/04 06:17:01 matt Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 #include <machine/scb.h> 55 56 #include <dev/qbus/ubavar.h> 57 58 #include <dev/qbus/dhureg.h> 59 60 #include "ioconf.h" 61 62 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 63 64 #define NDHULINE 16 65 66 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 67 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 68 69 struct dhu_softc { 70 struct device sc_dev; /* Device struct used by config */ 71 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 72 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 73 int sc_type; /* controller type, DHU or DHV */ 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 bus_dma_tag_t sc_dmat; 77 struct { 78 struct tty *dhu_tty; /* what we work on */ 79 bus_dmamap_t dhu_dmah; 80 int dhu_state; /* to manage TX output status */ 81 short dhu_cc; /* character count on TX */ 82 short dhu_modem; /* modem bits state */ 83 } sc_dhu[NDHULINE]; 84 }; 85 86 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 87 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 88 89 #define STATE_IDLE 000 /* no current output in progress */ 90 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 91 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 92 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 93 94 /* Flags used to monitor modem bits, make them understood outside driver */ 95 96 #define DML_DTR TIOCM_DTR 97 #define DML_RTS TIOCM_RTS 98 #define DML_CTS TIOCM_CTS 99 #define DML_DCD TIOCM_CD 100 #define DML_RI TIOCM_RI 101 #define DML_DSR TIOCM_DSR 102 #define DML_BRK 0100000 /* no equivalent, we will mask */ 103 104 #define DHU_READ_WORD(reg) \ 105 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 106 #define DHU_WRITE_WORD(reg, val) \ 107 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 108 #define DHU_READ_BYTE(reg) \ 109 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 110 #define DHU_WRITE_BYTE(reg, val) \ 111 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 112 113 114 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 115 /* a baud rate from the same group. So limiting to B is likely */ 116 /* best, although clone boards like the ABLE QHV allow all settings. */ 117 118 static struct speedtab dhuspeedtab[] = { 119 { 0, 0 }, /* Groups */ 120 { 50, DHU_LPR_B50 }, /* A */ 121 { 75, DHU_LPR_B75 }, /* B */ 122 { 110, DHU_LPR_B110 }, /* A and B */ 123 { 134, DHU_LPR_B134 }, /* A and B */ 124 { 150, DHU_LPR_B150 }, /* B */ 125 { 300, DHU_LPR_B300 }, /* A and B */ 126 { 600, DHU_LPR_B600 }, /* A and B */ 127 { 1200, DHU_LPR_B1200 }, /* A and B */ 128 { 1800, DHU_LPR_B1800 }, /* B */ 129 { 2000, DHU_LPR_B2000 }, /* B */ 130 { 2400, DHU_LPR_B2400 }, /* A and B */ 131 { 4800, DHU_LPR_B4800 }, /* A and B */ 132 { 7200, DHU_LPR_B7200 }, /* A */ 133 { 9600, DHU_LPR_B9600 }, /* A and B */ 134 { 19200, DHU_LPR_B19200 }, /* B */ 135 { 38400, DHU_LPR_B38400 }, /* A */ 136 { -1, -1 } 137 }; 138 139 static int dhu_match __P((struct device *, struct cfdata *, void *)); 140 static void dhu_attach __P((struct device *, struct device *, void *)); 141 static void dhurint __P((void *)); 142 static void dhuxint __P((void *)); 143 static void dhustart __P((struct tty *)); 144 static int dhuparam __P((struct tty *, struct termios *)); 145 static int dhuiflow __P((struct tty *, int)); 146 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 147 int dhuopen __P((dev_t, int, int, struct proc *)); 148 int dhuclose __P((dev_t, int, int, struct proc *)); 149 int dhuread __P((dev_t, struct uio *, int)); 150 int dhuwrite __P((dev_t, struct uio *, int)); 151 int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); 152 void dhustop __P((struct tty *, int)); 153 struct tty * dhutty __P((dev_t)); 154 155 struct cfattach dhu_ca = { 156 sizeof(struct dhu_softc), dhu_match, dhu_attach 157 }; 158 159 /* Autoconfig handles: setup the controller to interrupt, */ 160 /* then complete the housecleaning for full operation */ 161 162 static int 163 dhu_match(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 struct uba_attach_args *ua = aux; 169 int n; 170 171 /* Reset controller to initialize, enable TX/RX interrupts */ 172 /* to catch floating vector info elsewhere when completed */ 173 174 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 175 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 176 177 /* Now wait up to 3 seconds for self-test to complete. */ 178 179 for (n = 0; n < 300; n++) { 180 DELAY(10000); 181 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 182 DHU_CSR_MASTER_RESET) == 0) 183 break; 184 } 185 186 /* If the RESET did not clear after 3 seconds, */ 187 /* the controller must be broken. */ 188 189 if (n >= 300) 190 return 0; 191 192 /* Check whether diagnostic run has signalled a failure. */ 193 194 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 195 DHU_CSR_DIAG_FAIL) != 0) 196 return 0; 197 198 return 1; 199 } 200 201 static void 202 dhu_attach(parent, self, aux) 203 struct device *parent, *self; 204 void *aux; 205 { 206 struct dhu_softc *sc = (void *)self; 207 struct uba_attach_args *ua = aux; 208 unsigned c; 209 int n, i; 210 211 sc->sc_iot = ua->ua_iot; 212 sc->sc_ioh = ua->ua_ioh; 213 sc->sc_dmat = ua->ua_dmat; 214 /* Process the 8 bytes of diagnostic info put into */ 215 /* the FIFO following the master reset operation. */ 216 217 printf("\n%s:", self->dv_xname); 218 for (n = 0; n < 8; n++) { 219 c = DHU_READ_WORD(DHU_UBA_RBUF); 220 221 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 222 if ((c&0200) == 0000) 223 printf(" rom(%d) version %d", 224 ((c>>1)&01), ((c>>2)&037)); 225 else if (((c>>2)&07) != 0) 226 printf(" diag-error(proc%d)=%x", 227 ((c>>1)&01), ((c>>2)&07)); 228 } 229 } 230 231 c = DHU_READ_WORD(DHU_UBA_STAT); 232 233 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 234 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 235 236 for (i = 0; i < sc->sc_type; i++) { 237 struct tty *tp; 238 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 239 sc->sc_dhu[i].dhu_state = STATE_IDLE; 240 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 241 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 242 &sc->sc_dhu[i].dhu_dmah); 243 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 244 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 245 246 } 247 248 /* Now establish RX & TX interrupt handlers */ 249 250 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 251 dhurint, sc, &sc->sc_rintrcnt); 252 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 253 dhuxint, sc, &sc->sc_tintrcnt); 254 evcnt_attach(&sc->sc_dev, "rintr", &sc->sc_rintrcnt); 255 evcnt_attach(&sc->sc_dev, "tintr", &sc->sc_tintrcnt); 256 } 257 258 /* Receiver Interrupt */ 259 260 static void 261 dhurint(arg) 262 void *arg; 263 { 264 struct dhu_softc *sc = arg; 265 struct tty *tp; 266 int cc, line; 267 unsigned c, delta; 268 int overrun = 0; 269 270 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 271 272 /* Ignore diagnostic FIFO entries. */ 273 274 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 275 continue; 276 277 cc = c & 0xFF; 278 line = DHU_LINE(c>>8); 279 tp = sc->sc_dhu[line].dhu_tty; 280 281 /* LINK.TYPE is set so we get modem control FIFO entries */ 282 283 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 284 c = (c << 8); 285 /* Do MDMBUF flow control, wakeup sleeping opens */ 286 if (c & DHU_STAT_DCD) { 287 if (!(tp->t_state & TS_CARR_ON)) 288 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 289 } 290 else if ((tp->t_state & TS_CARR_ON) && 291 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) 292 (void) dhumctl(sc, line, 0, DMSET); 293 294 /* Do CRTSCTS flow control */ 295 delta = c ^ sc->sc_dhu[line].dhu_modem; 296 sc->sc_dhu[line].dhu_modem = c; 297 if ((delta & DHU_STAT_CTS) && 298 (tp->t_state & TS_ISOPEN) && 299 (tp->t_cflag & CRTSCTS)) { 300 if (c & DHU_STAT_CTS) { 301 tp->t_state &= ~TS_TTSTOP; 302 ttstart(tp); 303 } else { 304 tp->t_state |= TS_TTSTOP; 305 dhustop(tp, 0); 306 } 307 } 308 continue; 309 } 310 311 if (!(tp->t_state & TS_ISOPEN)) { 312 wakeup((caddr_t)&tp->t_rawq); 313 continue; 314 } 315 316 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 317 log(LOG_WARNING, "%s: silo overflow, line %d\n", 318 sc->sc_dev.dv_xname, line); 319 overrun = 1; 320 } 321 /* A BREAK key will appear as a NULL with a framing error */ 322 if (c & DHU_RBUF_FRAMING_ERR) 323 cc |= TTY_FE; 324 if (c & DHU_RBUF_PARITY_ERR) 325 cc |= TTY_PE; 326 327 (*linesw[tp->t_line].l_rint)(cc, tp); 328 } 329 } 330 331 /* Transmitter Interrupt */ 332 333 static void 334 dhuxint(arg) 335 void *arg; 336 { 337 struct dhu_softc *sc = arg; 338 struct tty *tp; 339 int line; 340 341 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 342 343 tp = sc->sc_dhu[line].dhu_tty; 344 345 tp->t_state &= ~TS_BUSY; 346 if (tp->t_state & TS_FLUSH) 347 tp->t_state &= ~TS_FLUSH; 348 else { 349 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 350 sc->sc_dhu[line].dhu_cc -= 351 DHU_READ_WORD(DHU_UBA_TBUFCNT); 352 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 353 sc->sc_dhu[line].dhu_cc = 0; 354 } 355 356 sc->sc_dhu[line].dhu_state = STATE_IDLE; 357 358 if (tp->t_line) 359 (*linesw[tp->t_line].l_start)(tp); 360 else 361 dhustart(tp); 362 } 363 364 int 365 dhuopen(dev, flag, mode, p) 366 dev_t dev; 367 int flag, mode; 368 struct proc *p; 369 { 370 struct tty *tp; 371 int unit, line; 372 struct dhu_softc *sc; 373 int s, error = 0; 374 375 unit = DHU_M2U(minor(dev)); 376 line = DHU_LINE(minor(dev)); 377 378 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 379 return (ENXIO); 380 381 sc = dhu_cd.cd_devs[unit]; 382 383 if (line >= sc->sc_type) 384 return ENXIO; 385 386 s = spltty(); 387 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 388 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 389 (void) splx(s); 390 391 tp = sc->sc_dhu[line].dhu_tty; 392 393 tp->t_oproc = dhustart; 394 tp->t_param = dhuparam; 395 tp->t_hwiflow = dhuiflow; 396 tp->t_dev = dev; 397 if ((tp->t_state & TS_ISOPEN) == 0) { 398 ttychars(tp); 399 if (tp->t_ispeed == 0) { 400 tp->t_iflag = TTYDEF_IFLAG; 401 tp->t_oflag = TTYDEF_OFLAG; 402 tp->t_cflag = TTYDEF_CFLAG; 403 tp->t_lflag = TTYDEF_LFLAG; 404 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 405 } 406 (void) dhuparam(tp, &tp->t_termios); 407 ttsetwater(tp); 408 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 409 return (EBUSY); 410 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 411 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 412 tp->t_state |= TS_CARR_ON; 413 s = spltty(); 414 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 415 !(tp->t_state & TS_CARR_ON)) { 416 tp->t_wopen++; 417 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 418 TTIPRI | PCATCH, ttopen, 0); 419 tp->t_wopen--; 420 if (error) 421 break; 422 } 423 (void) splx(s); 424 if (error) 425 return (error); 426 return ((*linesw[tp->t_line].l_open)(dev, tp)); 427 } 428 429 /*ARGSUSED*/ 430 int 431 dhuclose(dev, flag, mode, p) 432 dev_t dev; 433 int flag, mode; 434 struct proc *p; 435 { 436 struct tty *tp; 437 int unit, line; 438 struct dhu_softc *sc; 439 440 unit = DHU_M2U(minor(dev)); 441 line = DHU_LINE(minor(dev)); 442 443 sc = dhu_cd.cd_devs[unit]; 444 445 tp = sc->sc_dhu[line].dhu_tty; 446 447 (*linesw[tp->t_line].l_close)(tp, flag); 448 449 /* Make sure a BREAK state is not left enabled. */ 450 451 (void) dhumctl(sc, line, DML_BRK, DMBIC); 452 453 /* Do a hangup if so required. */ 454 455 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 456 !(tp->t_state & TS_ISOPEN)) 457 (void) dhumctl(sc, line, 0, DMSET); 458 459 return (ttyclose(tp)); 460 } 461 462 int 463 dhuread(dev, uio, flag) 464 dev_t dev; 465 struct uio *uio; 466 { 467 struct dhu_softc *sc; 468 struct tty *tp; 469 470 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 471 472 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 473 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 474 } 475 476 int 477 dhuwrite(dev, uio, flag) 478 dev_t dev; 479 struct uio *uio; 480 { 481 struct dhu_softc *sc; 482 struct tty *tp; 483 484 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 485 486 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 487 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 488 } 489 490 /*ARGSUSED*/ 491 int 492 dhuioctl(dev, cmd, data, flag, p) 493 dev_t dev; 494 u_long cmd; 495 caddr_t data; 496 int flag; 497 struct proc *p; 498 { 499 struct dhu_softc *sc; 500 struct tty *tp; 501 int unit, line; 502 int error; 503 504 unit = DHU_M2U(minor(dev)); 505 line = DHU_LINE(minor(dev)); 506 sc = dhu_cd.cd_devs[unit]; 507 tp = sc->sc_dhu[line].dhu_tty; 508 509 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 510 if (error >= 0) 511 return (error); 512 error = ttioctl(tp, cmd, data, flag, p); 513 if (error >= 0) 514 return (error); 515 516 switch (cmd) { 517 518 case TIOCSBRK: 519 (void) dhumctl(sc, line, DML_BRK, DMBIS); 520 break; 521 522 case TIOCCBRK: 523 (void) dhumctl(sc, line, DML_BRK, DMBIC); 524 break; 525 526 case TIOCSDTR: 527 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 528 break; 529 530 case TIOCCDTR: 531 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 532 break; 533 534 case TIOCMSET: 535 (void) dhumctl(sc, line, *(int *)data, DMSET); 536 break; 537 538 case TIOCMBIS: 539 (void) dhumctl(sc, line, *(int *)data, DMBIS); 540 break; 541 542 case TIOCMBIC: 543 (void) dhumctl(sc, line, *(int *)data, DMBIC); 544 break; 545 546 case TIOCMGET: 547 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 548 break; 549 550 default: 551 return (ENOTTY); 552 } 553 return (0); 554 } 555 556 struct tty * 557 dhutty(dev) 558 dev_t dev; 559 { 560 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 561 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 562 return (tp); 563 } 564 565 /*ARGSUSED*/ 566 void 567 dhustop(tp, flag) 568 struct tty *tp; 569 { 570 struct dhu_softc *sc; 571 int line; 572 int s; 573 574 s = spltty(); 575 576 if (tp->t_state & TS_BUSY) { 577 578 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 579 line = DHU_LINE(minor(tp->t_dev)); 580 581 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 582 583 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 584 585 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 586 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 587 DHU_READ_WORD(DHU_UBA_LNCTRL) | 588 DHU_LNCTRL_DMA_ABORT); 589 } 590 591 if (!(tp->t_state & TS_TTSTOP)) 592 tp->t_state |= TS_FLUSH; 593 } 594 (void) splx(s); 595 } 596 597 static void 598 dhustart(tp) 599 struct tty *tp; 600 { 601 struct dhu_softc *sc; 602 int line, cc; 603 int addr; 604 int s; 605 606 s = spltty(); 607 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 608 goto out; 609 if (tp->t_outq.c_cc <= tp->t_lowat) { 610 if (tp->t_state & TS_ASLEEP) { 611 tp->t_state &= ~TS_ASLEEP; 612 wakeup((caddr_t)&tp->t_outq); 613 } 614 selwakeup(&tp->t_wsel); 615 } 616 if (tp->t_outq.c_cc == 0) 617 goto out; 618 cc = ndqb(&tp->t_outq, 0); 619 if (cc == 0) 620 goto out; 621 622 tp->t_state |= TS_BUSY; 623 624 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 625 626 line = DHU_LINE(minor(tp->t_dev)); 627 628 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 629 630 sc->sc_dhu[line].dhu_cc = cc; 631 632 if (cc == 1) { 633 634 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 635 636 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 637 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 638 639 } else { 640 641 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 642 643 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 644 (tp->t_outq.c_cf - tp->t_outq.c_cs); 645 646 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 647 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 648 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 649 DHU_TBUFAD2_TX_ENABLE); 650 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 651 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 652 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 653 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 654 } 655 out: 656 (void) splx(s); 657 return; 658 } 659 660 static int 661 dhuparam(tp, t) 662 struct tty *tp; 663 struct termios *t; 664 { 665 struct dhu_softc *sc; 666 int cflag = t->c_cflag; 667 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 668 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 669 unsigned lpr, lnctrl; 670 int unit, line; 671 int s; 672 673 unit = DHU_M2U(minor(tp->t_dev)); 674 line = DHU_LINE(minor(tp->t_dev)); 675 676 sc = dhu_cd.cd_devs[unit]; 677 678 /* check requested parameters */ 679 if (ospeed < 0 || ispeed < 0) 680 return (EINVAL); 681 682 tp->t_ispeed = t->c_ispeed; 683 tp->t_ospeed = t->c_ospeed; 684 tp->t_cflag = cflag; 685 686 if (ospeed == 0) { 687 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 688 return (0); 689 } 690 691 s = spltty(); 692 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 693 694 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 695 696 switch (cflag & CSIZE) { 697 698 case CS5: 699 lpr |= DHU_LPR_5_BIT_CHAR; 700 break; 701 702 case CS6: 703 lpr |= DHU_LPR_6_BIT_CHAR; 704 break; 705 706 case CS7: 707 lpr |= DHU_LPR_7_BIT_CHAR; 708 break; 709 710 default: 711 lpr |= DHU_LPR_8_BIT_CHAR; 712 break; 713 } 714 715 if (cflag & PARENB) 716 lpr |= DHU_LPR_PARENB; 717 if (!(cflag & PARODD)) 718 lpr |= DHU_LPR_EPAR; 719 if (cflag & CSTOPB) 720 lpr |= DHU_LPR_2_STOP; 721 722 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 723 724 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 725 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 726 727 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 728 729 /* Setting LINK.TYPE enables modem signal change interrupts. */ 730 731 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 732 733 /* Enable the auto XON/XOFF feature on the controller */ 734 735 if (t->c_iflag & IXON) 736 lnctrl |= DHU_LNCTRL_OAUTO; 737 else 738 lnctrl &= ~DHU_LNCTRL_OAUTO; 739 740 if (t->c_iflag & IXOFF) 741 lnctrl |= DHU_LNCTRL_IAUTO; 742 else 743 lnctrl &= ~DHU_LNCTRL_IAUTO; 744 745 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 746 747 (void) splx(s); 748 return (0); 749 } 750 751 static int 752 dhuiflow(tp, flag) 753 struct tty *tp; 754 int flag; 755 { 756 struct dhu_softc *sc; 757 int line = DHU_LINE(minor(tp->t_dev)); 758 759 if (tp->t_cflag & CRTSCTS) { 760 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 761 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 762 return (1); 763 } 764 return (0); 765 } 766 767 static unsigned 768 dhumctl(sc, line, bits, how) 769 struct dhu_softc *sc; 770 int line, bits, how; 771 { 772 unsigned status; 773 unsigned lnctrl; 774 unsigned mbits; 775 int s; 776 777 s = spltty(); 778 779 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 780 781 mbits = 0; 782 783 /* external signals as seen from the port */ 784 785 status = DHU_READ_WORD(DHU_UBA_STAT); 786 787 if (status & DHU_STAT_CTS) 788 mbits |= DML_CTS; 789 790 if (status & DHU_STAT_DCD) 791 mbits |= DML_DCD; 792 793 if (status & DHU_STAT_DSR) 794 mbits |= DML_DSR; 795 796 if (status & DHU_STAT_RI) 797 mbits |= DML_RI; 798 799 /* internal signals/state delivered to port */ 800 801 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 802 803 if (lnctrl & DHU_LNCTRL_RTS) 804 mbits |= DML_RTS; 805 806 if (lnctrl & DHU_LNCTRL_DTR) 807 mbits |= DML_DTR; 808 809 if (lnctrl & DHU_LNCTRL_BREAK) 810 mbits |= DML_BRK; 811 812 switch (how) { 813 814 case DMSET: 815 mbits = bits; 816 break; 817 818 case DMBIS: 819 mbits |= bits; 820 break; 821 822 case DMBIC: 823 mbits &= ~bits; 824 break; 825 826 case DMGET: 827 (void) splx(s); 828 return (mbits); 829 } 830 831 if (mbits & DML_RTS) 832 lnctrl |= DHU_LNCTRL_RTS; 833 else 834 lnctrl &= ~DHU_LNCTRL_RTS; 835 836 if (mbits & DML_DTR) 837 lnctrl |= DHU_LNCTRL_DTR; 838 else 839 lnctrl &= ~DHU_LNCTRL_DTR; 840 841 if (mbits & DML_BRK) 842 lnctrl |= DHU_LNCTRL_BREAK; 843 else 844 lnctrl &= ~DHU_LNCTRL_BREAK; 845 846 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 847 848 (void) splx(s); 849 return (mbits); 850 } 851
Indexes created Tue Sep 23 01:09:51 GMT 2025