dhu.c revision 1.23
1 /* $NetBSD: dhu.c,v 1.23 2001/05/02 10:32:10 scw Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 #include <machine/scb.h> 55 56 #include <dev/qbus/ubavar.h> 57 58 #include <dev/qbus/dhureg.h> 59 60 #include "ioconf.h" 61 62 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 63 64 #define NDHULINE 16 65 66 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 67 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 68 69 struct dhu_softc { 70 struct device sc_dev; /* Device struct used by config */ 71 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 72 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 73 int sc_type; /* controller type, DHU or DHV */ 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 bus_dma_tag_t sc_dmat; 77 struct { 78 struct tty *dhu_tty; /* what we work on */ 79 bus_dmamap_t dhu_dmah; 80 int dhu_state; /* to manage TX output status */ 81 short dhu_cc; /* character count on TX */ 82 short dhu_modem; /* modem bits state */ 83 } sc_dhu[NDHULINE]; 84 }; 85 86 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 87 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 88 89 #define STATE_IDLE 000 /* no current output in progress */ 90 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 91 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 92 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 93 94 /* Flags used to monitor modem bits, make them understood outside driver */ 95 96 #define DML_DTR TIOCM_DTR 97 #define DML_RTS TIOCM_RTS 98 #define DML_CTS TIOCM_CTS 99 #define DML_DCD TIOCM_CD 100 #define DML_RI TIOCM_RI 101 #define DML_DSR TIOCM_DSR 102 #define DML_BRK 0100000 /* no equivalent, we will mask */ 103 104 #define DHU_READ_WORD(reg) \ 105 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 106 #define DHU_WRITE_WORD(reg, val) \ 107 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 108 #define DHU_READ_BYTE(reg) \ 109 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 110 #define DHU_WRITE_BYTE(reg, val) \ 111 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 112 113 114 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 115 /* a baud rate from the same group. So limiting to B is likely */ 116 /* best, although clone boards like the ABLE QHV allow all settings. */ 117 118 static struct speedtab dhuspeedtab[] = { 119 { 0, 0 }, /* Groups */ 120 { 50, DHU_LPR_B50 }, /* A */ 121 { 75, DHU_LPR_B75 }, /* B */ 122 { 110, DHU_LPR_B110 }, /* A and B */ 123 { 134, DHU_LPR_B134 }, /* A and B */ 124 { 150, DHU_LPR_B150 }, /* B */ 125 { 300, DHU_LPR_B300 }, /* A and B */ 126 { 600, DHU_LPR_B600 }, /* A and B */ 127 { 1200, DHU_LPR_B1200 }, /* A and B */ 128 { 1800, DHU_LPR_B1800 }, /* B */ 129 { 2000, DHU_LPR_B2000 }, /* B */ 130 { 2400, DHU_LPR_B2400 }, /* A and B */ 131 { 4800, DHU_LPR_B4800 }, /* A and B */ 132 { 7200, DHU_LPR_B7200 }, /* A */ 133 { 9600, DHU_LPR_B9600 }, /* A and B */ 134 { 19200, DHU_LPR_B19200 }, /* B */ 135 { 38400, DHU_LPR_B38400 }, /* A */ 136 { -1, -1 } 137 }; 138 139 static int dhu_match __P((struct device *, struct cfdata *, void *)); 140 static void dhu_attach __P((struct device *, struct device *, void *)); 141 static void dhurint __P((void *)); 142 static void dhuxint __P((void *)); 143 static void dhustart __P((struct tty *)); 144 static int dhuparam __P((struct tty *, struct termios *)); 145 static int dhuiflow __P((struct tty *, int)); 146 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 147 int dhuopen __P((dev_t, int, int, struct proc *)); 148 int dhuclose __P((dev_t, int, int, struct proc *)); 149 int dhuread __P((dev_t, struct uio *, int)); 150 int dhuwrite __P((dev_t, struct uio *, int)); 151 int dhuioctl __P((dev_t, u_long, caddr_t, int, struct proc *)); 152 void dhustop __P((struct tty *, int)); 153 struct tty * dhutty __P((dev_t)); 154 155 struct cfattach dhu_ca = { 156 sizeof(struct dhu_softc), dhu_match, dhu_attach 157 }; 158 159 /* Autoconfig handles: setup the controller to interrupt, */ 160 /* then complete the housecleaning for full operation */ 161 162 static int 163 dhu_match(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 struct uba_attach_args *ua = aux; 169 int n; 170 171 /* Reset controller to initialize, enable TX/RX interrupts */ 172 /* to catch floating vector info elsewhere when completed */ 173 174 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 175 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 176 177 /* Now wait up to 3 seconds for self-test to complete. */ 178 179 for (n = 0; n < 300; n++) { 180 DELAY(10000); 181 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 182 DHU_CSR_MASTER_RESET) == 0) 183 break; 184 } 185 186 /* If the RESET did not clear after 3 seconds, */ 187 /* the controller must be broken. */ 188 189 if (n >= 300) 190 return 0; 191 192 /* Check whether diagnostic run has signalled a failure. */ 193 194 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 195 DHU_CSR_DIAG_FAIL) != 0) 196 return 0; 197 198 return 1; 199 } 200 201 static void 202 dhu_attach(parent, self, aux) 203 struct device *parent, *self; 204 void *aux; 205 { 206 struct dhu_softc *sc = (void *)self; 207 struct uba_attach_args *ua = aux; 208 unsigned c; 209 int n, i; 210 211 sc->sc_iot = ua->ua_iot; 212 sc->sc_ioh = ua->ua_ioh; 213 sc->sc_dmat = ua->ua_dmat; 214 /* Process the 8 bytes of diagnostic info put into */ 215 /* the FIFO following the master reset operation. */ 216 217 printf("\n%s:", self->dv_xname); 218 for (n = 0; n < 8; n++) { 219 c = DHU_READ_WORD(DHU_UBA_RBUF); 220 221 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 222 if ((c&0200) == 0000) 223 printf(" rom(%d) version %d", 224 ((c>>1)&01), ((c>>2)&037)); 225 else if (((c>>2)&07) != 0) 226 printf(" diag-error(proc%d)=%x", 227 ((c>>1)&01), ((c>>2)&07)); 228 } 229 } 230 231 c = DHU_READ_WORD(DHU_UBA_STAT); 232 233 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 234 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 235 236 for (i = 0; i < sc->sc_type; i++) { 237 struct tty *tp; 238 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 239 sc->sc_dhu[i].dhu_state = STATE_IDLE; 240 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 241 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 242 &sc->sc_dhu[i].dhu_dmah); 243 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 244 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 245 246 } 247 248 /* Now establish RX & TX interrupt handlers */ 249 250 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 251 dhurint, sc, &sc->sc_rintrcnt); 252 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 253 dhuxint, sc, &sc->sc_tintrcnt); 254 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 255 sc->sc_dev.dv_xname, "rintr"); 256 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 257 sc->sc_dev.dv_xname, "tintr"); 258 } 259 260 /* Receiver Interrupt */ 261 262 static void 263 dhurint(arg) 264 void *arg; 265 { 266 struct dhu_softc *sc = arg; 267 struct tty *tp; 268 int cc, line; 269 unsigned c, delta; 270 int overrun = 0; 271 272 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 273 274 /* Ignore diagnostic FIFO entries. */ 275 276 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 277 continue; 278 279 cc = c & 0xFF; 280 line = DHU_LINE(c>>8); 281 tp = sc->sc_dhu[line].dhu_tty; 282 283 /* LINK.TYPE is set so we get modem control FIFO entries */ 284 285 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 286 c = (c << 8); 287 /* Do MDMBUF flow control, wakeup sleeping opens */ 288 if (c & DHU_STAT_DCD) { 289 if (!(tp->t_state & TS_CARR_ON)) 290 (void)(*tp->t_linesw->l_modem)(tp, 1); 291 } 292 else if ((tp->t_state & TS_CARR_ON) && 293 (*tp->t_linesw->l_modem)(tp, 0) == 0) 294 (void) dhumctl(sc, line, 0, DMSET); 295 296 /* Do CRTSCTS flow control */ 297 delta = c ^ sc->sc_dhu[line].dhu_modem; 298 sc->sc_dhu[line].dhu_modem = c; 299 if ((delta & DHU_STAT_CTS) && 300 (tp->t_state & TS_ISOPEN) && 301 (tp->t_cflag & CRTSCTS)) { 302 if (c & DHU_STAT_CTS) { 303 tp->t_state &= ~TS_TTSTOP; 304 ttstart(tp); 305 } else { 306 tp->t_state |= TS_TTSTOP; 307 dhustop(tp, 0); 308 } 309 } 310 continue; 311 } 312 313 if (!(tp->t_state & TS_ISOPEN)) { 314 wakeup((caddr_t)&tp->t_rawq); 315 continue; 316 } 317 318 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 319 log(LOG_WARNING, "%s: silo overflow, line %d\n", 320 sc->sc_dev.dv_xname, line); 321 overrun = 1; 322 } 323 /* A BREAK key will appear as a NULL with a framing error */ 324 if (c & DHU_RBUF_FRAMING_ERR) 325 cc |= TTY_FE; 326 if (c & DHU_RBUF_PARITY_ERR) 327 cc |= TTY_PE; 328 329 (*tp->t_linesw->l_rint)(cc, tp); 330 } 331 } 332 333 /* Transmitter Interrupt */ 334 335 static void 336 dhuxint(arg) 337 void *arg; 338 { 339 struct dhu_softc *sc = arg; 340 struct tty *tp; 341 int line; 342 343 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 344 345 tp = sc->sc_dhu[line].dhu_tty; 346 347 tp->t_state &= ~TS_BUSY; 348 if (tp->t_state & TS_FLUSH) 349 tp->t_state &= ~TS_FLUSH; 350 else { 351 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 352 sc->sc_dhu[line].dhu_cc -= 353 DHU_READ_WORD(DHU_UBA_TBUFCNT); 354 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 355 sc->sc_dhu[line].dhu_cc = 0; 356 } 357 358 sc->sc_dhu[line].dhu_state = STATE_IDLE; 359 360 (*tp->t_linesw->l_start)(tp); 361 } 362 363 int 364 dhuopen(dev, flag, mode, p) 365 dev_t dev; 366 int flag, mode; 367 struct proc *p; 368 { 369 struct tty *tp; 370 int unit, line; 371 struct dhu_softc *sc; 372 int s, error = 0; 373 374 unit = DHU_M2U(minor(dev)); 375 line = DHU_LINE(minor(dev)); 376 377 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 378 return (ENXIO); 379 380 sc = dhu_cd.cd_devs[unit]; 381 382 if (line >= sc->sc_type) 383 return ENXIO; 384 385 s = spltty(); 386 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 387 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 388 (void) splx(s); 389 390 tp = sc->sc_dhu[line].dhu_tty; 391 392 tp->t_oproc = dhustart; 393 tp->t_param = dhuparam; 394 tp->t_hwiflow = dhuiflow; 395 tp->t_dev = dev; 396 if ((tp->t_state & TS_ISOPEN) == 0) { 397 ttychars(tp); 398 if (tp->t_ispeed == 0) { 399 tp->t_iflag = TTYDEF_IFLAG; 400 tp->t_oflag = TTYDEF_OFLAG; 401 tp->t_cflag = TTYDEF_CFLAG; 402 tp->t_lflag = TTYDEF_LFLAG; 403 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 404 } 405 (void) dhuparam(tp, &tp->t_termios); 406 ttsetwater(tp); 407 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 408 return (EBUSY); 409 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 410 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 411 tp->t_state |= TS_CARR_ON; 412 s = spltty(); 413 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 414 !(tp->t_state & TS_CARR_ON)) { 415 tp->t_wopen++; 416 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 417 TTIPRI | PCATCH, ttopen, 0); 418 tp->t_wopen--; 419 if (error) 420 break; 421 } 422 (void) splx(s); 423 if (error) 424 return (error); 425 return ((*tp->t_linesw->l_open)(dev, tp)); 426 } 427 428 /*ARGSUSED*/ 429 int 430 dhuclose(dev, flag, mode, p) 431 dev_t dev; 432 int flag, mode; 433 struct proc *p; 434 { 435 struct tty *tp; 436 int unit, line; 437 struct dhu_softc *sc; 438 439 unit = DHU_M2U(minor(dev)); 440 line = DHU_LINE(minor(dev)); 441 442 sc = dhu_cd.cd_devs[unit]; 443 444 tp = sc->sc_dhu[line].dhu_tty; 445 446 (*tp->t_linesw->l_close)(tp, flag); 447 448 /* Make sure a BREAK state is not left enabled. */ 449 450 (void) dhumctl(sc, line, DML_BRK, DMBIC); 451 452 /* Do a hangup if so required. */ 453 454 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 455 !(tp->t_state & TS_ISOPEN)) 456 (void) dhumctl(sc, line, 0, DMSET); 457 458 return (ttyclose(tp)); 459 } 460 461 int 462 dhuread(dev, uio, flag) 463 dev_t dev; 464 struct uio *uio; 465 { 466 struct dhu_softc *sc; 467 struct tty *tp; 468 469 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 470 471 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 472 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 473 } 474 475 int 476 dhuwrite(dev, uio, flag) 477 dev_t dev; 478 struct uio *uio; 479 { 480 struct dhu_softc *sc; 481 struct tty *tp; 482 483 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 484 485 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 486 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 487 } 488 489 int 490 dhupoll(dev, events, p) 491 dev_t dev; 492 int events; 493 struct proc *p; 494 { 495 struct dhu_softc *sc; 496 struct tty *tp; 497 498 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 499 500 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 501 return ((*tp->t_linesw->l_poll)(tp, events, p)); 502 } 503 504 /*ARGSUSED*/ 505 int 506 dhuioctl(dev, cmd, data, flag, p) 507 dev_t dev; 508 u_long cmd; 509 caddr_t data; 510 int flag; 511 struct proc *p; 512 { 513 struct dhu_softc *sc; 514 struct tty *tp; 515 int unit, line; 516 int error; 517 518 unit = DHU_M2U(minor(dev)); 519 line = DHU_LINE(minor(dev)); 520 sc = dhu_cd.cd_devs[unit]; 521 tp = sc->sc_dhu[line].dhu_tty; 522 523 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 524 if (error >= 0) 525 return (error); 526 error = ttioctl(tp, cmd, data, flag, p); 527 if (error >= 0) 528 return (error); 529 530 switch (cmd) { 531 532 case TIOCSBRK: 533 (void) dhumctl(sc, line, DML_BRK, DMBIS); 534 break; 535 536 case TIOCCBRK: 537 (void) dhumctl(sc, line, DML_BRK, DMBIC); 538 break; 539 540 case TIOCSDTR: 541 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 542 break; 543 544 case TIOCCDTR: 545 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 546 break; 547 548 case TIOCMSET: 549 (void) dhumctl(sc, line, *(int *)data, DMSET); 550 break; 551 552 case TIOCMBIS: 553 (void) dhumctl(sc, line, *(int *)data, DMBIS); 554 break; 555 556 case TIOCMBIC: 557 (void) dhumctl(sc, line, *(int *)data, DMBIC); 558 break; 559 560 case TIOCMGET: 561 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 562 break; 563 564 default: 565 return (ENOTTY); 566 } 567 return (0); 568 } 569 570 struct tty * 571 dhutty(dev) 572 dev_t dev; 573 { 574 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 575 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 576 return (tp); 577 } 578 579 /*ARGSUSED*/ 580 void 581 dhustop(tp, flag) 582 struct tty *tp; 583 { 584 struct dhu_softc *sc; 585 int line; 586 int s; 587 588 s = spltty(); 589 590 if (tp->t_state & TS_BUSY) { 591 592 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 593 line = DHU_LINE(minor(tp->t_dev)); 594 595 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 596 597 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 598 599 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 600 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 601 DHU_READ_WORD(DHU_UBA_LNCTRL) | 602 DHU_LNCTRL_DMA_ABORT); 603 } 604 605 if (!(tp->t_state & TS_TTSTOP)) 606 tp->t_state |= TS_FLUSH; 607 } 608 (void) splx(s); 609 } 610 611 static void 612 dhustart(tp) 613 struct tty *tp; 614 { 615 struct dhu_softc *sc; 616 int line, cc; 617 int addr; 618 int s; 619 620 s = spltty(); 621 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 622 goto out; 623 if (tp->t_outq.c_cc <= tp->t_lowat) { 624 if (tp->t_state & TS_ASLEEP) { 625 tp->t_state &= ~TS_ASLEEP; 626 wakeup((caddr_t)&tp->t_outq); 627 } 628 selwakeup(&tp->t_wsel); 629 } 630 if (tp->t_outq.c_cc == 0) 631 goto out; 632 cc = ndqb(&tp->t_outq, 0); 633 if (cc == 0) 634 goto out; 635 636 tp->t_state |= TS_BUSY; 637 638 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 639 640 line = DHU_LINE(minor(tp->t_dev)); 641 642 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 643 644 sc->sc_dhu[line].dhu_cc = cc; 645 646 if (cc == 1) { 647 648 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 649 650 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 651 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 652 653 } else { 654 655 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 656 657 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 658 (tp->t_outq.c_cf - tp->t_outq.c_cs); 659 660 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 661 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 662 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 663 DHU_TBUFAD2_TX_ENABLE); 664 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 665 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 666 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 667 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 668 } 669 out: 670 (void) splx(s); 671 return; 672 } 673 674 static int 675 dhuparam(tp, t) 676 struct tty *tp; 677 struct termios *t; 678 { 679 struct dhu_softc *sc; 680 int cflag = t->c_cflag; 681 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 682 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 683 unsigned lpr, lnctrl; 684 int unit, line; 685 int s; 686 687 unit = DHU_M2U(minor(tp->t_dev)); 688 line = DHU_LINE(minor(tp->t_dev)); 689 690 sc = dhu_cd.cd_devs[unit]; 691 692 /* check requested parameters */ 693 if (ospeed < 0 || ispeed < 0) 694 return (EINVAL); 695 696 tp->t_ispeed = t->c_ispeed; 697 tp->t_ospeed = t->c_ospeed; 698 tp->t_cflag = cflag; 699 700 if (ospeed == 0) { 701 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 702 return (0); 703 } 704 705 s = spltty(); 706 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 707 708 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 709 710 switch (cflag & CSIZE) { 711 712 case CS5: 713 lpr |= DHU_LPR_5_BIT_CHAR; 714 break; 715 716 case CS6: 717 lpr |= DHU_LPR_6_BIT_CHAR; 718 break; 719 720 case CS7: 721 lpr |= DHU_LPR_7_BIT_CHAR; 722 break; 723 724 default: 725 lpr |= DHU_LPR_8_BIT_CHAR; 726 break; 727 } 728 729 if (cflag & PARENB) 730 lpr |= DHU_LPR_PARENB; 731 if (!(cflag & PARODD)) 732 lpr |= DHU_LPR_EPAR; 733 if (cflag & CSTOPB) 734 lpr |= DHU_LPR_2_STOP; 735 736 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 737 738 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 739 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 740 741 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 742 743 /* Setting LINK.TYPE enables modem signal change interrupts. */ 744 745 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 746 747 /* Enable the auto XON/XOFF feature on the controller */ 748 749 if (t->c_iflag & IXON) 750 lnctrl |= DHU_LNCTRL_OAUTO; 751 else 752 lnctrl &= ~DHU_LNCTRL_OAUTO; 753 754 if (t->c_iflag & IXOFF) 755 lnctrl |= DHU_LNCTRL_IAUTO; 756 else 757 lnctrl &= ~DHU_LNCTRL_IAUTO; 758 759 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 760 761 (void) splx(s); 762 return (0); 763 } 764 765 static int 766 dhuiflow(tp, flag) 767 struct tty *tp; 768 int flag; 769 { 770 struct dhu_softc *sc; 771 int line = DHU_LINE(minor(tp->t_dev)); 772 773 if (tp->t_cflag & CRTSCTS) { 774 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 775 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 776 return (1); 777 } 778 return (0); 779 } 780 781 static unsigned 782 dhumctl(sc, line, bits, how) 783 struct dhu_softc *sc; 784 int line, bits, how; 785 { 786 unsigned status; 787 unsigned lnctrl; 788 unsigned mbits; 789 int s; 790 791 s = spltty(); 792 793 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 794 795 mbits = 0; 796 797 /* external signals as seen from the port */ 798 799 status = DHU_READ_WORD(DHU_UBA_STAT); 800 801 if (status & DHU_STAT_CTS) 802 mbits |= DML_CTS; 803 804 if (status & DHU_STAT_DCD) 805 mbits |= DML_DCD; 806 807 if (status & DHU_STAT_DSR) 808 mbits |= DML_DSR; 809 810 if (status & DHU_STAT_RI) 811 mbits |= DML_RI; 812 813 /* internal signals/state delivered to port */ 814 815 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 816 817 if (lnctrl & DHU_LNCTRL_RTS) 818 mbits |= DML_RTS; 819 820 if (lnctrl & DHU_LNCTRL_DTR) 821 mbits |= DML_DTR; 822 823 if (lnctrl & DHU_LNCTRL_BREAK) 824 mbits |= DML_BRK; 825 826 switch (how) { 827 828 case DMSET: 829 mbits = bits; 830 break; 831 832 case DMBIS: 833 mbits |= bits; 834 break; 835 836 case DMBIC: 837 mbits &= ~bits; 838 break; 839 840 case DMGET: 841 (void) splx(s); 842 return (mbits); 843 } 844 845 if (mbits & DML_RTS) 846 lnctrl |= DHU_LNCTRL_RTS; 847 else 848 lnctrl &= ~DHU_LNCTRL_RTS; 849 850 if (mbits & DML_DTR) 851 lnctrl |= DHU_LNCTRL_DTR; 852 else 853 lnctrl &= ~DHU_LNCTRL_DTR; 854 855 if (mbits & DML_BRK) 856 lnctrl |= DHU_LNCTRL_BREAK; 857 else 858 lnctrl &= ~DHU_LNCTRL_BREAK; 859 860 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 861 862 (void) splx(s); 863 return (mbits); 864 } 865
Indexes created Tue Sep 23 22:09:46 GMT 2025