dhu.c revision 1.24
1 /* $NetBSD: dhu.c,v 1.24 2001/05/26 21:24:38 ragge Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 #include <machine/scb.h> 55 56 #include <dev/qbus/ubavar.h> 57 58 #include <dev/qbus/dhureg.h> 59 60 #include "ioconf.h" 61 62 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 63 64 #define NDHULINE 16 65 66 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 67 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 68 69 struct dhu_softc { 70 struct device sc_dev; /* Device struct used by config */ 71 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 72 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 73 int sc_type; /* controller type, DHU or DHV */ 74 bus_space_tag_t sc_iot; 75 bus_space_handle_t sc_ioh; 76 bus_dma_tag_t sc_dmat; 77 struct { 78 struct tty *dhu_tty; /* what we work on */ 79 bus_dmamap_t dhu_dmah; 80 int dhu_state; /* to manage TX output status */ 81 short dhu_cc; /* character count on TX */ 82 short dhu_modem; /* modem bits state */ 83 } sc_dhu[NDHULINE]; 84 }; 85 86 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 87 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 88 89 #define STATE_IDLE 000 /* no current output in progress */ 90 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 91 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 92 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 93 94 /* Flags used to monitor modem bits, make them understood outside driver */ 95 96 #define DML_DTR TIOCM_DTR 97 #define DML_RTS TIOCM_RTS 98 #define DML_CTS TIOCM_CTS 99 #define DML_DCD TIOCM_CD 100 #define DML_RI TIOCM_RI 101 #define DML_DSR TIOCM_DSR 102 #define DML_BRK 0100000 /* no equivalent, we will mask */ 103 104 #define DHU_READ_WORD(reg) \ 105 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 106 #define DHU_WRITE_WORD(reg, val) \ 107 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 108 #define DHU_READ_BYTE(reg) \ 109 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 110 #define DHU_WRITE_BYTE(reg, val) \ 111 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 112 113 114 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 115 /* a baud rate from the same group. So limiting to B is likely */ 116 /* best, although clone boards like the ABLE QHV allow all settings. */ 117 118 static struct speedtab dhuspeedtab[] = { 119 { 0, 0 }, /* Groups */ 120 { 50, DHU_LPR_B50 }, /* A */ 121 { 75, DHU_LPR_B75 }, /* B */ 122 { 110, DHU_LPR_B110 }, /* A and B */ 123 { 134, DHU_LPR_B134 }, /* A and B */ 124 { 150, DHU_LPR_B150 }, /* B */ 125 { 300, DHU_LPR_B300 }, /* A and B */ 126 { 600, DHU_LPR_B600 }, /* A and B */ 127 { 1200, DHU_LPR_B1200 }, /* A and B */ 128 { 1800, DHU_LPR_B1800 }, /* B */ 129 { 2000, DHU_LPR_B2000 }, /* B */ 130 { 2400, DHU_LPR_B2400 }, /* A and B */ 131 { 4800, DHU_LPR_B4800 }, /* A and B */ 132 { 7200, DHU_LPR_B7200 }, /* A */ 133 { 9600, DHU_LPR_B9600 }, /* A and B */ 134 { 19200, DHU_LPR_B19200 }, /* B */ 135 { 38400, DHU_LPR_B38400 }, /* A */ 136 { -1, -1 } 137 }; 138 139 static int dhu_match __P((struct device *, struct cfdata *, void *)); 140 static void dhu_attach __P((struct device *, struct device *, void *)); 141 static void dhurint __P((void *)); 142 static void dhuxint __P((void *)); 143 static void dhustart __P((struct tty *)); 144 static int dhuparam __P((struct tty *, struct termios *)); 145 static int dhuiflow __P((struct tty *, int)); 146 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 147 148 cdev_decl(dhu); 149 150 struct cfattach dhu_ca = { 151 sizeof(struct dhu_softc), dhu_match, dhu_attach 152 }; 153 154 /* Autoconfig handles: setup the controller to interrupt, */ 155 /* then complete the housecleaning for full operation */ 156 157 static int 158 dhu_match(parent, cf, aux) 159 struct device *parent; 160 struct cfdata *cf; 161 void *aux; 162 { 163 struct uba_attach_args *ua = aux; 164 int n; 165 166 /* Reset controller to initialize, enable TX/RX interrupts */ 167 /* to catch floating vector info elsewhere when completed */ 168 169 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 170 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 171 172 /* Now wait up to 3 seconds for self-test to complete. */ 173 174 for (n = 0; n < 300; n++) { 175 DELAY(10000); 176 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 177 DHU_CSR_MASTER_RESET) == 0) 178 break; 179 } 180 181 /* If the RESET did not clear after 3 seconds, */ 182 /* the controller must be broken. */ 183 184 if (n >= 300) 185 return 0; 186 187 /* Check whether diagnostic run has signalled a failure. */ 188 189 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 190 DHU_CSR_DIAG_FAIL) != 0) 191 return 0; 192 193 return 1; 194 } 195 196 static void 197 dhu_attach(parent, self, aux) 198 struct device *parent, *self; 199 void *aux; 200 { 201 struct dhu_softc *sc = (void *)self; 202 struct uba_attach_args *ua = aux; 203 unsigned c; 204 int n, i; 205 206 sc->sc_iot = ua->ua_iot; 207 sc->sc_ioh = ua->ua_ioh; 208 sc->sc_dmat = ua->ua_dmat; 209 /* Process the 8 bytes of diagnostic info put into */ 210 /* the FIFO following the master reset operation. */ 211 212 printf("\n%s:", self->dv_xname); 213 for (n = 0; n < 8; n++) { 214 c = DHU_READ_WORD(DHU_UBA_RBUF); 215 216 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 217 if ((c&0200) == 0000) 218 printf(" rom(%d) version %d", 219 ((c>>1)&01), ((c>>2)&037)); 220 else if (((c>>2)&07) != 0) 221 printf(" diag-error(proc%d)=%x", 222 ((c>>1)&01), ((c>>2)&07)); 223 } 224 } 225 226 c = DHU_READ_WORD(DHU_UBA_STAT); 227 228 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 229 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 230 231 for (i = 0; i < sc->sc_type; i++) { 232 struct tty *tp; 233 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 234 sc->sc_dhu[i].dhu_state = STATE_IDLE; 235 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 236 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 237 &sc->sc_dhu[i].dhu_dmah); 238 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 239 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 240 241 } 242 243 /* Now establish RX & TX interrupt handlers */ 244 245 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 246 dhurint, sc, &sc->sc_rintrcnt); 247 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 248 dhuxint, sc, &sc->sc_tintrcnt); 249 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 250 sc->sc_dev.dv_xname, "rintr"); 251 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 252 sc->sc_dev.dv_xname, "tintr"); 253 } 254 255 /* Receiver Interrupt */ 256 257 static void 258 dhurint(arg) 259 void *arg; 260 { 261 struct dhu_softc *sc = arg; 262 struct tty *tp; 263 int cc, line; 264 unsigned c, delta; 265 int overrun = 0; 266 267 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 268 269 /* Ignore diagnostic FIFO entries. */ 270 271 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 272 continue; 273 274 cc = c & 0xFF; 275 line = DHU_LINE(c>>8); 276 tp = sc->sc_dhu[line].dhu_tty; 277 278 /* LINK.TYPE is set so we get modem control FIFO entries */ 279 280 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 281 c = (c << 8); 282 /* Do MDMBUF flow control, wakeup sleeping opens */ 283 if (c & DHU_STAT_DCD) { 284 if (!(tp->t_state & TS_CARR_ON)) 285 (void)(*tp->t_linesw->l_modem)(tp, 1); 286 } 287 else if ((tp->t_state & TS_CARR_ON) && 288 (*tp->t_linesw->l_modem)(tp, 0) == 0) 289 (void) dhumctl(sc, line, 0, DMSET); 290 291 /* Do CRTSCTS flow control */ 292 delta = c ^ sc->sc_dhu[line].dhu_modem; 293 sc->sc_dhu[line].dhu_modem = c; 294 if ((delta & DHU_STAT_CTS) && 295 (tp->t_state & TS_ISOPEN) && 296 (tp->t_cflag & CRTSCTS)) { 297 if (c & DHU_STAT_CTS) { 298 tp->t_state &= ~TS_TTSTOP; 299 ttstart(tp); 300 } else { 301 tp->t_state |= TS_TTSTOP; 302 dhustop(tp, 0); 303 } 304 } 305 continue; 306 } 307 308 if (!(tp->t_state & TS_ISOPEN)) { 309 wakeup((caddr_t)&tp->t_rawq); 310 continue; 311 } 312 313 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 314 log(LOG_WARNING, "%s: silo overflow, line %d\n", 315 sc->sc_dev.dv_xname, line); 316 overrun = 1; 317 } 318 /* A BREAK key will appear as a NULL with a framing error */ 319 if (c & DHU_RBUF_FRAMING_ERR) 320 cc |= TTY_FE; 321 if (c & DHU_RBUF_PARITY_ERR) 322 cc |= TTY_PE; 323 324 (*tp->t_linesw->l_rint)(cc, tp); 325 } 326 } 327 328 /* Transmitter Interrupt */ 329 330 static void 331 dhuxint(arg) 332 void *arg; 333 { 334 struct dhu_softc *sc = arg; 335 struct tty *tp; 336 int line; 337 338 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 339 340 tp = sc->sc_dhu[line].dhu_tty; 341 342 tp->t_state &= ~TS_BUSY; 343 if (tp->t_state & TS_FLUSH) 344 tp->t_state &= ~TS_FLUSH; 345 else { 346 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 347 sc->sc_dhu[line].dhu_cc -= 348 DHU_READ_WORD(DHU_UBA_TBUFCNT); 349 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 350 sc->sc_dhu[line].dhu_cc = 0; 351 } 352 353 sc->sc_dhu[line].dhu_state = STATE_IDLE; 354 355 (*tp->t_linesw->l_start)(tp); 356 } 357 358 int 359 dhuopen(dev, flag, mode, p) 360 dev_t dev; 361 int flag, mode; 362 struct proc *p; 363 { 364 struct tty *tp; 365 int unit, line; 366 struct dhu_softc *sc; 367 int s, error = 0; 368 369 unit = DHU_M2U(minor(dev)); 370 line = DHU_LINE(minor(dev)); 371 372 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 373 return (ENXIO); 374 375 sc = dhu_cd.cd_devs[unit]; 376 377 if (line >= sc->sc_type) 378 return ENXIO; 379 380 s = spltty(); 381 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 382 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 383 (void) splx(s); 384 385 tp = sc->sc_dhu[line].dhu_tty; 386 387 tp->t_oproc = dhustart; 388 tp->t_param = dhuparam; 389 tp->t_hwiflow = dhuiflow; 390 tp->t_dev = dev; 391 if ((tp->t_state & TS_ISOPEN) == 0) { 392 ttychars(tp); 393 if (tp->t_ispeed == 0) { 394 tp->t_iflag = TTYDEF_IFLAG; 395 tp->t_oflag = TTYDEF_OFLAG; 396 tp->t_cflag = TTYDEF_CFLAG; 397 tp->t_lflag = TTYDEF_LFLAG; 398 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 399 } 400 (void) dhuparam(tp, &tp->t_termios); 401 ttsetwater(tp); 402 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 403 return (EBUSY); 404 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 405 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 406 tp->t_state |= TS_CARR_ON; 407 s = spltty(); 408 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 409 !(tp->t_state & TS_CARR_ON)) { 410 tp->t_wopen++; 411 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 412 TTIPRI | PCATCH, ttopen, 0); 413 tp->t_wopen--; 414 if (error) 415 break; 416 } 417 (void) splx(s); 418 if (error) 419 return (error); 420 return ((*tp->t_linesw->l_open)(dev, tp)); 421 } 422 423 /*ARGSUSED*/ 424 int 425 dhuclose(dev, flag, mode, p) 426 dev_t dev; 427 int flag, mode; 428 struct proc *p; 429 { 430 struct tty *tp; 431 int unit, line; 432 struct dhu_softc *sc; 433 434 unit = DHU_M2U(minor(dev)); 435 line = DHU_LINE(minor(dev)); 436 437 sc = dhu_cd.cd_devs[unit]; 438 439 tp = sc->sc_dhu[line].dhu_tty; 440 441 (*tp->t_linesw->l_close)(tp, flag); 442 443 /* Make sure a BREAK state is not left enabled. */ 444 445 (void) dhumctl(sc, line, DML_BRK, DMBIC); 446 447 /* Do a hangup if so required. */ 448 449 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 450 !(tp->t_state & TS_ISOPEN)) 451 (void) dhumctl(sc, line, 0, DMSET); 452 453 return (ttyclose(tp)); 454 } 455 456 int 457 dhuread(dev, uio, flag) 458 dev_t dev; 459 struct uio *uio; 460 { 461 struct dhu_softc *sc; 462 struct tty *tp; 463 464 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 465 466 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 467 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 468 } 469 470 int 471 dhuwrite(dev, uio, flag) 472 dev_t dev; 473 struct uio *uio; 474 { 475 struct dhu_softc *sc; 476 struct tty *tp; 477 478 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 479 480 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 481 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 482 } 483 484 int 485 dhupoll(dev, events, p) 486 dev_t dev; 487 int events; 488 struct proc *p; 489 { 490 struct dhu_softc *sc; 491 struct tty *tp; 492 493 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 494 495 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 496 return ((*tp->t_linesw->l_poll)(tp, events, p)); 497 } 498 499 /*ARGSUSED*/ 500 int 501 dhuioctl(dev, cmd, data, flag, p) 502 dev_t dev; 503 u_long cmd; 504 caddr_t data; 505 int flag; 506 struct proc *p; 507 { 508 struct dhu_softc *sc; 509 struct tty *tp; 510 int unit, line; 511 int error; 512 513 unit = DHU_M2U(minor(dev)); 514 line = DHU_LINE(minor(dev)); 515 sc = dhu_cd.cd_devs[unit]; 516 tp = sc->sc_dhu[line].dhu_tty; 517 518 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 519 if (error >= 0) 520 return (error); 521 error = ttioctl(tp, cmd, data, flag, p); 522 if (error >= 0) 523 return (error); 524 525 switch (cmd) { 526 527 case TIOCSBRK: 528 (void) dhumctl(sc, line, DML_BRK, DMBIS); 529 break; 530 531 case TIOCCBRK: 532 (void) dhumctl(sc, line, DML_BRK, DMBIC); 533 break; 534 535 case TIOCSDTR: 536 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 537 break; 538 539 case TIOCCDTR: 540 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 541 break; 542 543 case TIOCMSET: 544 (void) dhumctl(sc, line, *(int *)data, DMSET); 545 break; 546 547 case TIOCMBIS: 548 (void) dhumctl(sc, line, *(int *)data, DMBIS); 549 break; 550 551 case TIOCMBIC: 552 (void) dhumctl(sc, line, *(int *)data, DMBIC); 553 break; 554 555 case TIOCMGET: 556 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 557 break; 558 559 default: 560 return (ENOTTY); 561 } 562 return (0); 563 } 564 565 struct tty * 566 dhutty(dev) 567 dev_t dev; 568 { 569 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 570 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 571 return (tp); 572 } 573 574 /*ARGSUSED*/ 575 void 576 dhustop(tp, flag) 577 struct tty *tp; 578 { 579 struct dhu_softc *sc; 580 int line; 581 int s; 582 583 s = spltty(); 584 585 if (tp->t_state & TS_BUSY) { 586 587 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 588 line = DHU_LINE(minor(tp->t_dev)); 589 590 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 591 592 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 593 594 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 595 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 596 DHU_READ_WORD(DHU_UBA_LNCTRL) | 597 DHU_LNCTRL_DMA_ABORT); 598 } 599 600 if (!(tp->t_state & TS_TTSTOP)) 601 tp->t_state |= TS_FLUSH; 602 } 603 (void) splx(s); 604 } 605 606 static void 607 dhustart(tp) 608 struct tty *tp; 609 { 610 struct dhu_softc *sc; 611 int line, cc; 612 int addr; 613 int s; 614 615 s = spltty(); 616 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 617 goto out; 618 if (tp->t_outq.c_cc <= tp->t_lowat) { 619 if (tp->t_state & TS_ASLEEP) { 620 tp->t_state &= ~TS_ASLEEP; 621 wakeup((caddr_t)&tp->t_outq); 622 } 623 selwakeup(&tp->t_wsel); 624 } 625 if (tp->t_outq.c_cc == 0) 626 goto out; 627 cc = ndqb(&tp->t_outq, 0); 628 if (cc == 0) 629 goto out; 630 631 tp->t_state |= TS_BUSY; 632 633 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 634 635 line = DHU_LINE(minor(tp->t_dev)); 636 637 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 638 639 sc->sc_dhu[line].dhu_cc = cc; 640 641 if (cc == 1) { 642 643 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 644 645 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 646 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 647 648 } else { 649 650 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 651 652 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 653 (tp->t_outq.c_cf - tp->t_outq.c_cs); 654 655 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 656 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 657 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 658 DHU_TBUFAD2_TX_ENABLE); 659 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 660 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 661 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 662 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 663 } 664 out: 665 (void) splx(s); 666 return; 667 } 668 669 static int 670 dhuparam(tp, t) 671 struct tty *tp; 672 struct termios *t; 673 { 674 struct dhu_softc *sc; 675 int cflag = t->c_cflag; 676 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 677 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 678 unsigned lpr, lnctrl; 679 int unit, line; 680 int s; 681 682 unit = DHU_M2U(minor(tp->t_dev)); 683 line = DHU_LINE(minor(tp->t_dev)); 684 685 sc = dhu_cd.cd_devs[unit]; 686 687 /* check requested parameters */ 688 if (ospeed < 0 || ispeed < 0) 689 return (EINVAL); 690 691 tp->t_ispeed = t->c_ispeed; 692 tp->t_ospeed = t->c_ospeed; 693 tp->t_cflag = cflag; 694 695 if (ospeed == 0) { 696 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 697 return (0); 698 } 699 700 s = spltty(); 701 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 702 703 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 704 705 switch (cflag & CSIZE) { 706 707 case CS5: 708 lpr |= DHU_LPR_5_BIT_CHAR; 709 break; 710 711 case CS6: 712 lpr |= DHU_LPR_6_BIT_CHAR; 713 break; 714 715 case CS7: 716 lpr |= DHU_LPR_7_BIT_CHAR; 717 break; 718 719 default: 720 lpr |= DHU_LPR_8_BIT_CHAR; 721 break; 722 } 723 724 if (cflag & PARENB) 725 lpr |= DHU_LPR_PARENB; 726 if (!(cflag & PARODD)) 727 lpr |= DHU_LPR_EPAR; 728 if (cflag & CSTOPB) 729 lpr |= DHU_LPR_2_STOP; 730 731 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 732 733 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 734 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 735 736 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 737 738 /* Setting LINK.TYPE enables modem signal change interrupts. */ 739 740 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 741 742 /* Enable the auto XON/XOFF feature on the controller */ 743 744 if (t->c_iflag & IXON) 745 lnctrl |= DHU_LNCTRL_OAUTO; 746 else 747 lnctrl &= ~DHU_LNCTRL_OAUTO; 748 749 if (t->c_iflag & IXOFF) 750 lnctrl |= DHU_LNCTRL_IAUTO; 751 else 752 lnctrl &= ~DHU_LNCTRL_IAUTO; 753 754 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 755 756 (void) splx(s); 757 return (0); 758 } 759 760 static int 761 dhuiflow(tp, flag) 762 struct tty *tp; 763 int flag; 764 { 765 struct dhu_softc *sc; 766 int line = DHU_LINE(minor(tp->t_dev)); 767 768 if (tp->t_cflag & CRTSCTS) { 769 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 770 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 771 return (1); 772 } 773 return (0); 774 } 775 776 static unsigned 777 dhumctl(sc, line, bits, how) 778 struct dhu_softc *sc; 779 int line, bits, how; 780 { 781 unsigned status; 782 unsigned lnctrl; 783 unsigned mbits; 784 int s; 785 786 s = spltty(); 787 788 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 789 790 mbits = 0; 791 792 /* external signals as seen from the port */ 793 794 status = DHU_READ_WORD(DHU_UBA_STAT); 795 796 if (status & DHU_STAT_CTS) 797 mbits |= DML_CTS; 798 799 if (status & DHU_STAT_DCD) 800 mbits |= DML_DCD; 801 802 if (status & DHU_STAT_DSR) 803 mbits |= DML_DSR; 804 805 if (status & DHU_STAT_RI) 806 mbits |= DML_RI; 807 808 /* internal signals/state delivered to port */ 809 810 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 811 812 if (lnctrl & DHU_LNCTRL_RTS) 813 mbits |= DML_RTS; 814 815 if (lnctrl & DHU_LNCTRL_DTR) 816 mbits |= DML_DTR; 817 818 if (lnctrl & DHU_LNCTRL_BREAK) 819 mbits |= DML_BRK; 820 821 switch (how) { 822 823 case DMSET: 824 mbits = bits; 825 break; 826 827 case DMBIS: 828 mbits |= bits; 829 break; 830 831 case DMBIC: 832 mbits &= ~bits; 833 break; 834 835 case DMGET: 836 (void) splx(s); 837 return (mbits); 838 } 839 840 if (mbits & DML_RTS) 841 lnctrl |= DHU_LNCTRL_RTS; 842 else 843 lnctrl &= ~DHU_LNCTRL_RTS; 844 845 if (mbits & DML_DTR) 846 lnctrl |= DHU_LNCTRL_DTR; 847 else 848 lnctrl &= ~DHU_LNCTRL_DTR; 849 850 if (mbits & DML_BRK) 851 lnctrl |= DHU_LNCTRL_BREAK; 852 else 853 lnctrl &= ~DHU_LNCTRL_BREAK; 854 855 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 856 857 (void) splx(s); 858 return (mbits); 859 } 860
Indexes created Thu Sep 25 08:09:54 GMT 2025