dhu.c revision 1.24.4.2
1 /* $NetBSD: dhu.c,v 1.24.4.2 2001/10/13 17:42:48 fvdl Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/ioctl.h> 42 #include <sys/tty.h> 43 #include <sys/proc.h> 44 #include <sys/map.h> 45 #include <sys/buf.h> 46 #include <sys/conf.h> 47 #include <sys/file.h> 48 #include <sys/uio.h> 49 #include <sys/kernel.h> 50 #include <sys/syslog.h> 51 #include <sys/device.h> 52 #include <sys/vnode.h> 53 54 #include <machine/bus.h> 55 #include <machine/scb.h> 56 57 #include <dev/qbus/ubavar.h> 58 59 #include <dev/qbus/dhureg.h> 60 61 #include "ioconf.h" 62 63 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 64 65 #define NDHULINE 16 66 67 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 68 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 69 70 struct dhu_softc { 71 struct device sc_dev; /* Device struct used by config */ 72 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 73 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 74 int sc_type; /* controller type, DHU or DHV */ 75 bus_space_tag_t sc_iot; 76 bus_space_handle_t sc_ioh; 77 bus_dma_tag_t sc_dmat; 78 struct { 79 struct tty *dhu_tty; /* what we work on */ 80 bus_dmamap_t dhu_dmah; 81 int dhu_state; /* to manage TX output status */ 82 short dhu_cc; /* character count on TX */ 83 short dhu_modem; /* modem bits state */ 84 } sc_dhu[NDHULINE]; 85 }; 86 87 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 88 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 89 90 #define STATE_IDLE 000 /* no current output in progress */ 91 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 92 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 93 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 94 95 /* Flags used to monitor modem bits, make them understood outside driver */ 96 97 #define DML_DTR TIOCM_DTR 98 #define DML_RTS TIOCM_RTS 99 #define DML_CTS TIOCM_CTS 100 #define DML_DCD TIOCM_CD 101 #define DML_RI TIOCM_RI 102 #define DML_DSR TIOCM_DSR 103 #define DML_BRK 0100000 /* no equivalent, we will mask */ 104 105 #define DHU_READ_WORD(reg) \ 106 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 107 #define DHU_WRITE_WORD(reg, val) \ 108 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 109 #define DHU_READ_BYTE(reg) \ 110 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 111 #define DHU_WRITE_BYTE(reg, val) \ 112 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 113 114 115 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 116 /* a baud rate from the same group. So limiting to B is likely */ 117 /* best, although clone boards like the ABLE QHV allow all settings. */ 118 119 static struct speedtab dhuspeedtab[] = { 120 { 0, 0 }, /* Groups */ 121 { 50, DHU_LPR_B50 }, /* A */ 122 { 75, DHU_LPR_B75 }, /* B */ 123 { 110, DHU_LPR_B110 }, /* A and B */ 124 { 134, DHU_LPR_B134 }, /* A and B */ 125 { 150, DHU_LPR_B150 }, /* B */ 126 { 300, DHU_LPR_B300 }, /* A and B */ 127 { 600, DHU_LPR_B600 }, /* A and B */ 128 { 1200, DHU_LPR_B1200 }, /* A and B */ 129 { 1800, DHU_LPR_B1800 }, /* B */ 130 { 2000, DHU_LPR_B2000 }, /* B */ 131 { 2400, DHU_LPR_B2400 }, /* A and B */ 132 { 4800, DHU_LPR_B4800 }, /* A and B */ 133 { 7200, DHU_LPR_B7200 }, /* A */ 134 { 9600, DHU_LPR_B9600 }, /* A and B */ 135 { 19200, DHU_LPR_B19200 }, /* B */ 136 { 38400, DHU_LPR_B38400 }, /* A */ 137 { -1, -1 } 138 }; 139 140 static int dhu_match __P((struct device *, struct cfdata *, void *)); 141 static void dhu_attach __P((struct device *, struct device *, void *)); 142 static void dhurint __P((void *)); 143 static void dhuxint __P((void *)); 144 static void dhustart __P((struct tty *)); 145 static int dhuparam __P((struct tty *, struct termios *)); 146 static int dhuiflow __P((struct tty *, int)); 147 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 148 149 cdev_decl(dhu); 150 151 struct cfattach dhu_ca = { 152 sizeof(struct dhu_softc), dhu_match, dhu_attach 153 }; 154 155 /* Autoconfig handles: setup the controller to interrupt, */ 156 /* then complete the housecleaning for full operation */ 157 158 static int 159 dhu_match(parent, cf, aux) 160 struct device *parent; 161 struct cfdata *cf; 162 void *aux; 163 { 164 struct uba_attach_args *ua = aux; 165 int n; 166 167 /* Reset controller to initialize, enable TX/RX interrupts */ 168 /* to catch floating vector info elsewhere when completed */ 169 170 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 171 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 172 173 /* Now wait up to 3 seconds for self-test to complete. */ 174 175 for (n = 0; n < 300; n++) { 176 DELAY(10000); 177 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 178 DHU_CSR_MASTER_RESET) == 0) 179 break; 180 } 181 182 /* If the RESET did not clear after 3 seconds, */ 183 /* the controller must be broken. */ 184 185 if (n >= 300) 186 return 0; 187 188 /* Check whether diagnostic run has signalled a failure. */ 189 190 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 191 DHU_CSR_DIAG_FAIL) != 0) 192 return 0; 193 194 return 1; 195 } 196 197 static void 198 dhu_attach(parent, self, aux) 199 struct device *parent, *self; 200 void *aux; 201 { 202 struct dhu_softc *sc = (void *)self; 203 struct uba_attach_args *ua = aux; 204 unsigned c; 205 int n, i; 206 207 sc->sc_iot = ua->ua_iot; 208 sc->sc_ioh = ua->ua_ioh; 209 sc->sc_dmat = ua->ua_dmat; 210 /* Process the 8 bytes of diagnostic info put into */ 211 /* the FIFO following the master reset operation. */ 212 213 printf("\n%s:", self->dv_xname); 214 for (n = 0; n < 8; n++) { 215 c = DHU_READ_WORD(DHU_UBA_RBUF); 216 217 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 218 if ((c&0200) == 0000) 219 printf(" rom(%d) version %d", 220 ((c>>1)&01), ((c>>2)&037)); 221 else if (((c>>2)&07) != 0) 222 printf(" diag-error(proc%d)=%x", 223 ((c>>1)&01), ((c>>2)&07)); 224 } 225 } 226 227 c = DHU_READ_WORD(DHU_UBA_STAT); 228 229 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 230 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 231 232 for (i = 0; i < sc->sc_type; i++) { 233 struct tty *tp; 234 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 235 sc->sc_dhu[i].dhu_state = STATE_IDLE; 236 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 237 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 238 &sc->sc_dhu[i].dhu_dmah); 239 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 240 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 241 242 } 243 244 /* Now establish RX & TX interrupt handlers */ 245 246 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 247 dhurint, sc, &sc->sc_rintrcnt); 248 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 249 dhuxint, sc, &sc->sc_tintrcnt); 250 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 251 sc->sc_dev.dv_xname, "rintr"); 252 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 253 sc->sc_dev.dv_xname, "tintr"); 254 } 255 256 /* Receiver Interrupt */ 257 258 static void 259 dhurint(arg) 260 void *arg; 261 { 262 struct dhu_softc *sc = arg; 263 struct tty *tp; 264 int cc, line; 265 unsigned c, delta; 266 int overrun = 0; 267 268 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 269 270 /* Ignore diagnostic FIFO entries. */ 271 272 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 273 continue; 274 275 cc = c & 0xFF; 276 line = DHU_LINE(c>>8); 277 tp = sc->sc_dhu[line].dhu_tty; 278 279 /* LINK.TYPE is set so we get modem control FIFO entries */ 280 281 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 282 c = (c << 8); 283 /* Do MDMBUF flow control, wakeup sleeping opens */ 284 if (c & DHU_STAT_DCD) { 285 if (!(tp->t_state & TS_CARR_ON)) 286 (void)(*tp->t_linesw->l_modem)(tp, 1); 287 } 288 else if ((tp->t_state & TS_CARR_ON) && 289 (*tp->t_linesw->l_modem)(tp, 0) == 0) 290 (void) dhumctl(sc, line, 0, DMSET); 291 292 /* Do CRTSCTS flow control */ 293 delta = c ^ sc->sc_dhu[line].dhu_modem; 294 sc->sc_dhu[line].dhu_modem = c; 295 if ((delta & DHU_STAT_CTS) && 296 (tp->t_state & TS_ISOPEN) && 297 (tp->t_cflag & CRTSCTS)) { 298 if (c & DHU_STAT_CTS) { 299 tp->t_state &= ~TS_TTSTOP; 300 ttstart(tp); 301 } else { 302 tp->t_state |= TS_TTSTOP; 303 dhustop(tp, 0); 304 } 305 } 306 continue; 307 } 308 309 if (!(tp->t_state & TS_ISOPEN)) { 310 wakeup((caddr_t)&tp->t_rawq); 311 continue; 312 } 313 314 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 315 log(LOG_WARNING, "%s: silo overflow, line %d\n", 316 sc->sc_dev.dv_xname, line); 317 overrun = 1; 318 } 319 /* A BREAK key will appear as a NULL with a framing error */ 320 if (c & DHU_RBUF_FRAMING_ERR) 321 cc |= TTY_FE; 322 if (c & DHU_RBUF_PARITY_ERR) 323 cc |= TTY_PE; 324 325 (*tp->t_linesw->l_rint)(cc, tp); 326 } 327 } 328 329 /* Transmitter Interrupt */ 330 331 static void 332 dhuxint(arg) 333 void *arg; 334 { 335 struct dhu_softc *sc = arg; 336 struct tty *tp; 337 int line; 338 339 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 340 341 tp = sc->sc_dhu[line].dhu_tty; 342 343 tp->t_state &= ~TS_BUSY; 344 if (tp->t_state & TS_FLUSH) 345 tp->t_state &= ~TS_FLUSH; 346 else { 347 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 348 sc->sc_dhu[line].dhu_cc -= 349 DHU_READ_WORD(DHU_UBA_TBUFCNT); 350 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 351 sc->sc_dhu[line].dhu_cc = 0; 352 } 353 354 sc->sc_dhu[line].dhu_state = STATE_IDLE; 355 356 (*tp->t_linesw->l_start)(tp); 357 } 358 359 int 360 dhuopen(devvp, flag, mode, p) 361 struct vnode *devvp; 362 int flag, mode; 363 struct proc *p; 364 { 365 struct tty *tp; 366 int unit, line; 367 struct dhu_softc *sc; 368 int s, error = 0; 369 dev_t dev; 370 371 dev = vdev_rdev(devvp); 372 unit = DHU_M2U(minor(dev)); 373 line = DHU_LINE(minor(dev)); 374 375 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 376 return (ENXIO); 377 378 sc = dhu_cd.cd_devs[unit]; 379 380 if (line >= sc->sc_type) 381 return ENXIO; 382 383 s = spltty(); 384 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 385 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 386 (void) splx(s); 387 388 vdev_setprivdata(devvp, sc); 389 390 tp = sc->sc_dhu[line].dhu_tty; 391 392 tp->t_oproc = dhustart; 393 tp->t_param = dhuparam; 394 tp->t_hwiflow = dhuiflow; 395 tp->t_dev = dev; 396 if ((tp->t_state & TS_ISOPEN) == 0) { 397 ttychars(tp); 398 if (tp->t_ispeed == 0) { 399 tp->t_iflag = TTYDEF_IFLAG; 400 tp->t_oflag = TTYDEF_OFLAG; 401 tp->t_cflag = TTYDEF_CFLAG; 402 tp->t_lflag = TTYDEF_LFLAG; 403 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 404 } 405 (void) dhuparam(tp, &tp->t_termios); 406 ttsetwater(tp); 407 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 408 return (EBUSY); 409 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 410 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 411 tp->t_state |= TS_CARR_ON; 412 s = spltty(); 413 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 414 !(tp->t_state & TS_CARR_ON)) { 415 tp->t_wopen++; 416 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 417 TTIPRI | PCATCH, ttopen, 0); 418 tp->t_wopen--; 419 if (error) 420 break; 421 } 422 (void) splx(s); 423 if (error) 424 return (error); 425 return ((*tp->t_linesw->l_open)(devvp, tp)); 426 } 427 428 /*ARGSUSED*/ 429 int 430 dhuclose(devvp, flag, mode, p) 431 struct vnode *devvp; 432 int flag, mode; 433 struct proc *p; 434 { 435 struct tty *tp; 436 int line; 437 struct dhu_softc *sc; 438 dev_t dev; 439 440 dev = vdev_rdev(devvp); 441 line = DHU_LINE(minor(dev)); 442 443 sc = vdev_privdata(devvp); 444 445 tp = sc->sc_dhu[line].dhu_tty; 446 447 (*tp->t_linesw->l_close)(tp, flag); 448 449 /* Make sure a BREAK state is not left enabled. */ 450 451 (void) dhumctl(sc, line, DML_BRK, DMBIC); 452 453 /* Do a hangup if so required. */ 454 455 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 456 !(tp->t_state & TS_ISOPEN)) 457 (void) dhumctl(sc, line, 0, DMSET); 458 459 return (ttyclose(tp)); 460 } 461 462 int 463 dhuread(devvp, uio, flag) 464 struct vnode *devvp; 465 struct uio *uio; 466 { 467 struct dhu_softc *sc; 468 struct tty *tp; 469 470 sc = vdev_privdata(devvp); 471 472 tp = sc->sc_dhu[DHU_LINE(minor(vdev_rdev(devvp)))].dhu_tty; 473 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 474 } 475 476 int 477 dhuwrite(devvp, uio, flag) 478 struct vnode *devvp; 479 struct uio *uio; 480 { 481 struct dhu_softc *sc; 482 struct tty *tp; 483 484 sc = vdev_privdata(devvp); 485 486 tp = sc->sc_dhu[DHU_LINE(minor(vdev_rdev(devvp)))].dhu_tty; 487 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 488 } 489 490 int 491 dhupoll(devvp, events, p) 492 struct vnode *devvp; 493 int events; 494 struct proc *p; 495 { 496 struct dhu_softc *sc; 497 struct tty *tp; 498 499 sc = vdev_privdata(devvp); 500 501 tp = sc->sc_dhu[DHU_LINE(minor(vdev_rdev(devvp)))].dhu_tty; 502 return ((*tp->t_linesw->l_poll)(tp, events, p)); 503 } 504 505 /*ARGSUSED*/ 506 int 507 dhuioctl(devvp, cmd, data, flag, p) 508 struct vnode *devvp; 509 u_long cmd; 510 caddr_t data; 511 int flag; 512 struct proc *p; 513 { 514 struct dhu_softc *sc; 515 struct tty *tp; 516 int line; 517 int error; 518 dev_t dev; 519 520 dev = vdev_rdev(devvp); 521 line = DHU_LINE(minor(dev)); 522 sc = vdev_privdata(devvp); 523 tp = sc->sc_dhu[line].dhu_tty; 524 525 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 526 if (error >= 0) 527 return (error); 528 error = ttioctl(tp, devvp, cmd, data, flag, p); 529 if (error >= 0) 530 return (error); 531 532 switch (cmd) { 533 534 case TIOCSBRK: 535 (void) dhumctl(sc, line, DML_BRK, DMBIS); 536 break; 537 538 case TIOCCBRK: 539 (void) dhumctl(sc, line, DML_BRK, DMBIC); 540 break; 541 542 case TIOCSDTR: 543 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 544 break; 545 546 case TIOCCDTR: 547 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 548 break; 549 550 case TIOCMSET: 551 (void) dhumctl(sc, line, *(int *)data, DMSET); 552 break; 553 554 case TIOCMBIS: 555 (void) dhumctl(sc, line, *(int *)data, DMBIS); 556 break; 557 558 case TIOCMBIC: 559 (void) dhumctl(sc, line, *(int *)data, DMBIC); 560 break; 561 562 case TIOCMGET: 563 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 564 break; 565 566 default: 567 return (ENOTTY); 568 } 569 return (0); 570 } 571 572 struct tty * 573 dhutty(devvp) 574 struct vnode *devvp; 575 { 576 dev_t dev = vdev_rdev(devvp); 577 struct dhu_softc *sc = vdev_privdata(devvp); 578 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 579 580 return (tp); 581 } 582 583 /*ARGSUSED*/ 584 void 585 dhustop(tp, flag) 586 struct tty *tp; 587 { 588 struct dhu_softc *sc; 589 int line; 590 int s; 591 dev_t dev; 592 593 dev = tp->t_dev; 594 595 s = spltty(); 596 597 if (tp->t_state & TS_BUSY) { 598 599 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 600 line = DHU_LINE(minor(dev)); 601 602 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 603 604 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 605 606 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 607 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 608 DHU_READ_WORD(DHU_UBA_LNCTRL) | 609 DHU_LNCTRL_DMA_ABORT); 610 } 611 612 if (!(tp->t_state & TS_TTSTOP)) 613 tp->t_state |= TS_FLUSH; 614 } 615 (void) splx(s); 616 } 617 618 static void 619 dhustart(tp) 620 struct tty *tp; 621 { 622 struct dhu_softc *sc; 623 int line, cc; 624 int addr; 625 int s; 626 dev_t dev; 627 628 s = spltty(); 629 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 630 goto out; 631 if (tp->t_outq.c_cc <= tp->t_lowat) { 632 if (tp->t_state & TS_ASLEEP) { 633 tp->t_state &= ~TS_ASLEEP; 634 wakeup((caddr_t)&tp->t_outq); 635 } 636 selwakeup(&tp->t_wsel); 637 } 638 if (tp->t_outq.c_cc == 0) 639 goto out; 640 cc = ndqb(&tp->t_outq, 0); 641 if (cc == 0) 642 goto out; 643 644 dev = tp->t_dev; 645 tp->t_state |= TS_BUSY; 646 647 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 648 649 line = DHU_LINE(minor(dev)); 650 651 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 652 653 sc->sc_dhu[line].dhu_cc = cc; 654 655 if (cc == 1) { 656 657 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 658 659 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 660 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 661 662 } else { 663 664 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 665 666 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 667 (tp->t_outq.c_cf - tp->t_outq.c_cs); 668 669 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 670 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 671 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 672 DHU_TBUFAD2_TX_ENABLE); 673 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 674 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 675 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 676 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 677 } 678 out: 679 (void) splx(s); 680 return; 681 } 682 683 static int 684 dhuparam(tp, t) 685 struct tty *tp; 686 struct termios *t; 687 { 688 struct dhu_softc *sc; 689 int cflag = t->c_cflag; 690 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 691 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 692 unsigned lpr, lnctrl; 693 int line, unit; 694 int s; 695 dev_t dev; 696 697 dev = tp->t_dev; 698 unit = DHU_M2U(minor(tp->t_dev)); 699 line = DHU_LINE(minor(dev)); 700 701 sc = dhu_cd.cd_devs[unit]; 702 703 /* check requested parameters */ 704 if (ospeed < 0 || ispeed < 0) 705 return (EINVAL); 706 707 tp->t_ispeed = t->c_ispeed; 708 tp->t_ospeed = t->c_ospeed; 709 tp->t_cflag = cflag; 710 711 if (ospeed == 0) { 712 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 713 return (0); 714 } 715 716 s = spltty(); 717 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 718 719 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 720 721 switch (cflag & CSIZE) { 722 723 case CS5: 724 lpr |= DHU_LPR_5_BIT_CHAR; 725 break; 726 727 case CS6: 728 lpr |= DHU_LPR_6_BIT_CHAR; 729 break; 730 731 case CS7: 732 lpr |= DHU_LPR_7_BIT_CHAR; 733 break; 734 735 default: 736 lpr |= DHU_LPR_8_BIT_CHAR; 737 break; 738 } 739 740 if (cflag & PARENB) 741 lpr |= DHU_LPR_PARENB; 742 if (!(cflag & PARODD)) 743 lpr |= DHU_LPR_EPAR; 744 if (cflag & CSTOPB) 745 lpr |= DHU_LPR_2_STOP; 746 747 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 748 749 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 750 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 751 752 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 753 754 /* Setting LINK.TYPE enables modem signal change interrupts. */ 755 756 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 757 758 /* Enable the auto XON/XOFF feature on the controller */ 759 760 if (t->c_iflag & IXON) 761 lnctrl |= DHU_LNCTRL_OAUTO; 762 else 763 lnctrl &= ~DHU_LNCTRL_OAUTO; 764 765 if (t->c_iflag & IXOFF) 766 lnctrl |= DHU_LNCTRL_IAUTO; 767 else 768 lnctrl &= ~DHU_LNCTRL_IAUTO; 769 770 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 771 772 (void) splx(s); 773 return (0); 774 } 775 776 static int 777 dhuiflow(tp, flag) 778 struct tty *tp; 779 int flag; 780 { 781 struct dhu_softc *sc; 782 dev_t dev; 783 int line; 784 785 dev = tp->t_dev; 786 line = DHU_LINE(minor(dev)); 787 if (tp->t_cflag & CRTSCTS) { 788 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 789 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 790 return (1); 791 } 792 return (0); 793 } 794 795 static unsigned 796 dhumctl(sc, line, bits, how) 797 struct dhu_softc *sc; 798 int line, bits, how; 799 { 800 unsigned status; 801 unsigned lnctrl; 802 unsigned mbits; 803 int s; 804 805 s = spltty(); 806 807 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 808 809 mbits = 0; 810 811 /* external signals as seen from the port */ 812 813 status = DHU_READ_WORD(DHU_UBA_STAT); 814 815 if (status & DHU_STAT_CTS) 816 mbits |= DML_CTS; 817 818 if (status & DHU_STAT_DCD) 819 mbits |= DML_DCD; 820 821 if (status & DHU_STAT_DSR) 822 mbits |= DML_DSR; 823 824 if (status & DHU_STAT_RI) 825 mbits |= DML_RI; 826 827 /* internal signals/state delivered to port */ 828 829 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 830 831 if (lnctrl & DHU_LNCTRL_RTS) 832 mbits |= DML_RTS; 833 834 if (lnctrl & DHU_LNCTRL_DTR) 835 mbits |= DML_DTR; 836 837 if (lnctrl & DHU_LNCTRL_BREAK) 838 mbits |= DML_BRK; 839 840 switch (how) { 841 842 case DMSET: 843 mbits = bits; 844 break; 845 846 case DMBIS: 847 mbits |= bits; 848 break; 849 850 case DMBIC: 851 mbits &= ~bits; 852 break; 853 854 case DMGET: 855 (void) splx(s); 856 return (mbits); 857 } 858 859 if (mbits & DML_RTS) 860 lnctrl |= DHU_LNCTRL_RTS; 861 else 862 lnctrl &= ~DHU_LNCTRL_RTS; 863 864 if (mbits & DML_DTR) 865 lnctrl |= DHU_LNCTRL_DTR; 866 else 867 lnctrl &= ~DHU_LNCTRL_DTR; 868 869 if (mbits & DML_BRK) 870 lnctrl |= DHU_LNCTRL_BREAK; 871 else 872 lnctrl &= ~DHU_LNCTRL_BREAK; 873 874 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 875 876 (void) splx(s); 877 return (mbits); 878 } 879
Indexes created Mon Oct 20 05:10:11 GMT 2025