dhu.c revision 1.26
1 /* $NetBSD: dhu.c,v 1.26 2002/03/17 19:41:01 atatat Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.26 2002/03/17 19:41:01 atatat Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/ioctl.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/map.h> 48 #include <sys/buf.h> 49 #include <sys/conf.h> 50 #include <sys/file.h> 51 #include <sys/uio.h> 52 #include <sys/kernel.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 56 #include <machine/bus.h> 57 #include <machine/scb.h> 58 59 #include <dev/qbus/ubavar.h> 60 61 #include <dev/qbus/dhureg.h> 62 63 #include "ioconf.h" 64 65 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 66 67 #define NDHULINE 16 68 69 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 70 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 71 72 struct dhu_softc { 73 struct device sc_dev; /* Device struct used by config */ 74 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 75 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 76 int sc_type; /* controller type, DHU or DHV */ 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 bus_dma_tag_t sc_dmat; 80 struct { 81 struct tty *dhu_tty; /* what we work on */ 82 bus_dmamap_t dhu_dmah; 83 int dhu_state; /* to manage TX output status */ 84 short dhu_cc; /* character count on TX */ 85 short dhu_modem; /* modem bits state */ 86 } sc_dhu[NDHULINE]; 87 }; 88 89 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 90 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 91 92 #define STATE_IDLE 000 /* no current output in progress */ 93 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 94 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 95 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 96 97 /* Flags used to monitor modem bits, make them understood outside driver */ 98 99 #define DML_DTR TIOCM_DTR 100 #define DML_RTS TIOCM_RTS 101 #define DML_CTS TIOCM_CTS 102 #define DML_DCD TIOCM_CD 103 #define DML_RI TIOCM_RI 104 #define DML_DSR TIOCM_DSR 105 #define DML_BRK 0100000 /* no equivalent, we will mask */ 106 107 #define DHU_READ_WORD(reg) \ 108 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 109 #define DHU_WRITE_WORD(reg, val) \ 110 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 111 #define DHU_READ_BYTE(reg) \ 112 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 113 #define DHU_WRITE_BYTE(reg, val) \ 114 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 115 116 117 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 118 /* a baud rate from the same group. So limiting to B is likely */ 119 /* best, although clone boards like the ABLE QHV allow all settings. */ 120 121 static struct speedtab dhuspeedtab[] = { 122 { 0, 0 }, /* Groups */ 123 { 50, DHU_LPR_B50 }, /* A */ 124 { 75, DHU_LPR_B75 }, /* B */ 125 { 110, DHU_LPR_B110 }, /* A and B */ 126 { 134, DHU_LPR_B134 }, /* A and B */ 127 { 150, DHU_LPR_B150 }, /* B */ 128 { 300, DHU_LPR_B300 }, /* A and B */ 129 { 600, DHU_LPR_B600 }, /* A and B */ 130 { 1200, DHU_LPR_B1200 }, /* A and B */ 131 { 1800, DHU_LPR_B1800 }, /* B */ 132 { 2000, DHU_LPR_B2000 }, /* B */ 133 { 2400, DHU_LPR_B2400 }, /* A and B */ 134 { 4800, DHU_LPR_B4800 }, /* A and B */ 135 { 7200, DHU_LPR_B7200 }, /* A */ 136 { 9600, DHU_LPR_B9600 }, /* A and B */ 137 { 19200, DHU_LPR_B19200 }, /* B */ 138 { 38400, DHU_LPR_B38400 }, /* A */ 139 { -1, -1 } 140 }; 141 142 static int dhu_match __P((struct device *, struct cfdata *, void *)); 143 static void dhu_attach __P((struct device *, struct device *, void *)); 144 static void dhurint __P((void *)); 145 static void dhuxint __P((void *)); 146 static void dhustart __P((struct tty *)); 147 static int dhuparam __P((struct tty *, struct termios *)); 148 static int dhuiflow __P((struct tty *, int)); 149 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 150 151 cdev_decl(dhu); 152 153 struct cfattach dhu_ca = { 154 sizeof(struct dhu_softc), dhu_match, dhu_attach 155 }; 156 157 /* Autoconfig handles: setup the controller to interrupt, */ 158 /* then complete the housecleaning for full operation */ 159 160 static int 161 dhu_match(parent, cf, aux) 162 struct device *parent; 163 struct cfdata *cf; 164 void *aux; 165 { 166 struct uba_attach_args *ua = aux; 167 int n; 168 169 /* Reset controller to initialize, enable TX/RX interrupts */ 170 /* to catch floating vector info elsewhere when completed */ 171 172 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 173 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 174 175 /* Now wait up to 3 seconds for self-test to complete. */ 176 177 for (n = 0; n < 300; n++) { 178 DELAY(10000); 179 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 180 DHU_CSR_MASTER_RESET) == 0) 181 break; 182 } 183 184 /* If the RESET did not clear after 3 seconds, */ 185 /* the controller must be broken. */ 186 187 if (n >= 300) 188 return 0; 189 190 /* Check whether diagnostic run has signalled a failure. */ 191 192 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 193 DHU_CSR_DIAG_FAIL) != 0) 194 return 0; 195 196 return 1; 197 } 198 199 static void 200 dhu_attach(parent, self, aux) 201 struct device *parent, *self; 202 void *aux; 203 { 204 struct dhu_softc *sc = (void *)self; 205 struct uba_attach_args *ua = aux; 206 unsigned c; 207 int n, i; 208 209 sc->sc_iot = ua->ua_iot; 210 sc->sc_ioh = ua->ua_ioh; 211 sc->sc_dmat = ua->ua_dmat; 212 /* Process the 8 bytes of diagnostic info put into */ 213 /* the FIFO following the master reset operation. */ 214 215 printf("\n%s:", self->dv_xname); 216 for (n = 0; n < 8; n++) { 217 c = DHU_READ_WORD(DHU_UBA_RBUF); 218 219 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 220 if ((c&0200) == 0000) 221 printf(" rom(%d) version %d", 222 ((c>>1)&01), ((c>>2)&037)); 223 else if (((c>>2)&07) != 0) 224 printf(" diag-error(proc%d)=%x", 225 ((c>>1)&01), ((c>>2)&07)); 226 } 227 } 228 229 c = DHU_READ_WORD(DHU_UBA_STAT); 230 231 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 232 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 233 234 for (i = 0; i < sc->sc_type; i++) { 235 struct tty *tp; 236 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 237 sc->sc_dhu[i].dhu_state = STATE_IDLE; 238 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 239 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 240 &sc->sc_dhu[i].dhu_dmah); 241 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 242 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 243 244 } 245 246 /* Now establish RX & TX interrupt handlers */ 247 248 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 249 dhurint, sc, &sc->sc_rintrcnt); 250 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 251 dhuxint, sc, &sc->sc_tintrcnt); 252 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 253 sc->sc_dev.dv_xname, "rintr"); 254 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 255 sc->sc_dev.dv_xname, "tintr"); 256 } 257 258 /* Receiver Interrupt */ 259 260 static void 261 dhurint(arg) 262 void *arg; 263 { 264 struct dhu_softc *sc = arg; 265 struct tty *tp; 266 int cc, line; 267 unsigned c, delta; 268 int overrun = 0; 269 270 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 271 272 /* Ignore diagnostic FIFO entries. */ 273 274 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 275 continue; 276 277 cc = c & 0xFF; 278 line = DHU_LINE(c>>8); 279 tp = sc->sc_dhu[line].dhu_tty; 280 281 /* LINK.TYPE is set so we get modem control FIFO entries */ 282 283 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 284 c = (c << 8); 285 /* Do MDMBUF flow control, wakeup sleeping opens */ 286 if (c & DHU_STAT_DCD) { 287 if (!(tp->t_state & TS_CARR_ON)) 288 (void)(*tp->t_linesw->l_modem)(tp, 1); 289 } 290 else if ((tp->t_state & TS_CARR_ON) && 291 (*tp->t_linesw->l_modem)(tp, 0) == 0) 292 (void) dhumctl(sc, line, 0, DMSET); 293 294 /* Do CRTSCTS flow control */ 295 delta = c ^ sc->sc_dhu[line].dhu_modem; 296 sc->sc_dhu[line].dhu_modem = c; 297 if ((delta & DHU_STAT_CTS) && 298 (tp->t_state & TS_ISOPEN) && 299 (tp->t_cflag & CRTSCTS)) { 300 if (c & DHU_STAT_CTS) { 301 tp->t_state &= ~TS_TTSTOP; 302 ttstart(tp); 303 } else { 304 tp->t_state |= TS_TTSTOP; 305 dhustop(tp, 0); 306 } 307 } 308 continue; 309 } 310 311 if (!(tp->t_state & TS_ISOPEN)) { 312 wakeup((caddr_t)&tp->t_rawq); 313 continue; 314 } 315 316 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 317 log(LOG_WARNING, "%s: silo overflow, line %d\n", 318 sc->sc_dev.dv_xname, line); 319 overrun = 1; 320 } 321 /* A BREAK key will appear as a NULL with a framing error */ 322 if (c & DHU_RBUF_FRAMING_ERR) 323 cc |= TTY_FE; 324 if (c & DHU_RBUF_PARITY_ERR) 325 cc |= TTY_PE; 326 327 (*tp->t_linesw->l_rint)(cc, tp); 328 } 329 } 330 331 /* Transmitter Interrupt */ 332 333 static void 334 dhuxint(arg) 335 void *arg; 336 { 337 struct dhu_softc *sc = arg; 338 struct tty *tp; 339 int line; 340 341 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 342 343 tp = sc->sc_dhu[line].dhu_tty; 344 345 tp->t_state &= ~TS_BUSY; 346 if (tp->t_state & TS_FLUSH) 347 tp->t_state &= ~TS_FLUSH; 348 else { 349 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 350 sc->sc_dhu[line].dhu_cc -= 351 DHU_READ_WORD(DHU_UBA_TBUFCNT); 352 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 353 sc->sc_dhu[line].dhu_cc = 0; 354 } 355 356 sc->sc_dhu[line].dhu_state = STATE_IDLE; 357 358 (*tp->t_linesw->l_start)(tp); 359 } 360 361 int 362 dhuopen(dev, flag, mode, p) 363 dev_t dev; 364 int flag, mode; 365 struct proc *p; 366 { 367 struct tty *tp; 368 int unit, line; 369 struct dhu_softc *sc; 370 int s, error = 0; 371 372 unit = DHU_M2U(minor(dev)); 373 line = DHU_LINE(minor(dev)); 374 375 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 376 return (ENXIO); 377 378 sc = dhu_cd.cd_devs[unit]; 379 380 if (line >= sc->sc_type) 381 return ENXIO; 382 383 s = spltty(); 384 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 385 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 386 (void) splx(s); 387 388 tp = sc->sc_dhu[line].dhu_tty; 389 390 tp->t_oproc = dhustart; 391 tp->t_param = dhuparam; 392 tp->t_hwiflow = dhuiflow; 393 tp->t_dev = dev; 394 if ((tp->t_state & TS_ISOPEN) == 0) { 395 ttychars(tp); 396 if (tp->t_ispeed == 0) { 397 tp->t_iflag = TTYDEF_IFLAG; 398 tp->t_oflag = TTYDEF_OFLAG; 399 tp->t_cflag = TTYDEF_CFLAG; 400 tp->t_lflag = TTYDEF_LFLAG; 401 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 402 } 403 (void) dhuparam(tp, &tp->t_termios); 404 ttsetwater(tp); 405 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 406 return (EBUSY); 407 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 408 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 409 tp->t_state |= TS_CARR_ON; 410 s = spltty(); 411 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 412 !(tp->t_state & TS_CARR_ON)) { 413 tp->t_wopen++; 414 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 415 TTIPRI | PCATCH, ttopen, 0); 416 tp->t_wopen--; 417 if (error) 418 break; 419 } 420 (void) splx(s); 421 if (error) 422 return (error); 423 return ((*tp->t_linesw->l_open)(dev, tp)); 424 } 425 426 /*ARGSUSED*/ 427 int 428 dhuclose(dev, flag, mode, p) 429 dev_t dev; 430 int flag, mode; 431 struct proc *p; 432 { 433 struct tty *tp; 434 int unit, line; 435 struct dhu_softc *sc; 436 437 unit = DHU_M2U(minor(dev)); 438 line = DHU_LINE(minor(dev)); 439 440 sc = dhu_cd.cd_devs[unit]; 441 442 tp = sc->sc_dhu[line].dhu_tty; 443 444 (*tp->t_linesw->l_close)(tp, flag); 445 446 /* Make sure a BREAK state is not left enabled. */ 447 448 (void) dhumctl(sc, line, DML_BRK, DMBIC); 449 450 /* Do a hangup if so required. */ 451 452 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 453 !(tp->t_state & TS_ISOPEN)) 454 (void) dhumctl(sc, line, 0, DMSET); 455 456 return (ttyclose(tp)); 457 } 458 459 int 460 dhuread(dev, uio, flag) 461 dev_t dev; 462 struct uio *uio; 463 { 464 struct dhu_softc *sc; 465 struct tty *tp; 466 467 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 468 469 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 470 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 471 } 472 473 int 474 dhuwrite(dev, uio, flag) 475 dev_t dev; 476 struct uio *uio; 477 { 478 struct dhu_softc *sc; 479 struct tty *tp; 480 481 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 482 483 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 484 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 485 } 486 487 int 488 dhupoll(dev, events, p) 489 dev_t dev; 490 int events; 491 struct proc *p; 492 { 493 struct dhu_softc *sc; 494 struct tty *tp; 495 496 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 497 498 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 499 return ((*tp->t_linesw->l_poll)(tp, events, p)); 500 } 501 502 /*ARGSUSED*/ 503 int 504 dhuioctl(dev, cmd, data, flag, p) 505 dev_t dev; 506 u_long cmd; 507 caddr_t data; 508 int flag; 509 struct proc *p; 510 { 511 struct dhu_softc *sc; 512 struct tty *tp; 513 int unit, line; 514 int error; 515 516 unit = DHU_M2U(minor(dev)); 517 line = DHU_LINE(minor(dev)); 518 sc = dhu_cd.cd_devs[unit]; 519 tp = sc->sc_dhu[line].dhu_tty; 520 521 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 522 if (error != EPASSTHROUGH) 523 return (error); 524 525 error = ttioctl(tp, cmd, data, flag, p); 526 if (error != EPASSTHROUGH) 527 return (error); 528 529 switch (cmd) { 530 531 case TIOCSBRK: 532 (void) dhumctl(sc, line, DML_BRK, DMBIS); 533 break; 534 535 case TIOCCBRK: 536 (void) dhumctl(sc, line, DML_BRK, DMBIC); 537 break; 538 539 case TIOCSDTR: 540 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 541 break; 542 543 case TIOCCDTR: 544 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 545 break; 546 547 case TIOCMSET: 548 (void) dhumctl(sc, line, *(int *)data, DMSET); 549 break; 550 551 case TIOCMBIS: 552 (void) dhumctl(sc, line, *(int *)data, DMBIS); 553 break; 554 555 case TIOCMBIC: 556 (void) dhumctl(sc, line, *(int *)data, DMBIC); 557 break; 558 559 case TIOCMGET: 560 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 561 break; 562 563 default: 564 return (EPASSTHROUGH); 565 } 566 return (0); 567 } 568 569 struct tty * 570 dhutty(dev) 571 dev_t dev; 572 { 573 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 574 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 575 return (tp); 576 } 577 578 /*ARGSUSED*/ 579 void 580 dhustop(tp, flag) 581 struct tty *tp; 582 { 583 struct dhu_softc *sc; 584 int line; 585 int s; 586 587 s = spltty(); 588 589 if (tp->t_state & TS_BUSY) { 590 591 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 592 line = DHU_LINE(minor(tp->t_dev)); 593 594 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 595 596 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 597 598 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 599 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 600 DHU_READ_WORD(DHU_UBA_LNCTRL) | 601 DHU_LNCTRL_DMA_ABORT); 602 } 603 604 if (!(tp->t_state & TS_TTSTOP)) 605 tp->t_state |= TS_FLUSH; 606 } 607 (void) splx(s); 608 } 609 610 static void 611 dhustart(tp) 612 struct tty *tp; 613 { 614 struct dhu_softc *sc; 615 int line, cc; 616 int addr; 617 int s; 618 619 s = spltty(); 620 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 621 goto out; 622 if (tp->t_outq.c_cc <= tp->t_lowat) { 623 if (tp->t_state & TS_ASLEEP) { 624 tp->t_state &= ~TS_ASLEEP; 625 wakeup((caddr_t)&tp->t_outq); 626 } 627 selwakeup(&tp->t_wsel); 628 } 629 if (tp->t_outq.c_cc == 0) 630 goto out; 631 cc = ndqb(&tp->t_outq, 0); 632 if (cc == 0) 633 goto out; 634 635 tp->t_state |= TS_BUSY; 636 637 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 638 639 line = DHU_LINE(minor(tp->t_dev)); 640 641 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 642 643 sc->sc_dhu[line].dhu_cc = cc; 644 645 if (cc == 1) { 646 647 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 648 649 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 650 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 651 652 } else { 653 654 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 655 656 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 657 (tp->t_outq.c_cf - tp->t_outq.c_cs); 658 659 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 660 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 661 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 662 DHU_TBUFAD2_TX_ENABLE); 663 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 664 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 665 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 666 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 667 } 668 out: 669 (void) splx(s); 670 return; 671 } 672 673 static int 674 dhuparam(tp, t) 675 struct tty *tp; 676 struct termios *t; 677 { 678 struct dhu_softc *sc; 679 int cflag = t->c_cflag; 680 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 681 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 682 unsigned lpr, lnctrl; 683 int unit, line; 684 int s; 685 686 unit = DHU_M2U(minor(tp->t_dev)); 687 line = DHU_LINE(minor(tp->t_dev)); 688 689 sc = dhu_cd.cd_devs[unit]; 690 691 /* check requested parameters */ 692 if (ospeed < 0 || ispeed < 0) 693 return (EINVAL); 694 695 tp->t_ispeed = t->c_ispeed; 696 tp->t_ospeed = t->c_ospeed; 697 tp->t_cflag = cflag; 698 699 if (ospeed == 0) { 700 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 701 return (0); 702 } 703 704 s = spltty(); 705 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 706 707 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 708 709 switch (cflag & CSIZE) { 710 711 case CS5: 712 lpr |= DHU_LPR_5_BIT_CHAR; 713 break; 714 715 case CS6: 716 lpr |= DHU_LPR_6_BIT_CHAR; 717 break; 718 719 case CS7: 720 lpr |= DHU_LPR_7_BIT_CHAR; 721 break; 722 723 default: 724 lpr |= DHU_LPR_8_BIT_CHAR; 725 break; 726 } 727 728 if (cflag & PARENB) 729 lpr |= DHU_LPR_PARENB; 730 if (!(cflag & PARODD)) 731 lpr |= DHU_LPR_EPAR; 732 if (cflag & CSTOPB) 733 lpr |= DHU_LPR_2_STOP; 734 735 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 736 737 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 738 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 739 740 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 741 742 /* Setting LINK.TYPE enables modem signal change interrupts. */ 743 744 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 745 746 /* Enable the auto XON/XOFF feature on the controller */ 747 748 if (t->c_iflag & IXON) 749 lnctrl |= DHU_LNCTRL_OAUTO; 750 else 751 lnctrl &= ~DHU_LNCTRL_OAUTO; 752 753 if (t->c_iflag & IXOFF) 754 lnctrl |= DHU_LNCTRL_IAUTO; 755 else 756 lnctrl &= ~DHU_LNCTRL_IAUTO; 757 758 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 759 760 (void) splx(s); 761 return (0); 762 } 763 764 static int 765 dhuiflow(tp, flag) 766 struct tty *tp; 767 int flag; 768 { 769 struct dhu_softc *sc; 770 int line = DHU_LINE(minor(tp->t_dev)); 771 772 if (tp->t_cflag & CRTSCTS) { 773 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 774 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 775 return (1); 776 } 777 return (0); 778 } 779 780 static unsigned 781 dhumctl(sc, line, bits, how) 782 struct dhu_softc *sc; 783 int line, bits, how; 784 { 785 unsigned status; 786 unsigned lnctrl; 787 unsigned mbits; 788 int s; 789 790 s = spltty(); 791 792 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 793 794 mbits = 0; 795 796 /* external signals as seen from the port */ 797 798 status = DHU_READ_WORD(DHU_UBA_STAT); 799 800 if (status & DHU_STAT_CTS) 801 mbits |= DML_CTS; 802 803 if (status & DHU_STAT_DCD) 804 mbits |= DML_DCD; 805 806 if (status & DHU_STAT_DSR) 807 mbits |= DML_DSR; 808 809 if (status & DHU_STAT_RI) 810 mbits |= DML_RI; 811 812 /* internal signals/state delivered to port */ 813 814 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 815 816 if (lnctrl & DHU_LNCTRL_RTS) 817 mbits |= DML_RTS; 818 819 if (lnctrl & DHU_LNCTRL_DTR) 820 mbits |= DML_DTR; 821 822 if (lnctrl & DHU_LNCTRL_BREAK) 823 mbits |= DML_BRK; 824 825 switch (how) { 826 827 case DMSET: 828 mbits = bits; 829 break; 830 831 case DMBIS: 832 mbits |= bits; 833 break; 834 835 case DMBIC: 836 mbits &= ~bits; 837 break; 838 839 case DMGET: 840 (void) splx(s); 841 return (mbits); 842 } 843 844 if (mbits & DML_RTS) 845 lnctrl |= DHU_LNCTRL_RTS; 846 else 847 lnctrl &= ~DHU_LNCTRL_RTS; 848 849 if (mbits & DML_DTR) 850 lnctrl |= DHU_LNCTRL_DTR; 851 else 852 lnctrl &= ~DHU_LNCTRL_DTR; 853 854 if (mbits & DML_BRK) 855 lnctrl |= DHU_LNCTRL_BREAK; 856 else 857 lnctrl &= ~DHU_LNCTRL_BREAK; 858 859 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 860 861 (void) splx(s); 862 return (mbits); 863 } 864
Indexes created Tue Sep 23 07:09:52 GMT 2025