dhu.c revision 1.27
1 /* $NetBSD: dhu.c,v 1.27 2002/09/06 13:18:43 gehenna Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.27 2002/09/06 13:18:43 gehenna Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/ioctl.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/map.h> 48 #include <sys/buf.h> 49 #include <sys/conf.h> 50 #include <sys/file.h> 51 #include <sys/uio.h> 52 #include <sys/kernel.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 56 #include <machine/bus.h> 57 #include <machine/scb.h> 58 59 #include <dev/qbus/ubavar.h> 60 61 #include <dev/qbus/dhureg.h> 62 63 #include "ioconf.h" 64 65 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 66 67 #define NDHULINE 16 68 69 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 70 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 71 72 struct dhu_softc { 73 struct device sc_dev; /* Device struct used by config */ 74 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 75 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 76 int sc_type; /* controller type, DHU or DHV */ 77 bus_space_tag_t sc_iot; 78 bus_space_handle_t sc_ioh; 79 bus_dma_tag_t sc_dmat; 80 struct { 81 struct tty *dhu_tty; /* what we work on */ 82 bus_dmamap_t dhu_dmah; 83 int dhu_state; /* to manage TX output status */ 84 short dhu_cc; /* character count on TX */ 85 short dhu_modem; /* modem bits state */ 86 } sc_dhu[NDHULINE]; 87 }; 88 89 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 90 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 91 92 #define STATE_IDLE 000 /* no current output in progress */ 93 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 94 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 95 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 96 97 /* Flags used to monitor modem bits, make them understood outside driver */ 98 99 #define DML_DTR TIOCM_DTR 100 #define DML_RTS TIOCM_RTS 101 #define DML_CTS TIOCM_CTS 102 #define DML_DCD TIOCM_CD 103 #define DML_RI TIOCM_RI 104 #define DML_DSR TIOCM_DSR 105 #define DML_BRK 0100000 /* no equivalent, we will mask */ 106 107 #define DHU_READ_WORD(reg) \ 108 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 109 #define DHU_WRITE_WORD(reg, val) \ 110 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 111 #define DHU_READ_BYTE(reg) \ 112 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 113 #define DHU_WRITE_BYTE(reg, val) \ 114 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 115 116 117 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 118 /* a baud rate from the same group. So limiting to B is likely */ 119 /* best, although clone boards like the ABLE QHV allow all settings. */ 120 121 static struct speedtab dhuspeedtab[] = { 122 { 0, 0 }, /* Groups */ 123 { 50, DHU_LPR_B50 }, /* A */ 124 { 75, DHU_LPR_B75 }, /* B */ 125 { 110, DHU_LPR_B110 }, /* A and B */ 126 { 134, DHU_LPR_B134 }, /* A and B */ 127 { 150, DHU_LPR_B150 }, /* B */ 128 { 300, DHU_LPR_B300 }, /* A and B */ 129 { 600, DHU_LPR_B600 }, /* A and B */ 130 { 1200, DHU_LPR_B1200 }, /* A and B */ 131 { 1800, DHU_LPR_B1800 }, /* B */ 132 { 2000, DHU_LPR_B2000 }, /* B */ 133 { 2400, DHU_LPR_B2400 }, /* A and B */ 134 { 4800, DHU_LPR_B4800 }, /* A and B */ 135 { 7200, DHU_LPR_B7200 }, /* A */ 136 { 9600, DHU_LPR_B9600 }, /* A and B */ 137 { 19200, DHU_LPR_B19200 }, /* B */ 138 { 38400, DHU_LPR_B38400 }, /* A */ 139 { -1, -1 } 140 }; 141 142 static int dhu_match __P((struct device *, struct cfdata *, void *)); 143 static void dhu_attach __P((struct device *, struct device *, void *)); 144 static void dhurint __P((void *)); 145 static void dhuxint __P((void *)); 146 static void dhustart __P((struct tty *)); 147 static int dhuparam __P((struct tty *, struct termios *)); 148 static int dhuiflow __P((struct tty *, int)); 149 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 150 151 struct cfattach dhu_ca = { 152 sizeof(struct dhu_softc), dhu_match, dhu_attach 153 }; 154 155 dev_type_open(dhuopen); 156 dev_type_close(dhuclose); 157 dev_type_read(dhuread); 158 dev_type_write(dhuwrite); 159 dev_type_ioctl(dhuioctl); 160 dev_type_stop(dhustop); 161 dev_type_tty(dhutty); 162 dev_type_poll(dhupoll); 163 164 const struct cdevsw dhu_cdevsw = { 165 dhuopen, dhuclose, dhuread, dhuwrite, dhuioctl, 166 dhustop, dhutty, dhupoll, nommap, D_TTY 167 }; 168 169 /* Autoconfig handles: setup the controller to interrupt, */ 170 /* then complete the housecleaning for full operation */ 171 172 static int 173 dhu_match(parent, cf, aux) 174 struct device *parent; 175 struct cfdata *cf; 176 void *aux; 177 { 178 struct uba_attach_args *ua = aux; 179 int n; 180 181 /* Reset controller to initialize, enable TX/RX interrupts */ 182 /* to catch floating vector info elsewhere when completed */ 183 184 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 185 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 186 187 /* Now wait up to 3 seconds for self-test to complete. */ 188 189 for (n = 0; n < 300; n++) { 190 DELAY(10000); 191 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 192 DHU_CSR_MASTER_RESET) == 0) 193 break; 194 } 195 196 /* If the RESET did not clear after 3 seconds, */ 197 /* the controller must be broken. */ 198 199 if (n >= 300) 200 return 0; 201 202 /* Check whether diagnostic run has signalled a failure. */ 203 204 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 205 DHU_CSR_DIAG_FAIL) != 0) 206 return 0; 207 208 return 1; 209 } 210 211 static void 212 dhu_attach(parent, self, aux) 213 struct device *parent, *self; 214 void *aux; 215 { 216 struct dhu_softc *sc = (void *)self; 217 struct uba_attach_args *ua = aux; 218 unsigned c; 219 int n, i; 220 221 sc->sc_iot = ua->ua_iot; 222 sc->sc_ioh = ua->ua_ioh; 223 sc->sc_dmat = ua->ua_dmat; 224 /* Process the 8 bytes of diagnostic info put into */ 225 /* the FIFO following the master reset operation. */ 226 227 printf("\n%s:", self->dv_xname); 228 for (n = 0; n < 8; n++) { 229 c = DHU_READ_WORD(DHU_UBA_RBUF); 230 231 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 232 if ((c&0200) == 0000) 233 printf(" rom(%d) version %d", 234 ((c>>1)&01), ((c>>2)&037)); 235 else if (((c>>2)&07) != 0) 236 printf(" diag-error(proc%d)=%x", 237 ((c>>1)&01), ((c>>2)&07)); 238 } 239 } 240 241 c = DHU_READ_WORD(DHU_UBA_STAT); 242 243 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 244 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 245 246 for (i = 0; i < sc->sc_type; i++) { 247 struct tty *tp; 248 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 249 sc->sc_dhu[i].dhu_state = STATE_IDLE; 250 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 251 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 252 &sc->sc_dhu[i].dhu_dmah); 253 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 254 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 255 256 } 257 258 /* Now establish RX & TX interrupt handlers */ 259 260 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 261 dhurint, sc, &sc->sc_rintrcnt); 262 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 263 dhuxint, sc, &sc->sc_tintrcnt); 264 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 265 sc->sc_dev.dv_xname, "rintr"); 266 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 267 sc->sc_dev.dv_xname, "tintr"); 268 } 269 270 /* Receiver Interrupt */ 271 272 static void 273 dhurint(arg) 274 void *arg; 275 { 276 struct dhu_softc *sc = arg; 277 struct tty *tp; 278 int cc, line; 279 unsigned c, delta; 280 int overrun = 0; 281 282 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 283 284 /* Ignore diagnostic FIFO entries. */ 285 286 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 287 continue; 288 289 cc = c & 0xFF; 290 line = DHU_LINE(c>>8); 291 tp = sc->sc_dhu[line].dhu_tty; 292 293 /* LINK.TYPE is set so we get modem control FIFO entries */ 294 295 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 296 c = (c << 8); 297 /* Do MDMBUF flow control, wakeup sleeping opens */ 298 if (c & DHU_STAT_DCD) { 299 if (!(tp->t_state & TS_CARR_ON)) 300 (void)(*tp->t_linesw->l_modem)(tp, 1); 301 } 302 else if ((tp->t_state & TS_CARR_ON) && 303 (*tp->t_linesw->l_modem)(tp, 0) == 0) 304 (void) dhumctl(sc, line, 0, DMSET); 305 306 /* Do CRTSCTS flow control */ 307 delta = c ^ sc->sc_dhu[line].dhu_modem; 308 sc->sc_dhu[line].dhu_modem = c; 309 if ((delta & DHU_STAT_CTS) && 310 (tp->t_state & TS_ISOPEN) && 311 (tp->t_cflag & CRTSCTS)) { 312 if (c & DHU_STAT_CTS) { 313 tp->t_state &= ~TS_TTSTOP; 314 ttstart(tp); 315 } else { 316 tp->t_state |= TS_TTSTOP; 317 dhustop(tp, 0); 318 } 319 } 320 continue; 321 } 322 323 if (!(tp->t_state & TS_ISOPEN)) { 324 wakeup((caddr_t)&tp->t_rawq); 325 continue; 326 } 327 328 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 329 log(LOG_WARNING, "%s: silo overflow, line %d\n", 330 sc->sc_dev.dv_xname, line); 331 overrun = 1; 332 } 333 /* A BREAK key will appear as a NULL with a framing error */ 334 if (c & DHU_RBUF_FRAMING_ERR) 335 cc |= TTY_FE; 336 if (c & DHU_RBUF_PARITY_ERR) 337 cc |= TTY_PE; 338 339 (*tp->t_linesw->l_rint)(cc, tp); 340 } 341 } 342 343 /* Transmitter Interrupt */ 344 345 static void 346 dhuxint(arg) 347 void *arg; 348 { 349 struct dhu_softc *sc = arg; 350 struct tty *tp; 351 int line; 352 353 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 354 355 tp = sc->sc_dhu[line].dhu_tty; 356 357 tp->t_state &= ~TS_BUSY; 358 if (tp->t_state & TS_FLUSH) 359 tp->t_state &= ~TS_FLUSH; 360 else { 361 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 362 sc->sc_dhu[line].dhu_cc -= 363 DHU_READ_WORD(DHU_UBA_TBUFCNT); 364 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 365 sc->sc_dhu[line].dhu_cc = 0; 366 } 367 368 sc->sc_dhu[line].dhu_state = STATE_IDLE; 369 370 (*tp->t_linesw->l_start)(tp); 371 } 372 373 int 374 dhuopen(dev, flag, mode, p) 375 dev_t dev; 376 int flag, mode; 377 struct proc *p; 378 { 379 struct tty *tp; 380 int unit, line; 381 struct dhu_softc *sc; 382 int s, error = 0; 383 384 unit = DHU_M2U(minor(dev)); 385 line = DHU_LINE(minor(dev)); 386 387 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 388 return (ENXIO); 389 390 sc = dhu_cd.cd_devs[unit]; 391 392 if (line >= sc->sc_type) 393 return ENXIO; 394 395 s = spltty(); 396 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 397 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 398 (void) splx(s); 399 400 tp = sc->sc_dhu[line].dhu_tty; 401 402 tp->t_oproc = dhustart; 403 tp->t_param = dhuparam; 404 tp->t_hwiflow = dhuiflow; 405 tp->t_dev = dev; 406 if ((tp->t_state & TS_ISOPEN) == 0) { 407 ttychars(tp); 408 if (tp->t_ispeed == 0) { 409 tp->t_iflag = TTYDEF_IFLAG; 410 tp->t_oflag = TTYDEF_OFLAG; 411 tp->t_cflag = TTYDEF_CFLAG; 412 tp->t_lflag = TTYDEF_LFLAG; 413 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 414 } 415 (void) dhuparam(tp, &tp->t_termios); 416 ttsetwater(tp); 417 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 418 return (EBUSY); 419 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 420 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 421 tp->t_state |= TS_CARR_ON; 422 s = spltty(); 423 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 424 !(tp->t_state & TS_CARR_ON)) { 425 tp->t_wopen++; 426 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 427 TTIPRI | PCATCH, ttopen, 0); 428 tp->t_wopen--; 429 if (error) 430 break; 431 } 432 (void) splx(s); 433 if (error) 434 return (error); 435 return ((*tp->t_linesw->l_open)(dev, tp)); 436 } 437 438 /*ARGSUSED*/ 439 int 440 dhuclose(dev, flag, mode, p) 441 dev_t dev; 442 int flag, mode; 443 struct proc *p; 444 { 445 struct tty *tp; 446 int unit, line; 447 struct dhu_softc *sc; 448 449 unit = DHU_M2U(minor(dev)); 450 line = DHU_LINE(minor(dev)); 451 452 sc = dhu_cd.cd_devs[unit]; 453 454 tp = sc->sc_dhu[line].dhu_tty; 455 456 (*tp->t_linesw->l_close)(tp, flag); 457 458 /* Make sure a BREAK state is not left enabled. */ 459 460 (void) dhumctl(sc, line, DML_BRK, DMBIC); 461 462 /* Do a hangup if so required. */ 463 464 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 465 !(tp->t_state & TS_ISOPEN)) 466 (void) dhumctl(sc, line, 0, DMSET); 467 468 return (ttyclose(tp)); 469 } 470 471 int 472 dhuread(dev, uio, flag) 473 dev_t dev; 474 struct uio *uio; 475 int flag; 476 { 477 struct dhu_softc *sc; 478 struct tty *tp; 479 480 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 481 482 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 483 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 484 } 485 486 int 487 dhuwrite(dev, uio, flag) 488 dev_t dev; 489 struct uio *uio; 490 int flag; 491 { 492 struct dhu_softc *sc; 493 struct tty *tp; 494 495 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 496 497 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 498 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 499 } 500 501 int 502 dhupoll(dev, events, p) 503 dev_t dev; 504 int events; 505 struct proc *p; 506 { 507 struct dhu_softc *sc; 508 struct tty *tp; 509 510 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 511 512 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 513 return ((*tp->t_linesw->l_poll)(tp, events, p)); 514 } 515 516 /*ARGSUSED*/ 517 int 518 dhuioctl(dev, cmd, data, flag, p) 519 dev_t dev; 520 u_long cmd; 521 caddr_t data; 522 int flag; 523 struct proc *p; 524 { 525 struct dhu_softc *sc; 526 struct tty *tp; 527 int unit, line; 528 int error; 529 530 unit = DHU_M2U(minor(dev)); 531 line = DHU_LINE(minor(dev)); 532 sc = dhu_cd.cd_devs[unit]; 533 tp = sc->sc_dhu[line].dhu_tty; 534 535 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 536 if (error != EPASSTHROUGH) 537 return (error); 538 539 error = ttioctl(tp, cmd, data, flag, p); 540 if (error != EPASSTHROUGH) 541 return (error); 542 543 switch (cmd) { 544 545 case TIOCSBRK: 546 (void) dhumctl(sc, line, DML_BRK, DMBIS); 547 break; 548 549 case TIOCCBRK: 550 (void) dhumctl(sc, line, DML_BRK, DMBIC); 551 break; 552 553 case TIOCSDTR: 554 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 555 break; 556 557 case TIOCCDTR: 558 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 559 break; 560 561 case TIOCMSET: 562 (void) dhumctl(sc, line, *(int *)data, DMSET); 563 break; 564 565 case TIOCMBIS: 566 (void) dhumctl(sc, line, *(int *)data, DMBIS); 567 break; 568 569 case TIOCMBIC: 570 (void) dhumctl(sc, line, *(int *)data, DMBIC); 571 break; 572 573 case TIOCMGET: 574 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 575 break; 576 577 default: 578 return (EPASSTHROUGH); 579 } 580 return (0); 581 } 582 583 struct tty * 584 dhutty(dev) 585 dev_t dev; 586 { 587 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 588 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 589 return (tp); 590 } 591 592 /*ARGSUSED*/ 593 void 594 dhustop(tp, flag) 595 struct tty *tp; 596 int flag; 597 { 598 struct dhu_softc *sc; 599 int line; 600 int s; 601 602 s = spltty(); 603 604 if (tp->t_state & TS_BUSY) { 605 606 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 607 line = DHU_LINE(minor(tp->t_dev)); 608 609 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 610 611 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 612 613 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 614 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 615 DHU_READ_WORD(DHU_UBA_LNCTRL) | 616 DHU_LNCTRL_DMA_ABORT); 617 } 618 619 if (!(tp->t_state & TS_TTSTOP)) 620 tp->t_state |= TS_FLUSH; 621 } 622 (void) splx(s); 623 } 624 625 static void 626 dhustart(tp) 627 struct tty *tp; 628 { 629 struct dhu_softc *sc; 630 int line, cc; 631 int addr; 632 int s; 633 634 s = spltty(); 635 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 636 goto out; 637 if (tp->t_outq.c_cc <= tp->t_lowat) { 638 if (tp->t_state & TS_ASLEEP) { 639 tp->t_state &= ~TS_ASLEEP; 640 wakeup((caddr_t)&tp->t_outq); 641 } 642 selwakeup(&tp->t_wsel); 643 } 644 if (tp->t_outq.c_cc == 0) 645 goto out; 646 cc = ndqb(&tp->t_outq, 0); 647 if (cc == 0) 648 goto out; 649 650 tp->t_state |= TS_BUSY; 651 652 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 653 654 line = DHU_LINE(minor(tp->t_dev)); 655 656 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 657 658 sc->sc_dhu[line].dhu_cc = cc; 659 660 if (cc == 1) { 661 662 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 663 664 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 665 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 666 667 } else { 668 669 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 670 671 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 672 (tp->t_outq.c_cf - tp->t_outq.c_cs); 673 674 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 675 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 676 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 677 DHU_TBUFAD2_TX_ENABLE); 678 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 679 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 680 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 681 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 682 } 683 out: 684 (void) splx(s); 685 return; 686 } 687 688 static int 689 dhuparam(tp, t) 690 struct tty *tp; 691 struct termios *t; 692 { 693 struct dhu_softc *sc; 694 int cflag = t->c_cflag; 695 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 696 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 697 unsigned lpr, lnctrl; 698 int unit, line; 699 int s; 700 701 unit = DHU_M2U(minor(tp->t_dev)); 702 line = DHU_LINE(minor(tp->t_dev)); 703 704 sc = dhu_cd.cd_devs[unit]; 705 706 /* check requested parameters */ 707 if (ospeed < 0 || ispeed < 0) 708 return (EINVAL); 709 710 tp->t_ispeed = t->c_ispeed; 711 tp->t_ospeed = t->c_ospeed; 712 tp->t_cflag = cflag; 713 714 if (ospeed == 0) { 715 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 716 return (0); 717 } 718 719 s = spltty(); 720 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 721 722 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 723 724 switch (cflag & CSIZE) { 725 726 case CS5: 727 lpr |= DHU_LPR_5_BIT_CHAR; 728 break; 729 730 case CS6: 731 lpr |= DHU_LPR_6_BIT_CHAR; 732 break; 733 734 case CS7: 735 lpr |= DHU_LPR_7_BIT_CHAR; 736 break; 737 738 default: 739 lpr |= DHU_LPR_8_BIT_CHAR; 740 break; 741 } 742 743 if (cflag & PARENB) 744 lpr |= DHU_LPR_PARENB; 745 if (!(cflag & PARODD)) 746 lpr |= DHU_LPR_EPAR; 747 if (cflag & CSTOPB) 748 lpr |= DHU_LPR_2_STOP; 749 750 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 751 752 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 753 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 754 755 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 756 757 /* Setting LINK.TYPE enables modem signal change interrupts. */ 758 759 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 760 761 /* Enable the auto XON/XOFF feature on the controller */ 762 763 if (t->c_iflag & IXON) 764 lnctrl |= DHU_LNCTRL_OAUTO; 765 else 766 lnctrl &= ~DHU_LNCTRL_OAUTO; 767 768 if (t->c_iflag & IXOFF) 769 lnctrl |= DHU_LNCTRL_IAUTO; 770 else 771 lnctrl &= ~DHU_LNCTRL_IAUTO; 772 773 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 774 775 (void) splx(s); 776 return (0); 777 } 778 779 static int 780 dhuiflow(tp, flag) 781 struct tty *tp; 782 int flag; 783 { 784 struct dhu_softc *sc; 785 int line = DHU_LINE(minor(tp->t_dev)); 786 787 if (tp->t_cflag & CRTSCTS) { 788 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 789 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 790 return (1); 791 } 792 return (0); 793 } 794 795 static unsigned 796 dhumctl(sc, line, bits, how) 797 struct dhu_softc *sc; 798 int line, bits, how; 799 { 800 unsigned status; 801 unsigned lnctrl; 802 unsigned mbits; 803 int s; 804 805 s = spltty(); 806 807 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 808 809 mbits = 0; 810 811 /* external signals as seen from the port */ 812 813 status = DHU_READ_WORD(DHU_UBA_STAT); 814 815 if (status & DHU_STAT_CTS) 816 mbits |= DML_CTS; 817 818 if (status & DHU_STAT_DCD) 819 mbits |= DML_DCD; 820 821 if (status & DHU_STAT_DSR) 822 mbits |= DML_DSR; 823 824 if (status & DHU_STAT_RI) 825 mbits |= DML_RI; 826 827 /* internal signals/state delivered to port */ 828 829 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 830 831 if (lnctrl & DHU_LNCTRL_RTS) 832 mbits |= DML_RTS; 833 834 if (lnctrl & DHU_LNCTRL_DTR) 835 mbits |= DML_DTR; 836 837 if (lnctrl & DHU_LNCTRL_BREAK) 838 mbits |= DML_BRK; 839 840 switch (how) { 841 842 case DMSET: 843 mbits = bits; 844 break; 845 846 case DMBIS: 847 mbits |= bits; 848 break; 849 850 case DMBIC: 851 mbits &= ~bits; 852 break; 853 854 case DMGET: 855 (void) splx(s); 856 return (mbits); 857 } 858 859 if (mbits & DML_RTS) 860 lnctrl |= DHU_LNCTRL_RTS; 861 else 862 lnctrl &= ~DHU_LNCTRL_RTS; 863 864 if (mbits & DML_DTR) 865 lnctrl |= DHU_LNCTRL_DTR; 866 else 867 lnctrl &= ~DHU_LNCTRL_DTR; 868 869 if (mbits & DML_BRK) 870 lnctrl |= DHU_LNCTRL_BREAK; 871 else 872 lnctrl &= ~DHU_LNCTRL_BREAK; 873 874 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 875 876 (void) splx(s); 877 return (mbits); 878 } 879
Indexes created Tue Sep 23 14:10:03 GMT 2025