dhu.c revision 1.28
1 /* $NetBSD: dhu.c,v 1.28 2002/09/25 22:21:38 thorpej Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.28 2002/09/25 22:21:38 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/ioctl.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/buf.h> 48 #include <sys/conf.h> 49 #include <sys/file.h> 50 #include <sys/uio.h> 51 #include <sys/kernel.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 55 #include <machine/bus.h> 56 #include <machine/scb.h> 57 58 #include <dev/qbus/ubavar.h> 59 60 #include <dev/qbus/dhureg.h> 61 62 #include "ioconf.h" 63 64 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 65 66 #define NDHULINE 16 67 68 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 69 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 70 71 struct dhu_softc { 72 struct device sc_dev; /* Device struct used by config */ 73 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 74 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 75 int sc_type; /* controller type, DHU or DHV */ 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 bus_dma_tag_t sc_dmat; 79 struct { 80 struct tty *dhu_tty; /* what we work on */ 81 bus_dmamap_t dhu_dmah; 82 int dhu_state; /* to manage TX output status */ 83 short dhu_cc; /* character count on TX */ 84 short dhu_modem; /* modem bits state */ 85 } sc_dhu[NDHULINE]; 86 }; 87 88 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 89 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 90 91 #define STATE_IDLE 000 /* no current output in progress */ 92 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 93 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 94 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 95 96 /* Flags used to monitor modem bits, make them understood outside driver */ 97 98 #define DML_DTR TIOCM_DTR 99 #define DML_RTS TIOCM_RTS 100 #define DML_CTS TIOCM_CTS 101 #define DML_DCD TIOCM_CD 102 #define DML_RI TIOCM_RI 103 #define DML_DSR TIOCM_DSR 104 #define DML_BRK 0100000 /* no equivalent, we will mask */ 105 106 #define DHU_READ_WORD(reg) \ 107 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 108 #define DHU_WRITE_WORD(reg, val) \ 109 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 110 #define DHU_READ_BYTE(reg) \ 111 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 112 #define DHU_WRITE_BYTE(reg, val) \ 113 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 114 115 116 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 117 /* a baud rate from the same group. So limiting to B is likely */ 118 /* best, although clone boards like the ABLE QHV allow all settings. */ 119 120 static struct speedtab dhuspeedtab[] = { 121 { 0, 0 }, /* Groups */ 122 { 50, DHU_LPR_B50 }, /* A */ 123 { 75, DHU_LPR_B75 }, /* B */ 124 { 110, DHU_LPR_B110 }, /* A and B */ 125 { 134, DHU_LPR_B134 }, /* A and B */ 126 { 150, DHU_LPR_B150 }, /* B */ 127 { 300, DHU_LPR_B300 }, /* A and B */ 128 { 600, DHU_LPR_B600 }, /* A and B */ 129 { 1200, DHU_LPR_B1200 }, /* A and B */ 130 { 1800, DHU_LPR_B1800 }, /* B */ 131 { 2000, DHU_LPR_B2000 }, /* B */ 132 { 2400, DHU_LPR_B2400 }, /* A and B */ 133 { 4800, DHU_LPR_B4800 }, /* A and B */ 134 { 7200, DHU_LPR_B7200 }, /* A */ 135 { 9600, DHU_LPR_B9600 }, /* A and B */ 136 { 19200, DHU_LPR_B19200 }, /* B */ 137 { 38400, DHU_LPR_B38400 }, /* A */ 138 { -1, -1 } 139 }; 140 141 static int dhu_match __P((struct device *, struct cfdata *, void *)); 142 static void dhu_attach __P((struct device *, struct device *, void *)); 143 static void dhurint __P((void *)); 144 static void dhuxint __P((void *)); 145 static void dhustart __P((struct tty *)); 146 static int dhuparam __P((struct tty *, struct termios *)); 147 static int dhuiflow __P((struct tty *, int)); 148 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 149 150 struct cfattach dhu_ca = { 151 sizeof(struct dhu_softc), dhu_match, dhu_attach 152 }; 153 154 dev_type_open(dhuopen); 155 dev_type_close(dhuclose); 156 dev_type_read(dhuread); 157 dev_type_write(dhuwrite); 158 dev_type_ioctl(dhuioctl); 159 dev_type_stop(dhustop); 160 dev_type_tty(dhutty); 161 dev_type_poll(dhupoll); 162 163 const struct cdevsw dhu_cdevsw = { 164 dhuopen, dhuclose, dhuread, dhuwrite, dhuioctl, 165 dhustop, dhutty, dhupoll, nommap, D_TTY 166 }; 167 168 /* Autoconfig handles: setup the controller to interrupt, */ 169 /* then complete the housecleaning for full operation */ 170 171 static int 172 dhu_match(parent, cf, aux) 173 struct device *parent; 174 struct cfdata *cf; 175 void *aux; 176 { 177 struct uba_attach_args *ua = aux; 178 int n; 179 180 /* Reset controller to initialize, enable TX/RX interrupts */ 181 /* to catch floating vector info elsewhere when completed */ 182 183 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 184 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 185 186 /* Now wait up to 3 seconds for self-test to complete. */ 187 188 for (n = 0; n < 300; n++) { 189 DELAY(10000); 190 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 191 DHU_CSR_MASTER_RESET) == 0) 192 break; 193 } 194 195 /* If the RESET did not clear after 3 seconds, */ 196 /* the controller must be broken. */ 197 198 if (n >= 300) 199 return 0; 200 201 /* Check whether diagnostic run has signalled a failure. */ 202 203 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 204 DHU_CSR_DIAG_FAIL) != 0) 205 return 0; 206 207 return 1; 208 } 209 210 static void 211 dhu_attach(parent, self, aux) 212 struct device *parent, *self; 213 void *aux; 214 { 215 struct dhu_softc *sc = (void *)self; 216 struct uba_attach_args *ua = aux; 217 unsigned c; 218 int n, i; 219 220 sc->sc_iot = ua->ua_iot; 221 sc->sc_ioh = ua->ua_ioh; 222 sc->sc_dmat = ua->ua_dmat; 223 /* Process the 8 bytes of diagnostic info put into */ 224 /* the FIFO following the master reset operation. */ 225 226 printf("\n%s:", self->dv_xname); 227 for (n = 0; n < 8; n++) { 228 c = DHU_READ_WORD(DHU_UBA_RBUF); 229 230 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 231 if ((c&0200) == 0000) 232 printf(" rom(%d) version %d", 233 ((c>>1)&01), ((c>>2)&037)); 234 else if (((c>>2)&07) != 0) 235 printf(" diag-error(proc%d)=%x", 236 ((c>>1)&01), ((c>>2)&07)); 237 } 238 } 239 240 c = DHU_READ_WORD(DHU_UBA_STAT); 241 242 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 243 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 244 245 for (i = 0; i < sc->sc_type; i++) { 246 struct tty *tp; 247 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 248 sc->sc_dhu[i].dhu_state = STATE_IDLE; 249 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 250 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 251 &sc->sc_dhu[i].dhu_dmah); 252 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 253 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 254 255 } 256 257 /* Now establish RX & TX interrupt handlers */ 258 259 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 260 dhurint, sc, &sc->sc_rintrcnt); 261 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 262 dhuxint, sc, &sc->sc_tintrcnt); 263 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 264 sc->sc_dev.dv_xname, "rintr"); 265 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 266 sc->sc_dev.dv_xname, "tintr"); 267 } 268 269 /* Receiver Interrupt */ 270 271 static void 272 dhurint(arg) 273 void *arg; 274 { 275 struct dhu_softc *sc = arg; 276 struct tty *tp; 277 int cc, line; 278 unsigned c, delta; 279 int overrun = 0; 280 281 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 282 283 /* Ignore diagnostic FIFO entries. */ 284 285 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 286 continue; 287 288 cc = c & 0xFF; 289 line = DHU_LINE(c>>8); 290 tp = sc->sc_dhu[line].dhu_tty; 291 292 /* LINK.TYPE is set so we get modem control FIFO entries */ 293 294 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 295 c = (c << 8); 296 /* Do MDMBUF flow control, wakeup sleeping opens */ 297 if (c & DHU_STAT_DCD) { 298 if (!(tp->t_state & TS_CARR_ON)) 299 (void)(*tp->t_linesw->l_modem)(tp, 1); 300 } 301 else if ((tp->t_state & TS_CARR_ON) && 302 (*tp->t_linesw->l_modem)(tp, 0) == 0) 303 (void) dhumctl(sc, line, 0, DMSET); 304 305 /* Do CRTSCTS flow control */ 306 delta = c ^ sc->sc_dhu[line].dhu_modem; 307 sc->sc_dhu[line].dhu_modem = c; 308 if ((delta & DHU_STAT_CTS) && 309 (tp->t_state & TS_ISOPEN) && 310 (tp->t_cflag & CRTSCTS)) { 311 if (c & DHU_STAT_CTS) { 312 tp->t_state &= ~TS_TTSTOP; 313 ttstart(tp); 314 } else { 315 tp->t_state |= TS_TTSTOP; 316 dhustop(tp, 0); 317 } 318 } 319 continue; 320 } 321 322 if (!(tp->t_state & TS_ISOPEN)) { 323 wakeup((caddr_t)&tp->t_rawq); 324 continue; 325 } 326 327 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 328 log(LOG_WARNING, "%s: silo overflow, line %d\n", 329 sc->sc_dev.dv_xname, line); 330 overrun = 1; 331 } 332 /* A BREAK key will appear as a NULL with a framing error */ 333 if (c & DHU_RBUF_FRAMING_ERR) 334 cc |= TTY_FE; 335 if (c & DHU_RBUF_PARITY_ERR) 336 cc |= TTY_PE; 337 338 (*tp->t_linesw->l_rint)(cc, tp); 339 } 340 } 341 342 /* Transmitter Interrupt */ 343 344 static void 345 dhuxint(arg) 346 void *arg; 347 { 348 struct dhu_softc *sc = arg; 349 struct tty *tp; 350 int line; 351 352 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 353 354 tp = sc->sc_dhu[line].dhu_tty; 355 356 tp->t_state &= ~TS_BUSY; 357 if (tp->t_state & TS_FLUSH) 358 tp->t_state &= ~TS_FLUSH; 359 else { 360 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 361 sc->sc_dhu[line].dhu_cc -= 362 DHU_READ_WORD(DHU_UBA_TBUFCNT); 363 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 364 sc->sc_dhu[line].dhu_cc = 0; 365 } 366 367 sc->sc_dhu[line].dhu_state = STATE_IDLE; 368 369 (*tp->t_linesw->l_start)(tp); 370 } 371 372 int 373 dhuopen(dev, flag, mode, p) 374 dev_t dev; 375 int flag, mode; 376 struct proc *p; 377 { 378 struct tty *tp; 379 int unit, line; 380 struct dhu_softc *sc; 381 int s, error = 0; 382 383 unit = DHU_M2U(minor(dev)); 384 line = DHU_LINE(minor(dev)); 385 386 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 387 return (ENXIO); 388 389 sc = dhu_cd.cd_devs[unit]; 390 391 if (line >= sc->sc_type) 392 return ENXIO; 393 394 s = spltty(); 395 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 396 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 397 (void) splx(s); 398 399 tp = sc->sc_dhu[line].dhu_tty; 400 401 tp->t_oproc = dhustart; 402 tp->t_param = dhuparam; 403 tp->t_hwiflow = dhuiflow; 404 tp->t_dev = dev; 405 if ((tp->t_state & TS_ISOPEN) == 0) { 406 ttychars(tp); 407 if (tp->t_ispeed == 0) { 408 tp->t_iflag = TTYDEF_IFLAG; 409 tp->t_oflag = TTYDEF_OFLAG; 410 tp->t_cflag = TTYDEF_CFLAG; 411 tp->t_lflag = TTYDEF_LFLAG; 412 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 413 } 414 (void) dhuparam(tp, &tp->t_termios); 415 ttsetwater(tp); 416 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 417 return (EBUSY); 418 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 419 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 420 tp->t_state |= TS_CARR_ON; 421 s = spltty(); 422 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 423 !(tp->t_state & TS_CARR_ON)) { 424 tp->t_wopen++; 425 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 426 TTIPRI | PCATCH, ttopen, 0); 427 tp->t_wopen--; 428 if (error) 429 break; 430 } 431 (void) splx(s); 432 if (error) 433 return (error); 434 return ((*tp->t_linesw->l_open)(dev, tp)); 435 } 436 437 /*ARGSUSED*/ 438 int 439 dhuclose(dev, flag, mode, p) 440 dev_t dev; 441 int flag, mode; 442 struct proc *p; 443 { 444 struct tty *tp; 445 int unit, line; 446 struct dhu_softc *sc; 447 448 unit = DHU_M2U(minor(dev)); 449 line = DHU_LINE(minor(dev)); 450 451 sc = dhu_cd.cd_devs[unit]; 452 453 tp = sc->sc_dhu[line].dhu_tty; 454 455 (*tp->t_linesw->l_close)(tp, flag); 456 457 /* Make sure a BREAK state is not left enabled. */ 458 459 (void) dhumctl(sc, line, DML_BRK, DMBIC); 460 461 /* Do a hangup if so required. */ 462 463 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 464 !(tp->t_state & TS_ISOPEN)) 465 (void) dhumctl(sc, line, 0, DMSET); 466 467 return (ttyclose(tp)); 468 } 469 470 int 471 dhuread(dev, uio, flag) 472 dev_t dev; 473 struct uio *uio; 474 int flag; 475 { 476 struct dhu_softc *sc; 477 struct tty *tp; 478 479 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 480 481 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 482 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 483 } 484 485 int 486 dhuwrite(dev, uio, flag) 487 dev_t dev; 488 struct uio *uio; 489 int flag; 490 { 491 struct dhu_softc *sc; 492 struct tty *tp; 493 494 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 495 496 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 497 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 498 } 499 500 int 501 dhupoll(dev, events, p) 502 dev_t dev; 503 int events; 504 struct proc *p; 505 { 506 struct dhu_softc *sc; 507 struct tty *tp; 508 509 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 510 511 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 512 return ((*tp->t_linesw->l_poll)(tp, events, p)); 513 } 514 515 /*ARGSUSED*/ 516 int 517 dhuioctl(dev, cmd, data, flag, p) 518 dev_t dev; 519 u_long cmd; 520 caddr_t data; 521 int flag; 522 struct proc *p; 523 { 524 struct dhu_softc *sc; 525 struct tty *tp; 526 int unit, line; 527 int error; 528 529 unit = DHU_M2U(minor(dev)); 530 line = DHU_LINE(minor(dev)); 531 sc = dhu_cd.cd_devs[unit]; 532 tp = sc->sc_dhu[line].dhu_tty; 533 534 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 535 if (error != EPASSTHROUGH) 536 return (error); 537 538 error = ttioctl(tp, cmd, data, flag, p); 539 if (error != EPASSTHROUGH) 540 return (error); 541 542 switch (cmd) { 543 544 case TIOCSBRK: 545 (void) dhumctl(sc, line, DML_BRK, DMBIS); 546 break; 547 548 case TIOCCBRK: 549 (void) dhumctl(sc, line, DML_BRK, DMBIC); 550 break; 551 552 case TIOCSDTR: 553 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 554 break; 555 556 case TIOCCDTR: 557 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 558 break; 559 560 case TIOCMSET: 561 (void) dhumctl(sc, line, *(int *)data, DMSET); 562 break; 563 564 case TIOCMBIS: 565 (void) dhumctl(sc, line, *(int *)data, DMBIS); 566 break; 567 568 case TIOCMBIC: 569 (void) dhumctl(sc, line, *(int *)data, DMBIC); 570 break; 571 572 case TIOCMGET: 573 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 574 break; 575 576 default: 577 return (EPASSTHROUGH); 578 } 579 return (0); 580 } 581 582 struct tty * 583 dhutty(dev) 584 dev_t dev; 585 { 586 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 587 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 588 return (tp); 589 } 590 591 /*ARGSUSED*/ 592 void 593 dhustop(tp, flag) 594 struct tty *tp; 595 int flag; 596 { 597 struct dhu_softc *sc; 598 int line; 599 int s; 600 601 s = spltty(); 602 603 if (tp->t_state & TS_BUSY) { 604 605 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 606 line = DHU_LINE(minor(tp->t_dev)); 607 608 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 609 610 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 611 612 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 613 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 614 DHU_READ_WORD(DHU_UBA_LNCTRL) | 615 DHU_LNCTRL_DMA_ABORT); 616 } 617 618 if (!(tp->t_state & TS_TTSTOP)) 619 tp->t_state |= TS_FLUSH; 620 } 621 (void) splx(s); 622 } 623 624 static void 625 dhustart(tp) 626 struct tty *tp; 627 { 628 struct dhu_softc *sc; 629 int line, cc; 630 int addr; 631 int s; 632 633 s = spltty(); 634 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 635 goto out; 636 if (tp->t_outq.c_cc <= tp->t_lowat) { 637 if (tp->t_state & TS_ASLEEP) { 638 tp->t_state &= ~TS_ASLEEP; 639 wakeup((caddr_t)&tp->t_outq); 640 } 641 selwakeup(&tp->t_wsel); 642 } 643 if (tp->t_outq.c_cc == 0) 644 goto out; 645 cc = ndqb(&tp->t_outq, 0); 646 if (cc == 0) 647 goto out; 648 649 tp->t_state |= TS_BUSY; 650 651 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 652 653 line = DHU_LINE(minor(tp->t_dev)); 654 655 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 656 657 sc->sc_dhu[line].dhu_cc = cc; 658 659 if (cc == 1) { 660 661 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 662 663 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 664 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 665 666 } else { 667 668 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 669 670 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 671 (tp->t_outq.c_cf - tp->t_outq.c_cs); 672 673 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 674 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 675 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 676 DHU_TBUFAD2_TX_ENABLE); 677 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 678 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 679 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 680 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 681 } 682 out: 683 (void) splx(s); 684 return; 685 } 686 687 static int 688 dhuparam(tp, t) 689 struct tty *tp; 690 struct termios *t; 691 { 692 struct dhu_softc *sc; 693 int cflag = t->c_cflag; 694 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 695 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 696 unsigned lpr, lnctrl; 697 int unit, line; 698 int s; 699 700 unit = DHU_M2U(minor(tp->t_dev)); 701 line = DHU_LINE(minor(tp->t_dev)); 702 703 sc = dhu_cd.cd_devs[unit]; 704 705 /* check requested parameters */ 706 if (ospeed < 0 || ispeed < 0) 707 return (EINVAL); 708 709 tp->t_ispeed = t->c_ispeed; 710 tp->t_ospeed = t->c_ospeed; 711 tp->t_cflag = cflag; 712 713 if (ospeed == 0) { 714 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 715 return (0); 716 } 717 718 s = spltty(); 719 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 720 721 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 722 723 switch (cflag & CSIZE) { 724 725 case CS5: 726 lpr |= DHU_LPR_5_BIT_CHAR; 727 break; 728 729 case CS6: 730 lpr |= DHU_LPR_6_BIT_CHAR; 731 break; 732 733 case CS7: 734 lpr |= DHU_LPR_7_BIT_CHAR; 735 break; 736 737 default: 738 lpr |= DHU_LPR_8_BIT_CHAR; 739 break; 740 } 741 742 if (cflag & PARENB) 743 lpr |= DHU_LPR_PARENB; 744 if (!(cflag & PARODD)) 745 lpr |= DHU_LPR_EPAR; 746 if (cflag & CSTOPB) 747 lpr |= DHU_LPR_2_STOP; 748 749 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 750 751 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 752 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 753 754 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 755 756 /* Setting LINK.TYPE enables modem signal change interrupts. */ 757 758 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 759 760 /* Enable the auto XON/XOFF feature on the controller */ 761 762 if (t->c_iflag & IXON) 763 lnctrl |= DHU_LNCTRL_OAUTO; 764 else 765 lnctrl &= ~DHU_LNCTRL_OAUTO; 766 767 if (t->c_iflag & IXOFF) 768 lnctrl |= DHU_LNCTRL_IAUTO; 769 else 770 lnctrl &= ~DHU_LNCTRL_IAUTO; 771 772 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 773 774 (void) splx(s); 775 return (0); 776 } 777 778 static int 779 dhuiflow(tp, flag) 780 struct tty *tp; 781 int flag; 782 { 783 struct dhu_softc *sc; 784 int line = DHU_LINE(minor(tp->t_dev)); 785 786 if (tp->t_cflag & CRTSCTS) { 787 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 788 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 789 return (1); 790 } 791 return (0); 792 } 793 794 static unsigned 795 dhumctl(sc, line, bits, how) 796 struct dhu_softc *sc; 797 int line, bits, how; 798 { 799 unsigned status; 800 unsigned lnctrl; 801 unsigned mbits; 802 int s; 803 804 s = spltty(); 805 806 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 807 808 mbits = 0; 809 810 /* external signals as seen from the port */ 811 812 status = DHU_READ_WORD(DHU_UBA_STAT); 813 814 if (status & DHU_STAT_CTS) 815 mbits |= DML_CTS; 816 817 if (status & DHU_STAT_DCD) 818 mbits |= DML_DCD; 819 820 if (status & DHU_STAT_DSR) 821 mbits |= DML_DSR; 822 823 if (status & DHU_STAT_RI) 824 mbits |= DML_RI; 825 826 /* internal signals/state delivered to port */ 827 828 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 829 830 if (lnctrl & DHU_LNCTRL_RTS) 831 mbits |= DML_RTS; 832 833 if (lnctrl & DHU_LNCTRL_DTR) 834 mbits |= DML_DTR; 835 836 if (lnctrl & DHU_LNCTRL_BREAK) 837 mbits |= DML_BRK; 838 839 switch (how) { 840 841 case DMSET: 842 mbits = bits; 843 break; 844 845 case DMBIS: 846 mbits |= bits; 847 break; 848 849 case DMBIC: 850 mbits &= ~bits; 851 break; 852 853 case DMGET: 854 (void) splx(s); 855 return (mbits); 856 } 857 858 if (mbits & DML_RTS) 859 lnctrl |= DHU_LNCTRL_RTS; 860 else 861 lnctrl &= ~DHU_LNCTRL_RTS; 862 863 if (mbits & DML_DTR) 864 lnctrl |= DHU_LNCTRL_DTR; 865 else 866 lnctrl &= ~DHU_LNCTRL_DTR; 867 868 if (mbits & DML_BRK) 869 lnctrl |= DHU_LNCTRL_BREAK; 870 else 871 lnctrl &= ~DHU_LNCTRL_BREAK; 872 873 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 874 875 (void) splx(s); 876 return (mbits); 877 } 878
Indexes created Mon Oct 20 11:09:49 GMT 2025