dhu.c revision 1.32
1 /* $NetBSD: dhu.c,v 1.32 2002/10/23 09:13:35 jdolecek Exp $ */ 2 /* 3 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.32 2002/10/23 09:13:35 jdolecek Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/ioctl.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/buf.h> 48 #include <sys/conf.h> 49 #include <sys/file.h> 50 #include <sys/uio.h> 51 #include <sys/kernel.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 55 #include <machine/bus.h> 56 #include <machine/scb.h> 57 58 #include <dev/qbus/ubavar.h> 59 60 #include <dev/qbus/dhureg.h> 61 62 #include "ioconf.h" 63 64 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 65 66 #define NDHULINE 16 67 68 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 69 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 70 71 struct dhu_softc { 72 struct device sc_dev; /* Device struct used by config */ 73 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 74 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 75 int sc_type; /* controller type, DHU or DHV */ 76 bus_space_tag_t sc_iot; 77 bus_space_handle_t sc_ioh; 78 bus_dma_tag_t sc_dmat; 79 struct { 80 struct tty *dhu_tty; /* what we work on */ 81 bus_dmamap_t dhu_dmah; 82 int dhu_state; /* to manage TX output status */ 83 short dhu_cc; /* character count on TX */ 84 short dhu_modem; /* modem bits state */ 85 } sc_dhu[NDHULINE]; 86 }; 87 88 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 89 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 90 91 #define STATE_IDLE 000 /* no current output in progress */ 92 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 93 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 94 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 95 96 /* Flags used to monitor modem bits, make them understood outside driver */ 97 98 #define DML_DTR TIOCM_DTR 99 #define DML_RTS TIOCM_RTS 100 #define DML_CTS TIOCM_CTS 101 #define DML_DCD TIOCM_CD 102 #define DML_RI TIOCM_RI 103 #define DML_DSR TIOCM_DSR 104 #define DML_BRK 0100000 /* no equivalent, we will mask */ 105 106 #define DHU_READ_WORD(reg) \ 107 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 108 #define DHU_WRITE_WORD(reg, val) \ 109 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 110 #define DHU_READ_BYTE(reg) \ 111 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 112 #define DHU_WRITE_BYTE(reg, val) \ 113 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 114 115 116 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 117 /* a baud rate from the same group. So limiting to B is likely */ 118 /* best, although clone boards like the ABLE QHV allow all settings. */ 119 120 static struct speedtab dhuspeedtab[] = { 121 { 0, 0 }, /* Groups */ 122 { 50, DHU_LPR_B50 }, /* A */ 123 { 75, DHU_LPR_B75 }, /* B */ 124 { 110, DHU_LPR_B110 }, /* A and B */ 125 { 134, DHU_LPR_B134 }, /* A and B */ 126 { 150, DHU_LPR_B150 }, /* B */ 127 { 300, DHU_LPR_B300 }, /* A and B */ 128 { 600, DHU_LPR_B600 }, /* A and B */ 129 { 1200, DHU_LPR_B1200 }, /* A and B */ 130 { 1800, DHU_LPR_B1800 }, /* B */ 131 { 2000, DHU_LPR_B2000 }, /* B */ 132 { 2400, DHU_LPR_B2400 }, /* A and B */ 133 { 4800, DHU_LPR_B4800 }, /* A and B */ 134 { 7200, DHU_LPR_B7200 }, /* A */ 135 { 9600, DHU_LPR_B9600 }, /* A and B */ 136 { 19200, DHU_LPR_B19200 }, /* B */ 137 { 38400, DHU_LPR_B38400 }, /* A */ 138 { -1, -1 } 139 }; 140 141 static int dhu_match __P((struct device *, struct cfdata *, void *)); 142 static void dhu_attach __P((struct device *, struct device *, void *)); 143 static void dhurint __P((void *)); 144 static void dhuxint __P((void *)); 145 static void dhustart __P((struct tty *)); 146 static int dhuparam __P((struct tty *, struct termios *)); 147 static int dhuiflow __P((struct tty *, int)); 148 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 149 150 CFATTACH_DECL(dhu, sizeof(struct dhu_softc), 151 dhu_match, dhu_attach, NULL, NULL); 152 153 dev_type_open(dhuopen); 154 dev_type_close(dhuclose); 155 dev_type_read(dhuread); 156 dev_type_write(dhuwrite); 157 dev_type_ioctl(dhuioctl); 158 dev_type_stop(dhustop); 159 dev_type_tty(dhutty); 160 dev_type_poll(dhupoll); 161 162 const struct cdevsw dhu_cdevsw = { 163 dhuopen, dhuclose, dhuread, dhuwrite, dhuioctl, 164 dhustop, dhutty, dhupoll, nommap, ttykqfilter, D_TTY 165 }; 166 167 /* Autoconfig handles: setup the controller to interrupt, */ 168 /* then complete the housecleaning for full operation */ 169 170 static int 171 dhu_match(parent, cf, aux) 172 struct device *parent; 173 struct cfdata *cf; 174 void *aux; 175 { 176 struct uba_attach_args *ua = aux; 177 int n; 178 179 /* Reset controller to initialize, enable TX/RX interrupts */ 180 /* to catch floating vector info elsewhere when completed */ 181 182 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 183 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 184 185 /* Now wait up to 3 seconds for self-test to complete. */ 186 187 for (n = 0; n < 300; n++) { 188 DELAY(10000); 189 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 190 DHU_CSR_MASTER_RESET) == 0) 191 break; 192 } 193 194 /* If the RESET did not clear after 3 seconds, */ 195 /* the controller must be broken. */ 196 197 if (n >= 300) 198 return 0; 199 200 /* Check whether diagnostic run has signalled a failure. */ 201 202 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 203 DHU_CSR_DIAG_FAIL) != 0) 204 return 0; 205 206 return 1; 207 } 208 209 static void 210 dhu_attach(parent, self, aux) 211 struct device *parent, *self; 212 void *aux; 213 { 214 struct dhu_softc *sc = (void *)self; 215 struct uba_attach_args *ua = aux; 216 unsigned c; 217 int n, i; 218 219 sc->sc_iot = ua->ua_iot; 220 sc->sc_ioh = ua->ua_ioh; 221 sc->sc_dmat = ua->ua_dmat; 222 /* Process the 8 bytes of diagnostic info put into */ 223 /* the FIFO following the master reset operation. */ 224 225 printf("\n%s:", self->dv_xname); 226 for (n = 0; n < 8; n++) { 227 c = DHU_READ_WORD(DHU_UBA_RBUF); 228 229 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 230 if ((c&0200) == 0000) 231 printf(" rom(%d) version %d", 232 ((c>>1)&01), ((c>>2)&037)); 233 else if (((c>>2)&07) != 0) 234 printf(" diag-error(proc%d)=%x", 235 ((c>>1)&01), ((c>>2)&07)); 236 } 237 } 238 239 c = DHU_READ_WORD(DHU_UBA_STAT); 240 241 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 242 printf("\n%s: DH%s-11\n", self->dv_xname, (c & DHU_STAT_DHU)?"U":"V"); 243 244 for (i = 0; i < sc->sc_type; i++) { 245 struct tty *tp; 246 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 247 sc->sc_dhu[i].dhu_state = STATE_IDLE; 248 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 249 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 250 &sc->sc_dhu[i].dhu_dmah); 251 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 252 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 253 254 } 255 256 /* Now establish RX & TX interrupt handlers */ 257 258 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 259 dhurint, sc, &sc->sc_rintrcnt); 260 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 261 dhuxint, sc, &sc->sc_tintrcnt); 262 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 263 sc->sc_dev.dv_xname, "rintr"); 264 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 265 sc->sc_dev.dv_xname, "tintr"); 266 } 267 268 /* Receiver Interrupt */ 269 270 static void 271 dhurint(arg) 272 void *arg; 273 { 274 struct dhu_softc *sc = arg; 275 struct tty *tp; 276 int cc, line; 277 unsigned c, delta; 278 int overrun = 0; 279 280 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 281 282 /* Ignore diagnostic FIFO entries. */ 283 284 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 285 continue; 286 287 cc = c & 0xFF; 288 line = DHU_LINE(c>>8); 289 tp = sc->sc_dhu[line].dhu_tty; 290 291 /* LINK.TYPE is set so we get modem control FIFO entries */ 292 293 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 294 c = (c << 8); 295 /* Do MDMBUF flow control, wakeup sleeping opens */ 296 if (c & DHU_STAT_DCD) { 297 if (!(tp->t_state & TS_CARR_ON)) 298 (void)(*tp->t_linesw->l_modem)(tp, 1); 299 } 300 else if ((tp->t_state & TS_CARR_ON) && 301 (*tp->t_linesw->l_modem)(tp, 0) == 0) 302 (void) dhumctl(sc, line, 0, DMSET); 303 304 /* Do CRTSCTS flow control */ 305 delta = c ^ sc->sc_dhu[line].dhu_modem; 306 sc->sc_dhu[line].dhu_modem = c; 307 if ((delta & DHU_STAT_CTS) && 308 (tp->t_state & TS_ISOPEN) && 309 (tp->t_cflag & CRTSCTS)) { 310 if (c & DHU_STAT_CTS) { 311 tp->t_state &= ~TS_TTSTOP; 312 ttstart(tp); 313 } else { 314 tp->t_state |= TS_TTSTOP; 315 dhustop(tp, 0); 316 } 317 } 318 continue; 319 } 320 321 if (!(tp->t_state & TS_ISOPEN)) { 322 wakeup((caddr_t)&tp->t_rawq); 323 continue; 324 } 325 326 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 327 log(LOG_WARNING, "%s: silo overflow, line %d\n", 328 sc->sc_dev.dv_xname, line); 329 overrun = 1; 330 } 331 /* A BREAK key will appear as a NULL with a framing error */ 332 if (c & DHU_RBUF_FRAMING_ERR) 333 cc |= TTY_FE; 334 if (c & DHU_RBUF_PARITY_ERR) 335 cc |= TTY_PE; 336 337 (*tp->t_linesw->l_rint)(cc, tp); 338 } 339 } 340 341 /* Transmitter Interrupt */ 342 343 static void 344 dhuxint(arg) 345 void *arg; 346 { 347 struct dhu_softc *sc = arg; 348 struct tty *tp; 349 int line; 350 351 line = DHU_LINE(DHU_READ_BYTE(DHU_UBA_CSR_HI)); 352 353 tp = sc->sc_dhu[line].dhu_tty; 354 355 tp->t_state &= ~TS_BUSY; 356 if (tp->t_state & TS_FLUSH) 357 tp->t_state &= ~TS_FLUSH; 358 else { 359 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 360 sc->sc_dhu[line].dhu_cc -= 361 DHU_READ_WORD(DHU_UBA_TBUFCNT); 362 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 363 sc->sc_dhu[line].dhu_cc = 0; 364 } 365 366 sc->sc_dhu[line].dhu_state = STATE_IDLE; 367 368 (*tp->t_linesw->l_start)(tp); 369 } 370 371 int 372 dhuopen(dev, flag, mode, p) 373 dev_t dev; 374 int flag, mode; 375 struct proc *p; 376 { 377 struct tty *tp; 378 int unit, line; 379 struct dhu_softc *sc; 380 int s, error = 0; 381 382 unit = DHU_M2U(minor(dev)); 383 line = DHU_LINE(minor(dev)); 384 385 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 386 return (ENXIO); 387 388 sc = dhu_cd.cd_devs[unit]; 389 390 if (line >= sc->sc_type) 391 return ENXIO; 392 393 s = spltty(); 394 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 395 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 396 (void) splx(s); 397 398 tp = sc->sc_dhu[line].dhu_tty; 399 400 tp->t_oproc = dhustart; 401 tp->t_param = dhuparam; 402 tp->t_hwiflow = dhuiflow; 403 tp->t_dev = dev; 404 if ((tp->t_state & TS_ISOPEN) == 0) { 405 ttychars(tp); 406 if (tp->t_ispeed == 0) { 407 tp->t_iflag = TTYDEF_IFLAG; 408 tp->t_oflag = TTYDEF_OFLAG; 409 tp->t_cflag = TTYDEF_CFLAG; 410 tp->t_lflag = TTYDEF_LFLAG; 411 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 412 } 413 (void) dhuparam(tp, &tp->t_termios); 414 ttsetwater(tp); 415 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 416 return (EBUSY); 417 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 418 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 419 tp->t_state |= TS_CARR_ON; 420 s = spltty(); 421 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 422 !(tp->t_state & TS_CARR_ON)) { 423 tp->t_wopen++; 424 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 425 TTIPRI | PCATCH, ttopen, 0); 426 tp->t_wopen--; 427 if (error) 428 break; 429 } 430 (void) splx(s); 431 if (error) 432 return (error); 433 return ((*tp->t_linesw->l_open)(dev, tp)); 434 } 435 436 /*ARGSUSED*/ 437 int 438 dhuclose(dev, flag, mode, p) 439 dev_t dev; 440 int flag, mode; 441 struct proc *p; 442 { 443 struct tty *tp; 444 int unit, line; 445 struct dhu_softc *sc; 446 447 unit = DHU_M2U(minor(dev)); 448 line = DHU_LINE(minor(dev)); 449 450 sc = dhu_cd.cd_devs[unit]; 451 452 tp = sc->sc_dhu[line].dhu_tty; 453 454 (*tp->t_linesw->l_close)(tp, flag); 455 456 /* Make sure a BREAK state is not left enabled. */ 457 458 (void) dhumctl(sc, line, DML_BRK, DMBIC); 459 460 /* Do a hangup if so required. */ 461 462 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 463 !(tp->t_state & TS_ISOPEN)) 464 (void) dhumctl(sc, line, 0, DMSET); 465 466 return (ttyclose(tp)); 467 } 468 469 int 470 dhuread(dev, uio, flag) 471 dev_t dev; 472 struct uio *uio; 473 int flag; 474 { 475 struct dhu_softc *sc; 476 struct tty *tp; 477 478 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 479 480 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 481 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 482 } 483 484 int 485 dhuwrite(dev, uio, flag) 486 dev_t dev; 487 struct uio *uio; 488 int flag; 489 { 490 struct dhu_softc *sc; 491 struct tty *tp; 492 493 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 494 495 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 496 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 497 } 498 499 int 500 dhupoll(dev, events, p) 501 dev_t dev; 502 int events; 503 struct proc *p; 504 { 505 struct dhu_softc *sc; 506 struct tty *tp; 507 508 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 509 510 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 511 return ((*tp->t_linesw->l_poll)(tp, events, p)); 512 } 513 514 /*ARGSUSED*/ 515 int 516 dhuioctl(dev, cmd, data, flag, p) 517 dev_t dev; 518 u_long cmd; 519 caddr_t data; 520 int flag; 521 struct proc *p; 522 { 523 struct dhu_softc *sc; 524 struct tty *tp; 525 int unit, line; 526 int error; 527 528 unit = DHU_M2U(minor(dev)); 529 line = DHU_LINE(minor(dev)); 530 sc = dhu_cd.cd_devs[unit]; 531 tp = sc->sc_dhu[line].dhu_tty; 532 533 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 534 if (error != EPASSTHROUGH) 535 return (error); 536 537 error = ttioctl(tp, cmd, data, flag, p); 538 if (error != EPASSTHROUGH) 539 return (error); 540 541 switch (cmd) { 542 543 case TIOCSBRK: 544 (void) dhumctl(sc, line, DML_BRK, DMBIS); 545 break; 546 547 case TIOCCBRK: 548 (void) dhumctl(sc, line, DML_BRK, DMBIC); 549 break; 550 551 case TIOCSDTR: 552 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 553 break; 554 555 case TIOCCDTR: 556 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 557 break; 558 559 case TIOCMSET: 560 (void) dhumctl(sc, line, *(int *)data, DMSET); 561 break; 562 563 case TIOCMBIS: 564 (void) dhumctl(sc, line, *(int *)data, DMBIS); 565 break; 566 567 case TIOCMBIC: 568 (void) dhumctl(sc, line, *(int *)data, DMBIC); 569 break; 570 571 case TIOCMGET: 572 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 573 break; 574 575 default: 576 return (EPASSTHROUGH); 577 } 578 return (0); 579 } 580 581 struct tty * 582 dhutty(dev) 583 dev_t dev; 584 { 585 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 586 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 587 return (tp); 588 } 589 590 /*ARGSUSED*/ 591 void 592 dhustop(tp, flag) 593 struct tty *tp; 594 int flag; 595 { 596 struct dhu_softc *sc; 597 int line; 598 int s; 599 600 s = spltty(); 601 602 if (tp->t_state & TS_BUSY) { 603 604 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 605 line = DHU_LINE(minor(tp->t_dev)); 606 607 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 608 609 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 610 611 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 612 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 613 DHU_READ_WORD(DHU_UBA_LNCTRL) | 614 DHU_LNCTRL_DMA_ABORT); 615 } 616 617 if (!(tp->t_state & TS_TTSTOP)) 618 tp->t_state |= TS_FLUSH; 619 } 620 (void) splx(s); 621 } 622 623 static void 624 dhustart(tp) 625 struct tty *tp; 626 { 627 struct dhu_softc *sc; 628 int line, cc; 629 int addr; 630 int s; 631 632 s = spltty(); 633 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 634 goto out; 635 if (tp->t_outq.c_cc <= tp->t_lowat) { 636 if (tp->t_state & TS_ASLEEP) { 637 tp->t_state &= ~TS_ASLEEP; 638 wakeup((caddr_t)&tp->t_outq); 639 } 640 selwakeup(&tp->t_wsel); 641 } 642 if (tp->t_outq.c_cc == 0) 643 goto out; 644 cc = ndqb(&tp->t_outq, 0); 645 if (cc == 0) 646 goto out; 647 648 tp->t_state |= TS_BUSY; 649 650 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 651 652 line = DHU_LINE(minor(tp->t_dev)); 653 654 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 655 656 sc->sc_dhu[line].dhu_cc = cc; 657 658 if (cc == 1) { 659 660 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 661 662 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 663 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 664 665 } else { 666 667 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 668 669 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 670 (tp->t_outq.c_cf - tp->t_outq.c_cs); 671 672 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 673 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 674 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 675 DHU_TBUFAD2_TX_ENABLE); 676 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 677 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 678 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 679 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 680 } 681 out: 682 (void) splx(s); 683 return; 684 } 685 686 static int 687 dhuparam(tp, t) 688 struct tty *tp; 689 struct termios *t; 690 { 691 struct dhu_softc *sc; 692 int cflag = t->c_cflag; 693 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 694 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 695 unsigned lpr, lnctrl; 696 int unit, line; 697 int s; 698 699 unit = DHU_M2U(minor(tp->t_dev)); 700 line = DHU_LINE(minor(tp->t_dev)); 701 702 sc = dhu_cd.cd_devs[unit]; 703 704 /* check requested parameters */ 705 if (ospeed < 0 || ispeed < 0) 706 return (EINVAL); 707 708 tp->t_ispeed = t->c_ispeed; 709 tp->t_ospeed = t->c_ospeed; 710 tp->t_cflag = cflag; 711 712 if (ospeed == 0) { 713 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 714 return (0); 715 } 716 717 s = spltty(); 718 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 719 720 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 721 722 switch (cflag & CSIZE) { 723 724 case CS5: 725 lpr |= DHU_LPR_5_BIT_CHAR; 726 break; 727 728 case CS6: 729 lpr |= DHU_LPR_6_BIT_CHAR; 730 break; 731 732 case CS7: 733 lpr |= DHU_LPR_7_BIT_CHAR; 734 break; 735 736 default: 737 lpr |= DHU_LPR_8_BIT_CHAR; 738 break; 739 } 740 741 if (cflag & PARENB) 742 lpr |= DHU_LPR_PARENB; 743 if (!(cflag & PARODD)) 744 lpr |= DHU_LPR_EPAR; 745 if (cflag & CSTOPB) 746 lpr |= DHU_LPR_2_STOP; 747 748 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 749 750 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 751 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 752 753 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 754 755 /* Setting LINK.TYPE enables modem signal change interrupts. */ 756 757 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 758 759 /* Enable the auto XON/XOFF feature on the controller */ 760 761 if (t->c_iflag & IXON) 762 lnctrl |= DHU_LNCTRL_OAUTO; 763 else 764 lnctrl &= ~DHU_LNCTRL_OAUTO; 765 766 if (t->c_iflag & IXOFF) 767 lnctrl |= DHU_LNCTRL_IAUTO; 768 else 769 lnctrl &= ~DHU_LNCTRL_IAUTO; 770 771 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 772 773 (void) splx(s); 774 return (0); 775 } 776 777 static int 778 dhuiflow(tp, flag) 779 struct tty *tp; 780 int flag; 781 { 782 struct dhu_softc *sc; 783 int line = DHU_LINE(minor(tp->t_dev)); 784 785 if (tp->t_cflag & CRTSCTS) { 786 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 787 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 788 return (1); 789 } 790 return (0); 791 } 792 793 static unsigned 794 dhumctl(sc, line, bits, how) 795 struct dhu_softc *sc; 796 int line, bits, how; 797 { 798 unsigned status; 799 unsigned lnctrl; 800 unsigned mbits; 801 int s; 802 803 s = spltty(); 804 805 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 806 807 mbits = 0; 808 809 /* external signals as seen from the port */ 810 811 status = DHU_READ_WORD(DHU_UBA_STAT); 812 813 if (status & DHU_STAT_CTS) 814 mbits |= DML_CTS; 815 816 if (status & DHU_STAT_DCD) 817 mbits |= DML_DCD; 818 819 if (status & DHU_STAT_DSR) 820 mbits |= DML_DSR; 821 822 if (status & DHU_STAT_RI) 823 mbits |= DML_RI; 824 825 /* internal signals/state delivered to port */ 826 827 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 828 829 if (lnctrl & DHU_LNCTRL_RTS) 830 mbits |= DML_RTS; 831 832 if (lnctrl & DHU_LNCTRL_DTR) 833 mbits |= DML_DTR; 834 835 if (lnctrl & DHU_LNCTRL_BREAK) 836 mbits |= DML_BRK; 837 838 switch (how) { 839 840 case DMSET: 841 mbits = bits; 842 break; 843 844 case DMBIS: 845 mbits |= bits; 846 break; 847 848 case DMBIC: 849 mbits &= ~bits; 850 break; 851 852 case DMGET: 853 (void) splx(s); 854 return (mbits); 855 } 856 857 if (mbits & DML_RTS) 858 lnctrl |= DHU_LNCTRL_RTS; 859 else 860 lnctrl &= ~DHU_LNCTRL_RTS; 861 862 if (mbits & DML_DTR) 863 lnctrl |= DHU_LNCTRL_DTR; 864 else 865 lnctrl &= ~DHU_LNCTRL_DTR; 866 867 if (mbits & DML_BRK) 868 lnctrl |= DHU_LNCTRL_BREAK; 869 else 870 lnctrl &= ~DHU_LNCTRL_BREAK; 871 872 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 873 874 (void) splx(s); 875 return (mbits); 876 } 877
Indexes created Tue Sep 23 02:09:52 GMT 2025