dhu.c revision 1.33
1 /* $NetBSD: dhu.c,v 1.33 2003/04/06 15:45:11 ragge Exp $ */ 2 /* 3 * Copyright (c) 2003, Hugh Graham. 4 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * Ralph Campbell and Rick Macklem. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the University of 22 * California, Berkeley and its contributors. 23 * 4. Neither the name of the University nor the names of its contributors 24 * may be used to endorse or promote products derived from this software 25 * without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.33 2003/04/06 15:45:11 ragge Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/ioctl.h> 46 #include <sys/tty.h> 47 #include <sys/proc.h> 48 #include <sys/buf.h> 49 #include <sys/conf.h> 50 #include <sys/file.h> 51 #include <sys/uio.h> 52 #include <sys/kernel.h> 53 #include <sys/syslog.h> 54 #include <sys/device.h> 55 56 #include <machine/bus.h> 57 #include <machine/scb.h> 58 59 #include <dev/qbus/ubavar.h> 60 61 #include <dev/qbus/dhureg.h> 62 63 #include "ioconf.h" 64 65 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 66 67 #define NDHULINE 16 68 69 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 70 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 71 72 struct dhu_softc { 73 struct device sc_dev; /* Device struct used by config */ 74 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 75 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 76 int sc_type; /* controller type, DHU or DHV */ 77 int sc_lines; /* number of lines */ 78 bus_space_tag_t sc_iot; 79 bus_space_handle_t sc_ioh; 80 bus_dma_tag_t sc_dmat; 81 struct { 82 struct tty *dhu_tty; /* what we work on */ 83 bus_dmamap_t dhu_dmah; 84 int dhu_state; /* to manage TX output status */ 85 short dhu_cc; /* character count on TX */ 86 short dhu_modem; /* modem bits state */ 87 } sc_dhu[NDHULINE]; 88 }; 89 90 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 91 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 92 93 #define STATE_IDLE 000 /* no current output in progress */ 94 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 95 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 96 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 97 98 /* Flags used to monitor modem bits, make them understood outside driver */ 99 100 #define DML_DTR TIOCM_DTR 101 #define DML_RTS TIOCM_RTS 102 #define DML_CTS TIOCM_CTS 103 #define DML_DCD TIOCM_CD 104 #define DML_RI TIOCM_RI 105 #define DML_DSR TIOCM_DSR 106 #define DML_BRK 0100000 /* no equivalent, we will mask */ 107 108 #define DHU_READ_WORD(reg) \ 109 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 110 #define DHU_WRITE_WORD(reg, val) \ 111 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 112 #define DHU_READ_BYTE(reg) \ 113 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 114 #define DHU_WRITE_BYTE(reg, val) \ 115 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 116 117 118 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 119 /* a baud rate from the same group. So limiting to B is likely */ 120 /* best, although clone boards like the ABLE QHV allow all settings. */ 121 122 static struct speedtab dhuspeedtab[] = { 123 { 0, 0 }, /* Groups */ 124 { 50, DHU_LPR_B50 }, /* A */ 125 { 75, DHU_LPR_B75 }, /* B */ 126 { 110, DHU_LPR_B110 }, /* A and B */ 127 { 134, DHU_LPR_B134 }, /* A and B */ 128 { 150, DHU_LPR_B150 }, /* B */ 129 { 300, DHU_LPR_B300 }, /* A and B */ 130 { 600, DHU_LPR_B600 }, /* A and B */ 131 { 1200, DHU_LPR_B1200 }, /* A and B */ 132 { 1800, DHU_LPR_B1800 }, /* B */ 133 { 2000, DHU_LPR_B2000 }, /* B */ 134 { 2400, DHU_LPR_B2400 }, /* A and B */ 135 { 4800, DHU_LPR_B4800 }, /* A and B */ 136 { 7200, DHU_LPR_B7200 }, /* A */ 137 { 9600, DHU_LPR_B9600 }, /* A and B */ 138 { 19200, DHU_LPR_B19200 }, /* B */ 139 { 38400, DHU_LPR_B38400 }, /* A */ 140 { -1, -1 } 141 }; 142 143 static int dhu_match __P((struct device *, struct cfdata *, void *)); 144 static void dhu_attach __P((struct device *, struct device *, void *)); 145 static void dhurint __P((void *)); 146 static void dhuxint __P((void *)); 147 static void dhustart __P((struct tty *)); 148 static int dhuparam __P((struct tty *, struct termios *)); 149 static int dhuiflow __P((struct tty *, int)); 150 static unsigned dhumctl __P((struct dhu_softc *,int, int, int)); 151 152 CFATTACH_DECL(dhu, sizeof(struct dhu_softc), 153 dhu_match, dhu_attach, NULL, NULL); 154 155 dev_type_open(dhuopen); 156 dev_type_close(dhuclose); 157 dev_type_read(dhuread); 158 dev_type_write(dhuwrite); 159 dev_type_ioctl(dhuioctl); 160 dev_type_stop(dhustop); 161 dev_type_tty(dhutty); 162 dev_type_poll(dhupoll); 163 164 const struct cdevsw dhu_cdevsw = { 165 dhuopen, dhuclose, dhuread, dhuwrite, dhuioctl, 166 dhustop, dhutty, dhupoll, nommap, ttykqfilter, D_TTY 167 }; 168 169 /* Autoconfig handles: setup the controller to interrupt, */ 170 /* then complete the housecleaning for full operation */ 171 172 static int 173 dhu_match(parent, cf, aux) 174 struct device *parent; 175 struct cfdata *cf; 176 void *aux; 177 { 178 struct uba_attach_args *ua = aux; 179 int n; 180 181 /* Reset controller to initialize, enable TX/RX interrupts */ 182 /* to catch floating vector info elsewhere when completed */ 183 184 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 185 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 186 187 /* Now wait up to 3 seconds for self-test to complete. */ 188 189 for (n = 0; n < 300; n++) { 190 DELAY(10000); 191 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 192 DHU_CSR_MASTER_RESET) == 0) 193 break; 194 } 195 196 /* If the RESET did not clear after 3 seconds, */ 197 /* the controller must be broken. */ 198 199 if (n >= 300) 200 return 0; 201 202 /* Check whether diagnostic run has signalled a failure. */ 203 204 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 205 DHU_CSR_DIAG_FAIL) != 0) 206 return 0; 207 208 return 1; 209 } 210 211 static void 212 dhu_attach(parent, self, aux) 213 struct device *parent, *self; 214 void *aux; 215 { 216 struct dhu_softc *sc = (void *)self; 217 struct uba_attach_args *ua = aux; 218 unsigned c; 219 int n, i; 220 221 sc->sc_iot = ua->ua_iot; 222 sc->sc_ioh = ua->ua_ioh; 223 sc->sc_dmat = ua->ua_dmat; 224 /* Process the 8 bytes of diagnostic info put into */ 225 /* the FIFO following the master reset operation. */ 226 227 printf("\n%s:", self->dv_xname); 228 for (n = 0; n < 8; n++) { 229 c = DHU_READ_WORD(DHU_UBA_RBUF); 230 231 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 232 if ((c&0200) == 0000) 233 printf(" rom(%d) version %d", 234 ((c>>1)&01), ((c>>2)&037)); 235 else if (((c>>2)&07) != 0) 236 printf(" diag-error(proc%d)=%x", 237 ((c>>1)&01), ((c>>2)&07)); 238 } 239 } 240 241 c = DHU_READ_WORD(DHU_UBA_STAT); 242 243 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 244 245 sc->sc_lines = 8; /* default */ 246 if (sc->sc_type == IS_DHU && (c & DHU_STAT_MDL)) 247 sc->sc_lines = 16; 248 249 printf("\n%s: DH%s-11\n", self->dv_xname, 250 sc->sc_type == IS_DHU ? "U" : "V"); 251 252 for (i = 0; i < sc->sc_lines; i++) { 253 struct tty *tp; 254 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 255 sc->sc_dhu[i].dhu_state = STATE_IDLE; 256 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 257 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 258 &sc->sc_dhu[i].dhu_dmah); 259 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 260 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 261 262 } 263 264 /* Now establish RX & TX interrupt handlers */ 265 266 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 267 dhurint, sc, &sc->sc_rintrcnt); 268 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 269 dhuxint, sc, &sc->sc_tintrcnt); 270 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 271 sc->sc_dev.dv_xname, "rintr"); 272 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 273 sc->sc_dev.dv_xname, "tintr"); 274 } 275 276 /* Receiver Interrupt */ 277 278 static void 279 dhurint(arg) 280 void *arg; 281 { 282 struct dhu_softc *sc = arg; 283 struct tty *tp; 284 int cc, line; 285 unsigned c, delta; 286 int overrun = 0; 287 288 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 289 290 /* Ignore diagnostic FIFO entries. */ 291 292 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 293 continue; 294 295 cc = c & 0xFF; 296 line = DHU_LINE(c>>8); 297 tp = sc->sc_dhu[line].dhu_tty; 298 299 /* LINK.TYPE is set so we get modem control FIFO entries */ 300 301 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 302 c = (c << 8); 303 /* Do MDMBUF flow control, wakeup sleeping opens */ 304 if (c & DHU_STAT_DCD) { 305 if (!(tp->t_state & TS_CARR_ON)) 306 (void)(*tp->t_linesw->l_modem)(tp, 1); 307 } 308 else if ((tp->t_state & TS_CARR_ON) && 309 (*tp->t_linesw->l_modem)(tp, 0) == 0) 310 (void) dhumctl(sc, line, 0, DMSET); 311 312 /* Do CRTSCTS flow control */ 313 delta = c ^ sc->sc_dhu[line].dhu_modem; 314 sc->sc_dhu[line].dhu_modem = c; 315 if ((delta & DHU_STAT_CTS) && 316 (tp->t_state & TS_ISOPEN) && 317 (tp->t_cflag & CRTSCTS)) { 318 if (c & DHU_STAT_CTS) { 319 tp->t_state &= ~TS_TTSTOP; 320 ttstart(tp); 321 } else { 322 tp->t_state |= TS_TTSTOP; 323 dhustop(tp, 0); 324 } 325 } 326 continue; 327 } 328 329 if (!(tp->t_state & TS_ISOPEN)) { 330 wakeup((caddr_t)&tp->t_rawq); 331 continue; 332 } 333 334 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 335 log(LOG_WARNING, "%s: silo overflow, line %d\n", 336 sc->sc_dev.dv_xname, line); 337 overrun = 1; 338 } 339 /* A BREAK key will appear as a NULL with a framing error */ 340 if (c & DHU_RBUF_FRAMING_ERR) 341 cc |= TTY_FE; 342 if (c & DHU_RBUF_PARITY_ERR) 343 cc |= TTY_PE; 344 345 (*tp->t_linesw->l_rint)(cc, tp); 346 } 347 } 348 349 /* Transmitter Interrupt */ 350 351 static void 352 dhuxint(arg) 353 void *arg; 354 { 355 struct dhu_softc *sc = arg; 356 struct tty *tp; 357 int line, i; 358 359 while ((i = DHU_READ_BYTE(DHU_UBA_CSR_HI)) & (DHU_CSR_TX_ACTION >> 8)) { 360 361 line = DHU_LINE(i); 362 tp = sc->sc_dhu[line].dhu_tty; 363 364 if (i & (DHU_CSR_TX_DMA_ERROR >> 8)) 365 printf("%s: DMA ERROR on line: %d\n", 366 sc->sc_dev.dv_xname, line); 367 if (i & (DHU_CSR_DIAG_FAIL >> 8)) 368 printf("%s: DIAG FAIL on line: %d\n", 369 sc->sc_dev.dv_xname, line); 370 371 tp->t_state &= ~TS_BUSY; 372 if (tp->t_state & TS_FLUSH) 373 tp->t_state &= ~TS_FLUSH; 374 else { 375 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 376 sc->sc_dhu[line].dhu_cc -= 377 DHU_READ_WORD(DHU_UBA_TBUFCNT); 378 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 379 sc->sc_dhu[line].dhu_cc = 0; 380 } 381 382 sc->sc_dhu[line].dhu_state = STATE_IDLE; 383 384 (*tp->t_linesw->l_start)(tp); 385 } 386 } 387 388 int 389 dhuopen(dev, flag, mode, p) 390 dev_t dev; 391 int flag, mode; 392 struct proc *p; 393 { 394 struct tty *tp; 395 int unit, line; 396 struct dhu_softc *sc; 397 int s, error = 0; 398 399 unit = DHU_M2U(minor(dev)); 400 line = DHU_LINE(minor(dev)); 401 402 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 403 return (ENXIO); 404 405 sc = dhu_cd.cd_devs[unit]; 406 407 if (line >= sc->sc_lines) 408 return ENXIO; 409 410 if (sc->sc_type == IS_DHU) { 411 s = spltty(); /* CSR 3:0 must be 0 */ 412 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE); 413 DHU_WRITE_BYTE(DHU_UBA_RXTIME, 10); 414 splx(s); /* RX int delay 10ms */ 415 } 416 417 s = spltty(); 418 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 419 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 420 (void) splx(s); 421 422 tp = sc->sc_dhu[line].dhu_tty; 423 424 tp->t_oproc = dhustart; 425 tp->t_param = dhuparam; 426 tp->t_hwiflow = dhuiflow; 427 tp->t_dev = dev; 428 if ((tp->t_state & TS_ISOPEN) == 0) { 429 ttychars(tp); 430 if (tp->t_ispeed == 0) { 431 tp->t_iflag = TTYDEF_IFLAG; 432 tp->t_oflag = TTYDEF_OFLAG; 433 tp->t_cflag = TTYDEF_CFLAG; 434 tp->t_lflag = TTYDEF_LFLAG; 435 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 436 } 437 (void) dhuparam(tp, &tp->t_termios); 438 ttsetwater(tp); 439 } else if ((tp->t_state & TS_XCLUDE) && curproc->p_ucred->cr_uid != 0) 440 return (EBUSY); 441 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 442 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 443 tp->t_state |= TS_CARR_ON; 444 s = spltty(); 445 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 446 !(tp->t_state & TS_CARR_ON)) { 447 tp->t_wopen++; 448 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 449 TTIPRI | PCATCH, ttopen, 0); 450 tp->t_wopen--; 451 if (error) 452 break; 453 } 454 (void) splx(s); 455 if (error) 456 return (error); 457 return ((*tp->t_linesw->l_open)(dev, tp)); 458 } 459 460 /*ARGSUSED*/ 461 int 462 dhuclose(dev, flag, mode, p) 463 dev_t dev; 464 int flag, mode; 465 struct proc *p; 466 { 467 struct tty *tp; 468 int unit, line; 469 struct dhu_softc *sc; 470 471 unit = DHU_M2U(minor(dev)); 472 line = DHU_LINE(minor(dev)); 473 474 sc = dhu_cd.cd_devs[unit]; 475 476 tp = sc->sc_dhu[line].dhu_tty; 477 478 (*tp->t_linesw->l_close)(tp, flag); 479 480 /* Make sure a BREAK state is not left enabled. */ 481 482 (void) dhumctl(sc, line, DML_BRK, DMBIC); 483 484 /* Do a hangup if so required. */ 485 486 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 487 !(tp->t_state & TS_ISOPEN)) 488 (void) dhumctl(sc, line, 0, DMSET); 489 490 return (ttyclose(tp)); 491 } 492 493 int 494 dhuread(dev, uio, flag) 495 dev_t dev; 496 struct uio *uio; 497 int flag; 498 { 499 struct dhu_softc *sc; 500 struct tty *tp; 501 502 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 503 504 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 505 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 506 } 507 508 int 509 dhuwrite(dev, uio, flag) 510 dev_t dev; 511 struct uio *uio; 512 int flag; 513 { 514 struct dhu_softc *sc; 515 struct tty *tp; 516 517 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 518 519 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 520 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 521 } 522 523 int 524 dhupoll(dev, events, p) 525 dev_t dev; 526 int events; 527 struct proc *p; 528 { 529 struct dhu_softc *sc; 530 struct tty *tp; 531 532 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 533 534 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 535 return ((*tp->t_linesw->l_poll)(tp, events, p)); 536 } 537 538 /*ARGSUSED*/ 539 int 540 dhuioctl(dev, cmd, data, flag, p) 541 dev_t dev; 542 u_long cmd; 543 caddr_t data; 544 int flag; 545 struct proc *p; 546 { 547 struct dhu_softc *sc; 548 struct tty *tp; 549 int unit, line; 550 int error; 551 552 unit = DHU_M2U(minor(dev)); 553 line = DHU_LINE(minor(dev)); 554 sc = dhu_cd.cd_devs[unit]; 555 tp = sc->sc_dhu[line].dhu_tty; 556 557 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 558 if (error != EPASSTHROUGH) 559 return (error); 560 561 error = ttioctl(tp, cmd, data, flag, p); 562 if (error != EPASSTHROUGH) 563 return (error); 564 565 switch (cmd) { 566 567 case TIOCSBRK: 568 (void) dhumctl(sc, line, DML_BRK, DMBIS); 569 break; 570 571 case TIOCCBRK: 572 (void) dhumctl(sc, line, DML_BRK, DMBIC); 573 break; 574 575 case TIOCSDTR: 576 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 577 break; 578 579 case TIOCCDTR: 580 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 581 break; 582 583 case TIOCMSET: 584 (void) dhumctl(sc, line, *(int *)data, DMSET); 585 break; 586 587 case TIOCMBIS: 588 (void) dhumctl(sc, line, *(int *)data, DMBIS); 589 break; 590 591 case TIOCMBIC: 592 (void) dhumctl(sc, line, *(int *)data, DMBIC); 593 break; 594 595 case TIOCMGET: 596 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 597 break; 598 599 default: 600 return (EPASSTHROUGH); 601 } 602 return (0); 603 } 604 605 struct tty * 606 dhutty(dev) 607 dev_t dev; 608 { 609 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 610 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 611 return (tp); 612 } 613 614 /*ARGSUSED*/ 615 void 616 dhustop(tp, flag) 617 struct tty *tp; 618 int flag; 619 { 620 struct dhu_softc *sc; 621 int line; 622 int s; 623 624 s = spltty(); 625 626 if (tp->t_state & TS_BUSY) { 627 628 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 629 line = DHU_LINE(minor(tp->t_dev)); 630 631 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 632 633 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 634 635 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 636 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 637 DHU_READ_WORD(DHU_UBA_LNCTRL) | 638 DHU_LNCTRL_DMA_ABORT); 639 } 640 641 if (!(tp->t_state & TS_TTSTOP)) 642 tp->t_state |= TS_FLUSH; 643 } 644 (void) splx(s); 645 } 646 647 static void 648 dhustart(tp) 649 struct tty *tp; 650 { 651 struct dhu_softc *sc; 652 int line, cc; 653 int addr; 654 int s; 655 656 s = spltty(); 657 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 658 goto out; 659 if (tp->t_outq.c_cc <= tp->t_lowat) { 660 if (tp->t_state & TS_ASLEEP) { 661 tp->t_state &= ~TS_ASLEEP; 662 wakeup((caddr_t)&tp->t_outq); 663 } 664 selwakeup(&tp->t_wsel); 665 } 666 if (tp->t_outq.c_cc == 0) 667 goto out; 668 cc = ndqb(&tp->t_outq, 0); 669 if (cc == 0) 670 goto out; 671 672 tp->t_state |= TS_BUSY; 673 674 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 675 676 line = DHU_LINE(minor(tp->t_dev)); 677 678 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 679 680 sc->sc_dhu[line].dhu_cc = cc; 681 682 if (cc == 1 && sc->sc_type == IS_DHV) { 683 684 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 685 686 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 687 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 688 689 } else { 690 691 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 692 693 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 694 (tp->t_outq.c_cf - tp->t_outq.c_cs); 695 696 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 697 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 698 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 699 DHU_TBUFAD2_TX_ENABLE); 700 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 701 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 702 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 703 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 704 } 705 out: 706 (void) splx(s); 707 return; 708 } 709 710 static int 711 dhuparam(tp, t) 712 struct tty *tp; 713 struct termios *t; 714 { 715 struct dhu_softc *sc; 716 int cflag = t->c_cflag; 717 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 718 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 719 unsigned lpr, lnctrl; 720 int unit, line; 721 int s; 722 723 unit = DHU_M2U(minor(tp->t_dev)); 724 line = DHU_LINE(minor(tp->t_dev)); 725 726 sc = dhu_cd.cd_devs[unit]; 727 728 /* check requested parameters */ 729 if (ospeed < 0 || ispeed < 0) 730 return (EINVAL); 731 732 tp->t_ispeed = t->c_ispeed; 733 tp->t_ospeed = t->c_ospeed; 734 tp->t_cflag = cflag; 735 736 if (ospeed == 0) { 737 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 738 return (0); 739 } 740 741 s = spltty(); 742 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 743 744 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 745 746 switch (cflag & CSIZE) { 747 748 case CS5: 749 lpr |= DHU_LPR_5_BIT_CHAR; 750 break; 751 752 case CS6: 753 lpr |= DHU_LPR_6_BIT_CHAR; 754 break; 755 756 case CS7: 757 lpr |= DHU_LPR_7_BIT_CHAR; 758 break; 759 760 default: 761 lpr |= DHU_LPR_8_BIT_CHAR; 762 break; 763 } 764 765 if (cflag & PARENB) 766 lpr |= DHU_LPR_PARENB; 767 if (!(cflag & PARODD)) 768 lpr |= DHU_LPR_EPAR; 769 if (cflag & CSTOPB) 770 lpr |= DHU_LPR_2_STOP; 771 772 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 773 774 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 775 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 776 777 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 778 779 /* Setting LINK.TYPE enables modem signal change interrupts. */ 780 781 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 782 783 /* Enable the auto XON/XOFF feature on the controller */ 784 785 if (t->c_iflag & IXON) 786 lnctrl |= DHU_LNCTRL_OAUTO; 787 else 788 lnctrl &= ~DHU_LNCTRL_OAUTO; 789 790 if (t->c_iflag & IXOFF) 791 lnctrl |= DHU_LNCTRL_IAUTO; 792 else 793 lnctrl &= ~DHU_LNCTRL_IAUTO; 794 795 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 796 797 (void) splx(s); 798 return (0); 799 } 800 801 static int 802 dhuiflow(tp, flag) 803 struct tty *tp; 804 int flag; 805 { 806 struct dhu_softc *sc; 807 int line = DHU_LINE(minor(tp->t_dev)); 808 809 if (tp->t_cflag & CRTSCTS) { 810 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 811 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 812 return (1); 813 } 814 return (0); 815 } 816 817 static unsigned 818 dhumctl(sc, line, bits, how) 819 struct dhu_softc *sc; 820 int line, bits, how; 821 { 822 unsigned status; 823 unsigned lnctrl; 824 unsigned mbits; 825 int s; 826 827 s = spltty(); 828 829 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 830 831 mbits = 0; 832 833 /* external signals as seen from the port */ 834 835 status = DHU_READ_WORD(DHU_UBA_STAT); 836 837 if (status & DHU_STAT_CTS) 838 mbits |= DML_CTS; 839 840 if (status & DHU_STAT_DCD) 841 mbits |= DML_DCD; 842 843 if (status & DHU_STAT_DSR) 844 mbits |= DML_DSR; 845 846 if (status & DHU_STAT_RI) 847 mbits |= DML_RI; 848 849 /* internal signals/state delivered to port */ 850 851 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 852 853 if (lnctrl & DHU_LNCTRL_RTS) 854 mbits |= DML_RTS; 855 856 if (lnctrl & DHU_LNCTRL_DTR) 857 mbits |= DML_DTR; 858 859 if (lnctrl & DHU_LNCTRL_BREAK) 860 mbits |= DML_BRK; 861 862 switch (how) { 863 864 case DMSET: 865 mbits = bits; 866 break; 867 868 case DMBIS: 869 mbits |= bits; 870 break; 871 872 case DMBIC: 873 mbits &= ~bits; 874 break; 875 876 case DMGET: 877 (void) splx(s); 878 return (mbits); 879 } 880 881 if (mbits & DML_RTS) 882 lnctrl |= DHU_LNCTRL_RTS; 883 else 884 lnctrl &= ~DHU_LNCTRL_RTS; 885 886 if (mbits & DML_DTR) 887 lnctrl |= DHU_LNCTRL_DTR; 888 else 889 lnctrl &= ~DHU_LNCTRL_DTR; 890 891 if (mbits & DML_BRK) 892 lnctrl |= DHU_LNCTRL_BREAK; 893 else 894 lnctrl &= ~DHU_LNCTRL_BREAK; 895 896 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 897 898 (void) splx(s); 899 return (mbits); 900 } 901
Indexes created Fri Sep 26 20:09:58 GMT 2025