dhu.c revision 1.42
1 /* $NetBSD: dhu.c,v 1.42 2006/03/29 18:17:36 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2003, Hugh Graham. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * Ralph Campbell and Rick Macklem. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.42 2006/03/29 18:17:36 thorpej Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/ioctl.h> 76 #include <sys/tty.h> 77 #include <sys/proc.h> 78 #include <sys/buf.h> 79 #include <sys/conf.h> 80 #include <sys/file.h> 81 #include <sys/uio.h> 82 #include <sys/kernel.h> 83 #include <sys/syslog.h> 84 #include <sys/device.h> 85 86 #include <machine/bus.h> 87 #include <machine/scb.h> 88 89 #include <dev/qbus/ubavar.h> 90 91 #include <dev/qbus/dhureg.h> 92 93 #include "ioconf.h" 94 95 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 96 97 #define NDHULINE 16 98 99 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 100 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 101 102 struct dhu_softc { 103 struct device sc_dev; /* Device struct used by config */ 104 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 105 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 106 int sc_type; /* controller type, DHU or DHV */ 107 int sc_lines; /* number of lines */ 108 bus_space_tag_t sc_iot; 109 bus_space_handle_t sc_ioh; 110 bus_dma_tag_t sc_dmat; 111 struct { 112 struct tty *dhu_tty; /* what we work on */ 113 bus_dmamap_t dhu_dmah; 114 int dhu_state; /* to manage TX output status */ 115 short dhu_cc; /* character count on TX */ 116 short dhu_modem; /* modem bits state */ 117 } sc_dhu[NDHULINE]; 118 }; 119 120 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 121 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 122 123 #define STATE_IDLE 000 /* no current output in progress */ 124 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 125 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 126 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 127 128 /* Flags used to monitor modem bits, make them understood outside driver */ 129 130 #define DML_DTR TIOCM_DTR 131 #define DML_RTS TIOCM_RTS 132 #define DML_CTS TIOCM_CTS 133 #define DML_DCD TIOCM_CD 134 #define DML_RI TIOCM_RI 135 #define DML_DSR TIOCM_DSR 136 #define DML_BRK 0100000 /* no equivalent, we will mask */ 137 138 #define DHU_READ_WORD(reg) \ 139 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 140 #define DHU_WRITE_WORD(reg, val) \ 141 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 142 #define DHU_READ_BYTE(reg) \ 143 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 144 #define DHU_WRITE_BYTE(reg, val) \ 145 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 146 147 148 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 149 /* a baud rate from the same group. So limiting to B is likely */ 150 /* best, although clone boards like the ABLE QHV allow all settings. */ 151 152 static const struct speedtab dhuspeedtab[] = { 153 { 0, 0 }, /* Groups */ 154 { 50, DHU_LPR_B50 }, /* A */ 155 { 75, DHU_LPR_B75 }, /* B */ 156 { 110, DHU_LPR_B110 }, /* A and B */ 157 { 134, DHU_LPR_B134 }, /* A and B */ 158 { 150, DHU_LPR_B150 }, /* B */ 159 { 300, DHU_LPR_B300 }, /* A and B */ 160 { 600, DHU_LPR_B600 }, /* A and B */ 161 { 1200, DHU_LPR_B1200 }, /* A and B */ 162 { 1800, DHU_LPR_B1800 }, /* B */ 163 { 2000, DHU_LPR_B2000 }, /* B */ 164 { 2400, DHU_LPR_B2400 }, /* A and B */ 165 { 4800, DHU_LPR_B4800 }, /* A and B */ 166 { 7200, DHU_LPR_B7200 }, /* A */ 167 { 9600, DHU_LPR_B9600 }, /* A and B */ 168 { 19200, DHU_LPR_B19200 }, /* B */ 169 { 38400, DHU_LPR_B38400 }, /* A */ 170 { -1, -1 } 171 }; 172 173 static int dhu_match(struct device *, struct cfdata *, void *); 174 static void dhu_attach(struct device *, struct device *, void *); 175 static void dhurint(void *); 176 static void dhuxint(void *); 177 static void dhustart(struct tty *); 178 static int dhuparam(struct tty *, struct termios *); 179 static int dhuiflow(struct tty *, int); 180 static unsigned dhumctl(struct dhu_softc *,int, int, int); 181 182 CFATTACH_DECL(dhu, sizeof(struct dhu_softc), 183 dhu_match, dhu_attach, NULL, NULL); 184 185 dev_type_open(dhuopen); 186 dev_type_close(dhuclose); 187 dev_type_read(dhuread); 188 dev_type_write(dhuwrite); 189 dev_type_ioctl(dhuioctl); 190 dev_type_stop(dhustop); 191 dev_type_tty(dhutty); 192 dev_type_poll(dhupoll); 193 194 const struct cdevsw dhu_cdevsw = { 195 dhuopen, dhuclose, dhuread, dhuwrite, dhuioctl, 196 dhustop, dhutty, dhupoll, nommap, ttykqfilter, D_TTY 197 }; 198 199 /* Autoconfig handles: setup the controller to interrupt, */ 200 /* then complete the housecleaning for full operation */ 201 202 static int 203 dhu_match(parent, cf, aux) 204 struct device *parent; 205 struct cfdata *cf; 206 void *aux; 207 { 208 struct uba_attach_args *ua = aux; 209 int n; 210 211 /* Reset controller to initialize, enable TX/RX interrupts */ 212 /* to catch floating vector info elsewhere when completed */ 213 214 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 215 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 216 217 /* Now wait up to 3 seconds for self-test to complete. */ 218 219 for (n = 0; n < 300; n++) { 220 DELAY(10000); 221 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 222 DHU_CSR_MASTER_RESET) == 0) 223 break; 224 } 225 226 /* If the RESET did not clear after 3 seconds, */ 227 /* the controller must be broken. */ 228 229 if (n >= 300) 230 return 0; 231 232 /* Check whether diagnostic run has signalled a failure. */ 233 234 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 235 DHU_CSR_DIAG_FAIL) != 0) 236 return 0; 237 238 return 1; 239 } 240 241 static void 242 dhu_attach(parent, self, aux) 243 struct device *parent, *self; 244 void *aux; 245 { 246 struct dhu_softc *sc = device_private(self); 247 struct uba_attach_args *ua = aux; 248 unsigned c; 249 int n, i; 250 251 sc->sc_iot = ua->ua_iot; 252 sc->sc_ioh = ua->ua_ioh; 253 sc->sc_dmat = ua->ua_dmat; 254 /* Process the 8 bytes of diagnostic info put into */ 255 /* the FIFO following the master reset operation. */ 256 257 printf("\n%s:", self->dv_xname); 258 for (n = 0; n < 8; n++) { 259 c = DHU_READ_WORD(DHU_UBA_RBUF); 260 261 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 262 if ((c&0200) == 0000) 263 printf(" rom(%d) version %d", 264 ((c>>1)&01), ((c>>2)&037)); 265 else if (((c>>2)&07) != 0) 266 printf(" diag-error(proc%d)=%x", 267 ((c>>1)&01), ((c>>2)&07)); 268 } 269 } 270 271 c = DHU_READ_WORD(DHU_UBA_STAT); 272 273 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 274 275 sc->sc_lines = 8; /* default */ 276 if (sc->sc_type == IS_DHU && (c & DHU_STAT_MDL)) 277 sc->sc_lines = 16; 278 279 printf("\n%s: DH%s-11\n", self->dv_xname, 280 sc->sc_type == IS_DHU ? "U" : "V"); 281 282 for (i = 0; i < sc->sc_lines; i++) { 283 struct tty *tp; 284 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 285 sc->sc_dhu[i].dhu_state = STATE_IDLE; 286 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 287 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 288 &sc->sc_dhu[i].dhu_dmah); 289 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 290 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 291 292 } 293 294 /* Now establish RX & TX interrupt handlers */ 295 296 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 297 dhurint, sc, &sc->sc_rintrcnt); 298 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 299 dhuxint, sc, &sc->sc_tintrcnt); 300 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 301 sc->sc_dev.dv_xname, "rintr"); 302 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 303 sc->sc_dev.dv_xname, "tintr"); 304 } 305 306 /* Receiver Interrupt */ 307 308 static void 309 dhurint(arg) 310 void *arg; 311 { 312 struct dhu_softc *sc = arg; 313 struct tty *tp; 314 int cc, line; 315 unsigned c, delta; 316 int overrun = 0; 317 318 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 319 320 /* Ignore diagnostic FIFO entries. */ 321 322 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 323 continue; 324 325 cc = c & 0xFF; 326 line = DHU_LINE(c>>8); 327 tp = sc->sc_dhu[line].dhu_tty; 328 329 /* LINK.TYPE is set so we get modem control FIFO entries */ 330 331 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 332 c = (c << 8); 333 /* Do MDMBUF flow control, wakeup sleeping opens */ 334 if (c & DHU_STAT_DCD) { 335 if (!(tp->t_state & TS_CARR_ON)) 336 (void)(*tp->t_linesw->l_modem)(tp, 1); 337 } 338 else if ((tp->t_state & TS_CARR_ON) && 339 (*tp->t_linesw->l_modem)(tp, 0) == 0) 340 (void) dhumctl(sc, line, 0, DMSET); 341 342 /* Do CRTSCTS flow control */ 343 delta = c ^ sc->sc_dhu[line].dhu_modem; 344 sc->sc_dhu[line].dhu_modem = c; 345 if ((delta & DHU_STAT_CTS) && 346 (tp->t_state & TS_ISOPEN) && 347 (tp->t_cflag & CRTSCTS)) { 348 if (c & DHU_STAT_CTS) { 349 tp->t_state &= ~TS_TTSTOP; 350 ttstart(tp); 351 } else { 352 tp->t_state |= TS_TTSTOP; 353 dhustop(tp, 0); 354 } 355 } 356 continue; 357 } 358 359 if (!(tp->t_state & TS_ISOPEN)) { 360 wakeup((caddr_t)&tp->t_rawq); 361 continue; 362 } 363 364 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 365 log(LOG_WARNING, "%s: silo overflow, line %d\n", 366 sc->sc_dev.dv_xname, line); 367 overrun = 1; 368 } 369 /* A BREAK key will appear as a NULL with a framing error */ 370 if (c & DHU_RBUF_FRAMING_ERR) 371 cc |= TTY_FE; 372 if (c & DHU_RBUF_PARITY_ERR) 373 cc |= TTY_PE; 374 375 (*tp->t_linesw->l_rint)(cc, tp); 376 } 377 } 378 379 /* Transmitter Interrupt */ 380 381 static void 382 dhuxint(arg) 383 void *arg; 384 { 385 struct dhu_softc *sc = arg; 386 struct tty *tp; 387 int line, i; 388 389 while ((i = DHU_READ_BYTE(DHU_UBA_CSR_HI)) & (DHU_CSR_TX_ACTION >> 8)) { 390 391 line = DHU_LINE(i); 392 tp = sc->sc_dhu[line].dhu_tty; 393 394 if (i & (DHU_CSR_TX_DMA_ERROR >> 8)) 395 printf("%s: DMA ERROR on line: %d\n", 396 sc->sc_dev.dv_xname, line); 397 if (i & (DHU_CSR_DIAG_FAIL >> 8)) 398 printf("%s: DIAG FAIL on line: %d\n", 399 sc->sc_dev.dv_xname, line); 400 401 tp->t_state &= ~TS_BUSY; 402 if (tp->t_state & TS_FLUSH) 403 tp->t_state &= ~TS_FLUSH; 404 else { 405 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 406 sc->sc_dhu[line].dhu_cc -= 407 DHU_READ_WORD(DHU_UBA_TBUFCNT); 408 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 409 sc->sc_dhu[line].dhu_cc = 0; 410 } 411 412 sc->sc_dhu[line].dhu_state = STATE_IDLE; 413 414 (*tp->t_linesw->l_start)(tp); 415 } 416 } 417 418 int 419 dhuopen(dev, flag, mode, l) 420 dev_t dev; 421 int flag, mode; 422 struct lwp *l; 423 { 424 struct tty *tp; 425 int unit, line; 426 struct dhu_softc *sc; 427 int s, error = 0; 428 429 unit = DHU_M2U(minor(dev)); 430 line = DHU_LINE(minor(dev)); 431 432 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 433 return (ENXIO); 434 435 sc = dhu_cd.cd_devs[unit]; 436 437 if (line >= sc->sc_lines) 438 return ENXIO; 439 440 if (sc->sc_type == IS_DHU) { 441 s = spltty(); /* CSR 3:0 must be 0 */ 442 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE); 443 DHU_WRITE_BYTE(DHU_UBA_RXTIME, 10); 444 splx(s); /* RX int delay 10ms */ 445 } 446 447 s = spltty(); 448 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 449 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 450 (void) splx(s); 451 452 tp = sc->sc_dhu[line].dhu_tty; 453 454 tp->t_oproc = dhustart; 455 tp->t_param = dhuparam; 456 tp->t_hwiflow = dhuiflow; 457 tp->t_dev = dev; 458 if ((tp->t_state & TS_ISOPEN) == 0) { 459 ttychars(tp); 460 if (tp->t_ispeed == 0) { 461 tp->t_iflag = TTYDEF_IFLAG; 462 tp->t_oflag = TTYDEF_OFLAG; 463 tp->t_cflag = TTYDEF_CFLAG; 464 tp->t_lflag = TTYDEF_LFLAG; 465 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 466 } 467 (void) dhuparam(tp, &tp->t_termios); 468 ttsetwater(tp); 469 } else if ((tp->t_state & TS_XCLUDE) && 470 suser(l->l_proc->p_ucred, &l->l_proc->p_acflag) != 0) 471 return (EBUSY); 472 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 473 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 474 tp->t_state |= TS_CARR_ON; 475 s = spltty(); 476 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 477 !(tp->t_state & TS_CARR_ON)) { 478 tp->t_wopen++; 479 error = ttysleep(tp, (caddr_t)&tp->t_rawq, 480 TTIPRI | PCATCH, ttopen, 0); 481 tp->t_wopen--; 482 if (error) 483 break; 484 } 485 (void) splx(s); 486 if (error) 487 return (error); 488 return ((*tp->t_linesw->l_open)(dev, tp)); 489 } 490 491 /*ARGSUSED*/ 492 int 493 dhuclose(dev, flag, mode, l) 494 dev_t dev; 495 int flag, mode; 496 struct lwp *l; 497 { 498 struct tty *tp; 499 int unit, line; 500 struct dhu_softc *sc; 501 502 unit = DHU_M2U(minor(dev)); 503 line = DHU_LINE(minor(dev)); 504 505 sc = dhu_cd.cd_devs[unit]; 506 507 tp = sc->sc_dhu[line].dhu_tty; 508 509 (*tp->t_linesw->l_close)(tp, flag); 510 511 /* Make sure a BREAK state is not left enabled. */ 512 513 (void) dhumctl(sc, line, DML_BRK, DMBIC); 514 515 /* Do a hangup if so required. */ 516 517 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 518 !(tp->t_state & TS_ISOPEN)) 519 (void) dhumctl(sc, line, 0, DMSET); 520 521 return (ttyclose(tp)); 522 } 523 524 int 525 dhuread(dev, uio, flag) 526 dev_t dev; 527 struct uio *uio; 528 int flag; 529 { 530 struct dhu_softc *sc; 531 struct tty *tp; 532 533 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 534 535 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 536 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 537 } 538 539 int 540 dhuwrite(dev, uio, flag) 541 dev_t dev; 542 struct uio *uio; 543 int flag; 544 { 545 struct dhu_softc *sc; 546 struct tty *tp; 547 548 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 549 550 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 551 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 552 } 553 554 int 555 dhupoll(dev, events, l) 556 dev_t dev; 557 int events; 558 struct lwp *l; 559 { 560 struct dhu_softc *sc; 561 struct tty *tp; 562 563 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 564 565 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 566 return ((*tp->t_linesw->l_poll)(tp, events, l)); 567 } 568 569 /*ARGSUSED*/ 570 int 571 dhuioctl(dev, cmd, data, flag, l) 572 dev_t dev; 573 u_long cmd; 574 caddr_t data; 575 int flag; 576 struct lwp *l; 577 { 578 struct dhu_softc *sc; 579 struct tty *tp; 580 int unit, line; 581 int error; 582 583 unit = DHU_M2U(minor(dev)); 584 line = DHU_LINE(minor(dev)); 585 sc = dhu_cd.cd_devs[unit]; 586 tp = sc->sc_dhu[line].dhu_tty; 587 588 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 589 if (error != EPASSTHROUGH) 590 return (error); 591 592 error = ttioctl(tp, cmd, data, flag, l); 593 if (error != EPASSTHROUGH) 594 return (error); 595 596 switch (cmd) { 597 598 case TIOCSBRK: 599 (void) dhumctl(sc, line, DML_BRK, DMBIS); 600 break; 601 602 case TIOCCBRK: 603 (void) dhumctl(sc, line, DML_BRK, DMBIC); 604 break; 605 606 case TIOCSDTR: 607 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 608 break; 609 610 case TIOCCDTR: 611 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 612 break; 613 614 case TIOCMSET: 615 (void) dhumctl(sc, line, *(int *)data, DMSET); 616 break; 617 618 case TIOCMBIS: 619 (void) dhumctl(sc, line, *(int *)data, DMBIS); 620 break; 621 622 case TIOCMBIC: 623 (void) dhumctl(sc, line, *(int *)data, DMBIC); 624 break; 625 626 case TIOCMGET: 627 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 628 break; 629 630 default: 631 return (EPASSTHROUGH); 632 } 633 return (0); 634 } 635 636 struct tty * 637 dhutty(dev) 638 dev_t dev; 639 { 640 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 641 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 642 return (tp); 643 } 644 645 /*ARGSUSED*/ 646 void 647 dhustop(tp, flag) 648 struct tty *tp; 649 int flag; 650 { 651 struct dhu_softc *sc; 652 int line; 653 int s; 654 655 s = spltty(); 656 657 if (tp->t_state & TS_BUSY) { 658 659 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 660 line = DHU_LINE(minor(tp->t_dev)); 661 662 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 663 664 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 665 666 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 667 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 668 DHU_READ_WORD(DHU_UBA_LNCTRL) | 669 DHU_LNCTRL_DMA_ABORT); 670 } 671 672 if (!(tp->t_state & TS_TTSTOP)) 673 tp->t_state |= TS_FLUSH; 674 } 675 (void) splx(s); 676 } 677 678 static void 679 dhustart(tp) 680 struct tty *tp; 681 { 682 struct dhu_softc *sc; 683 int line, cc; 684 int addr; 685 int s; 686 687 s = spltty(); 688 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 689 goto out; 690 if (tp->t_outq.c_cc <= tp->t_lowat) { 691 if (tp->t_state & TS_ASLEEP) { 692 tp->t_state &= ~TS_ASLEEP; 693 wakeup((caddr_t)&tp->t_outq); 694 } 695 selwakeup(&tp->t_wsel); 696 } 697 if (tp->t_outq.c_cc == 0) 698 goto out; 699 cc = ndqb(&tp->t_outq, 0); 700 if (cc == 0) 701 goto out; 702 703 tp->t_state |= TS_BUSY; 704 705 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 706 707 line = DHU_LINE(minor(tp->t_dev)); 708 709 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 710 711 sc->sc_dhu[line].dhu_cc = cc; 712 713 if (cc == 1 && sc->sc_type == IS_DHV) { 714 715 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 716 717 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 718 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 719 720 } else { 721 722 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 723 724 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 725 (tp->t_outq.c_cf - tp->t_outq.c_cs); 726 727 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 728 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 729 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 730 DHU_TBUFAD2_TX_ENABLE); 731 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 732 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 733 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 734 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 735 } 736 out: 737 (void) splx(s); 738 return; 739 } 740 741 static int 742 dhuparam(tp, t) 743 struct tty *tp; 744 struct termios *t; 745 { 746 struct dhu_softc *sc; 747 int cflag = t->c_cflag; 748 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 749 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 750 unsigned lpr, lnctrl; 751 int unit, line; 752 int s; 753 754 unit = DHU_M2U(minor(tp->t_dev)); 755 line = DHU_LINE(minor(tp->t_dev)); 756 757 sc = dhu_cd.cd_devs[unit]; 758 759 /* check requested parameters */ 760 if (ospeed < 0 || ispeed < 0) 761 return (EINVAL); 762 763 tp->t_ispeed = t->c_ispeed; 764 tp->t_ospeed = t->c_ospeed; 765 tp->t_cflag = cflag; 766 767 if (ospeed == 0) { 768 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 769 return (0); 770 } 771 772 s = spltty(); 773 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 774 775 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 776 777 switch (cflag & CSIZE) { 778 779 case CS5: 780 lpr |= DHU_LPR_5_BIT_CHAR; 781 break; 782 783 case CS6: 784 lpr |= DHU_LPR_6_BIT_CHAR; 785 break; 786 787 case CS7: 788 lpr |= DHU_LPR_7_BIT_CHAR; 789 break; 790 791 default: 792 lpr |= DHU_LPR_8_BIT_CHAR; 793 break; 794 } 795 796 if (cflag & PARENB) 797 lpr |= DHU_LPR_PARENB; 798 if (!(cflag & PARODD)) 799 lpr |= DHU_LPR_EPAR; 800 if (cflag & CSTOPB) 801 lpr |= DHU_LPR_2_STOP; 802 803 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 804 805 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 806 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 807 808 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 809 810 /* Setting LINK.TYPE enables modem signal change interrupts. */ 811 812 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 813 814 /* Enable the auto XON/XOFF feature on the controller */ 815 816 if (t->c_iflag & IXON) 817 lnctrl |= DHU_LNCTRL_OAUTO; 818 else 819 lnctrl &= ~DHU_LNCTRL_OAUTO; 820 821 if (t->c_iflag & IXOFF) 822 lnctrl |= DHU_LNCTRL_IAUTO; 823 else 824 lnctrl &= ~DHU_LNCTRL_IAUTO; 825 826 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 827 828 (void) splx(s); 829 return (0); 830 } 831 832 static int 833 dhuiflow(tp, flag) 834 struct tty *tp; 835 int flag; 836 { 837 struct dhu_softc *sc; 838 int line = DHU_LINE(minor(tp->t_dev)); 839 840 if (tp->t_cflag & CRTSCTS) { 841 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 842 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 843 return (1); 844 } 845 return (0); 846 } 847 848 static unsigned 849 dhumctl(sc, line, bits, how) 850 struct dhu_softc *sc; 851 int line, bits, how; 852 { 853 unsigned status; 854 unsigned lnctrl; 855 unsigned mbits; 856 int s; 857 858 s = spltty(); 859 860 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 861 862 mbits = 0; 863 864 /* external signals as seen from the port */ 865 866 status = DHU_READ_WORD(DHU_UBA_STAT); 867 868 if (status & DHU_STAT_CTS) 869 mbits |= DML_CTS; 870 871 if (status & DHU_STAT_DCD) 872 mbits |= DML_DCD; 873 874 if (status & DHU_STAT_DSR) 875 mbits |= DML_DSR; 876 877 if (status & DHU_STAT_RI) 878 mbits |= DML_RI; 879 880 /* internal signals/state delivered to port */ 881 882 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 883 884 if (lnctrl & DHU_LNCTRL_RTS) 885 mbits |= DML_RTS; 886 887 if (lnctrl & DHU_LNCTRL_DTR) 888 mbits |= DML_DTR; 889 890 if (lnctrl & DHU_LNCTRL_BREAK) 891 mbits |= DML_BRK; 892 893 switch (how) { 894 895 case DMSET: 896 mbits = bits; 897 break; 898 899 case DMBIS: 900 mbits |= bits; 901 break; 902 903 case DMBIC: 904 mbits &= ~bits; 905 break; 906 907 case DMGET: 908 (void) splx(s); 909 return (mbits); 910 } 911 912 if (mbits & DML_RTS) 913 lnctrl |= DHU_LNCTRL_RTS; 914 else 915 lnctrl &= ~DHU_LNCTRL_RTS; 916 917 if (mbits & DML_DTR) 918 lnctrl |= DHU_LNCTRL_DTR; 919 else 920 lnctrl &= ~DHU_LNCTRL_DTR; 921 922 if (mbits & DML_BRK) 923 lnctrl |= DHU_LNCTRL_BREAK; 924 else 925 lnctrl &= ~DHU_LNCTRL_BREAK; 926 927 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 928 929 (void) splx(s); 930 return (mbits); 931 } 932
Indexes created Wed Sep 24 05:09:52 GMT 2025