dhu.c revision 1.49
1 /* $NetBSD: dhu.c,v 1.49 2007/11/07 15:56:21 ad Exp $ */ 2 /* 3 * Copyright (c) 2003, Hugh Graham. 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Copyright (c) 1996 Ken C. Wellsch. All rights reserved. 37 * 38 * This code is derived from software contributed to Berkeley by 39 * Ralph Campbell and Rick Macklem. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by the University of 52 * California, Berkeley and its contributors. 53 * 4. Neither the name of the University nor the names of its contributors 54 * may be used to endorse or promote products derived from this software 55 * without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 59 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 60 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 61 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 62 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 63 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 64 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 65 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 66 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 67 * SUCH DAMAGE. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: dhu.c,v 1.49 2007/11/07 15:56:21 ad Exp $"); 72 73 #include <sys/param.h> 74 #include <sys/systm.h> 75 #include <sys/ioctl.h> 76 #include <sys/tty.h> 77 #include <sys/proc.h> 78 #include <sys/buf.h> 79 #include <sys/conf.h> 80 #include <sys/file.h> 81 #include <sys/uio.h> 82 #include <sys/kernel.h> 83 #include <sys/syslog.h> 84 #include <sys/device.h> 85 #include <sys/kauth.h> 86 87 #include <sys/bus.h> 88 #include <machine/scb.h> 89 90 #include <dev/qbus/ubavar.h> 91 92 #include <dev/qbus/dhureg.h> 93 94 #include "ioconf.h" 95 96 /* A DHU-11 has 16 ports while a DHV-11 has only 8. We use 16 by default */ 97 98 #define NDHULINE 16 99 100 #define DHU_M2U(c) ((c)>>4) /* convert minor(dev) to unit # */ 101 #define DHU_LINE(u) ((u)&0xF) /* extract line # from minor(dev) */ 102 103 struct dhu_softc { 104 struct device sc_dev; /* Device struct used by config */ 105 struct evcnt sc_rintrcnt; /* Interrupt statistics */ 106 struct evcnt sc_tintrcnt; /* Interrupt statistics */ 107 int sc_type; /* controller type, DHU or DHV */ 108 int sc_lines; /* number of lines */ 109 bus_space_tag_t sc_iot; 110 bus_space_handle_t sc_ioh; 111 bus_dma_tag_t sc_dmat; 112 struct { 113 struct tty *dhu_tty; /* what we work on */ 114 bus_dmamap_t dhu_dmah; 115 int dhu_state; /* to manage TX output status */ 116 short dhu_cc; /* character count on TX */ 117 short dhu_modem; /* modem bits state */ 118 } sc_dhu[NDHULINE]; 119 }; 120 121 #define IS_DHU 16 /* Unibus DHU-11 board linecount */ 122 #define IS_DHV 8 /* Q-bus DHV-11 or DHQ-11 */ 123 124 #define STATE_IDLE 000 /* no current output in progress */ 125 #define STATE_DMA_RUNNING 001 /* DMA TX in progress */ 126 #define STATE_DMA_STOPPED 002 /* DMA TX was aborted */ 127 #define STATE_TX_ONE_CHAR 004 /* did a single char directly */ 128 129 /* Flags used to monitor modem bits, make them understood outside driver */ 130 131 #define DML_DTR TIOCM_DTR 132 #define DML_RTS TIOCM_RTS 133 #define DML_CTS TIOCM_CTS 134 #define DML_DCD TIOCM_CD 135 #define DML_RI TIOCM_RI 136 #define DML_DSR TIOCM_DSR 137 #define DML_BRK 0100000 /* no equivalent, we will mask */ 138 139 #define DHU_READ_WORD(reg) \ 140 bus_space_read_2(sc->sc_iot, sc->sc_ioh, reg) 141 #define DHU_WRITE_WORD(reg, val) \ 142 bus_space_write_2(sc->sc_iot, sc->sc_ioh, reg, val) 143 #define DHU_READ_BYTE(reg) \ 144 bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg) 145 #define DHU_WRITE_BYTE(reg, val) \ 146 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val) 147 148 149 /* On a stock DHV, channel pairs (0/1, 2/3, etc.) must use */ 150 /* a baud rate from the same group. So limiting to B is likely */ 151 /* best, although clone boards like the ABLE QHV allow all settings. */ 152 153 static const struct speedtab dhuspeedtab[] = { 154 { 0, 0 }, /* Groups */ 155 { 50, DHU_LPR_B50 }, /* A */ 156 { 75, DHU_LPR_B75 }, /* B */ 157 { 110, DHU_LPR_B110 }, /* A and B */ 158 { 134, DHU_LPR_B134 }, /* A and B */ 159 { 150, DHU_LPR_B150 }, /* B */ 160 { 300, DHU_LPR_B300 }, /* A and B */ 161 { 600, DHU_LPR_B600 }, /* A and B */ 162 { 1200, DHU_LPR_B1200 }, /* A and B */ 163 { 1800, DHU_LPR_B1800 }, /* B */ 164 { 2000, DHU_LPR_B2000 }, /* B */ 165 { 2400, DHU_LPR_B2400 }, /* A and B */ 166 { 4800, DHU_LPR_B4800 }, /* A and B */ 167 { 7200, DHU_LPR_B7200 }, /* A */ 168 { 9600, DHU_LPR_B9600 }, /* A and B */ 169 { 19200, DHU_LPR_B19200 }, /* B */ 170 { 38400, DHU_LPR_B38400 }, /* A */ 171 { -1, -1 } 172 }; 173 174 static int dhu_match(struct device *, struct cfdata *, void *); 175 static void dhu_attach(struct device *, struct device *, void *); 176 static void dhurint(void *); 177 static void dhuxint(void *); 178 static void dhustart(struct tty *); 179 static int dhuparam(struct tty *, struct termios *); 180 static int dhuiflow(struct tty *, int); 181 static unsigned dhumctl(struct dhu_softc *,int, int, int); 182 183 CFATTACH_DECL(dhu, sizeof(struct dhu_softc), 184 dhu_match, dhu_attach, NULL, NULL); 185 186 dev_type_open(dhuopen); 187 dev_type_close(dhuclose); 188 dev_type_read(dhuread); 189 dev_type_write(dhuwrite); 190 dev_type_ioctl(dhuioctl); 191 dev_type_stop(dhustop); 192 dev_type_tty(dhutty); 193 dev_type_poll(dhupoll); 194 195 const struct cdevsw dhu_cdevsw = { 196 dhuopen, dhuclose, dhuread, dhuwrite, dhuioctl, 197 dhustop, dhutty, dhupoll, nommap, ttykqfilter, D_TTY 198 }; 199 200 /* Autoconfig handles: setup the controller to interrupt, */ 201 /* then complete the housecleaning for full operation */ 202 203 static int 204 dhu_match(parent, cf, aux) 205 struct device *parent; 206 struct cfdata *cf; 207 void *aux; 208 { 209 struct uba_attach_args *ua = aux; 210 int n; 211 212 /* Reset controller to initialize, enable TX/RX interrupts */ 213 /* to catch floating vector info elsewhere when completed */ 214 215 bus_space_write_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR, 216 DHU_CSR_MASTER_RESET | DHU_CSR_RXIE | DHU_CSR_TXIE); 217 218 /* Now wait up to 3 seconds for self-test to complete. */ 219 220 for (n = 0; n < 300; n++) { 221 DELAY(10000); 222 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 223 DHU_CSR_MASTER_RESET) == 0) 224 break; 225 } 226 227 /* If the RESET did not clear after 3 seconds, */ 228 /* the controller must be broken. */ 229 230 if (n >= 300) 231 return 0; 232 233 /* Check whether diagnostic run has signalled a failure. */ 234 235 if ((bus_space_read_2(ua->ua_iot, ua->ua_ioh, DHU_UBA_CSR) & 236 DHU_CSR_DIAG_FAIL) != 0) 237 return 0; 238 239 return 1; 240 } 241 242 static void 243 dhu_attach(parent, self, aux) 244 struct device *parent, *self; 245 void *aux; 246 { 247 struct dhu_softc *sc = device_private(self); 248 struct uba_attach_args *ua = aux; 249 unsigned c; 250 int n, i; 251 252 sc->sc_iot = ua->ua_iot; 253 sc->sc_ioh = ua->ua_ioh; 254 sc->sc_dmat = ua->ua_dmat; 255 /* Process the 8 bytes of diagnostic info put into */ 256 /* the FIFO following the master reset operation. */ 257 258 printf("\n%s:", self->dv_xname); 259 for (n = 0; n < 8; n++) { 260 c = DHU_READ_WORD(DHU_UBA_RBUF); 261 262 if ((c&DHU_DIAG_CODE) == DHU_DIAG_CODE) { 263 if ((c&0200) == 0000) 264 printf(" rom(%d) version %d", 265 ((c>>1)&01), ((c>>2)&037)); 266 else if (((c>>2)&07) != 0) 267 printf(" diag-error(proc%d)=%x", 268 ((c>>1)&01), ((c>>2)&07)); 269 } 270 } 271 272 c = DHU_READ_WORD(DHU_UBA_STAT); 273 274 sc->sc_type = (c & DHU_STAT_DHU)? IS_DHU: IS_DHV; 275 276 sc->sc_lines = 8; /* default */ 277 if (sc->sc_type == IS_DHU && (c & DHU_STAT_MDL)) 278 sc->sc_lines = 16; 279 280 printf("\n%s: DH%s-11\n", self->dv_xname, 281 sc->sc_type == IS_DHU ? "U" : "V"); 282 283 for (i = 0; i < sc->sc_lines; i++) { 284 struct tty *tp; 285 tp = sc->sc_dhu[i].dhu_tty = ttymalloc(); 286 sc->sc_dhu[i].dhu_state = STATE_IDLE; 287 bus_dmamap_create(sc->sc_dmat, tp->t_outq.c_cn, 1, 288 tp->t_outq.c_cn, 0, BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, 289 &sc->sc_dhu[i].dhu_dmah); 290 bus_dmamap_load(sc->sc_dmat, sc->sc_dhu[i].dhu_dmah, 291 tp->t_outq.c_cs, tp->t_outq.c_cn, 0, BUS_DMA_NOWAIT); 292 293 } 294 295 /* Now establish RX & TX interrupt handlers */ 296 297 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, 298 dhurint, sc, &sc->sc_rintrcnt); 299 uba_intr_establish(ua->ua_icookie, ua->ua_cvec + 4, 300 dhuxint, sc, &sc->sc_tintrcnt); 301 evcnt_attach_dynamic(&sc->sc_rintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 302 sc->sc_dev.dv_xname, "rintr"); 303 evcnt_attach_dynamic(&sc->sc_tintrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 304 sc->sc_dev.dv_xname, "tintr"); 305 } 306 307 /* Receiver Interrupt */ 308 309 static void 310 dhurint(arg) 311 void *arg; 312 { 313 struct dhu_softc *sc = arg; 314 struct tty *tp; 315 int cc, line; 316 unsigned c, delta; 317 int overrun = 0; 318 319 while ((c = DHU_READ_WORD(DHU_UBA_RBUF)) & DHU_RBUF_DATA_VALID) { 320 321 /* Ignore diagnostic FIFO entries. */ 322 323 if ((c & DHU_DIAG_CODE) == DHU_DIAG_CODE) 324 continue; 325 326 cc = c & 0xFF; 327 line = DHU_LINE(c>>8); 328 tp = sc->sc_dhu[line].dhu_tty; 329 330 /* LINK.TYPE is set so we get modem control FIFO entries */ 331 332 if ((c & DHU_DIAG_CODE) == DHU_MODEM_CODE) { 333 c = (c << 8); 334 /* Do MDMBUF flow control, wakeup sleeping opens */ 335 if (c & DHU_STAT_DCD) { 336 if (!(tp->t_state & TS_CARR_ON)) 337 (void)(*tp->t_linesw->l_modem)(tp, 1); 338 } 339 else if ((tp->t_state & TS_CARR_ON) && 340 (*tp->t_linesw->l_modem)(tp, 0) == 0) 341 (void) dhumctl(sc, line, 0, DMSET); 342 343 /* Do CRTSCTS flow control */ 344 delta = c ^ sc->sc_dhu[line].dhu_modem; 345 sc->sc_dhu[line].dhu_modem = c; 346 if ((delta & DHU_STAT_CTS) && 347 (tp->t_state & TS_ISOPEN) && 348 (tp->t_cflag & CRTSCTS)) { 349 if (c & DHU_STAT_CTS) { 350 tp->t_state &= ~TS_TTSTOP; 351 ttstart(tp); 352 } else { 353 tp->t_state |= TS_TTSTOP; 354 dhustop(tp, 0); 355 } 356 } 357 continue; 358 } 359 360 if (!(tp->t_state & TS_ISOPEN)) { 361 wakeup((void *)&tp->t_rawq); 362 continue; 363 } 364 365 if ((c & DHU_RBUF_OVERRUN_ERR) && overrun == 0) { 366 log(LOG_WARNING, "%s: silo overflow, line %d\n", 367 sc->sc_dev.dv_xname, line); 368 overrun = 1; 369 } 370 /* A BREAK key will appear as a NULL with a framing error */ 371 if (c & DHU_RBUF_FRAMING_ERR) 372 cc |= TTY_FE; 373 if (c & DHU_RBUF_PARITY_ERR) 374 cc |= TTY_PE; 375 376 (*tp->t_linesw->l_rint)(cc, tp); 377 } 378 } 379 380 /* Transmitter Interrupt */ 381 382 static void 383 dhuxint(arg) 384 void *arg; 385 { 386 struct dhu_softc *sc = arg; 387 struct tty *tp; 388 int line, i; 389 390 while ((i = DHU_READ_BYTE(DHU_UBA_CSR_HI)) & (DHU_CSR_TX_ACTION >> 8)) { 391 392 line = DHU_LINE(i); 393 tp = sc->sc_dhu[line].dhu_tty; 394 395 if (i & (DHU_CSR_TX_DMA_ERROR >> 8)) 396 printf("%s: DMA ERROR on line: %d\n", 397 sc->sc_dev.dv_xname, line); 398 if (i & (DHU_CSR_DIAG_FAIL >> 8)) 399 printf("%s: DIAG FAIL on line: %d\n", 400 sc->sc_dev.dv_xname, line); 401 402 tp->t_state &= ~TS_BUSY; 403 if (tp->t_state & TS_FLUSH) 404 tp->t_state &= ~TS_FLUSH; 405 else { 406 if (sc->sc_dhu[line].dhu_state == STATE_DMA_STOPPED) 407 sc->sc_dhu[line].dhu_cc -= 408 DHU_READ_WORD(DHU_UBA_TBUFCNT); 409 ndflush(&tp->t_outq, sc->sc_dhu[line].dhu_cc); 410 sc->sc_dhu[line].dhu_cc = 0; 411 } 412 413 sc->sc_dhu[line].dhu_state = STATE_IDLE; 414 415 (*tp->t_linesw->l_start)(tp); 416 } 417 } 418 419 int 420 dhuopen(dev, flag, mode, l) 421 dev_t dev; 422 int flag, mode; 423 struct lwp *l; 424 { 425 struct tty *tp; 426 int unit, line; 427 struct dhu_softc *sc; 428 int error = 0; 429 430 unit = DHU_M2U(minor(dev)); 431 line = DHU_LINE(minor(dev)); 432 433 if (unit >= dhu_cd.cd_ndevs || dhu_cd.cd_devs[unit] == NULL) 434 return (ENXIO); 435 436 sc = dhu_cd.cd_devs[unit]; 437 438 if (line >= sc->sc_lines) 439 return ENXIO; 440 441 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 442 return (EBUSY); 443 444 mutex_spin_enter(&tty_lock); 445 if (sc->sc_type == IS_DHU) { 446 /* CSR 3:0 must be 0 */ 447 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE); 448 /* RX int delay 10ms */ 449 DHU_WRITE_BYTE(DHU_UBA_RXTIME, 10); 450 } 451 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 452 sc->sc_dhu[line].dhu_modem = DHU_READ_WORD(DHU_UBA_STAT); 453 454 tp = sc->sc_dhu[line].dhu_tty; 455 tp->t_oproc = dhustart; 456 tp->t_param = dhuparam; 457 tp->t_hwiflow = dhuiflow; 458 tp->t_dev = dev; 459 460 if ((tp->t_state & TS_ISOPEN) == 0) { 461 ttychars(tp); 462 if (tp->t_ispeed == 0) { 463 tp->t_iflag = TTYDEF_IFLAG; 464 tp->t_oflag = TTYDEF_OFLAG; 465 tp->t_cflag = TTYDEF_CFLAG; 466 tp->t_lflag = TTYDEF_LFLAG; 467 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED; 468 } 469 (void) dhuparam(tp, &tp->t_termios); 470 ttsetwater(tp); 471 } 472 /* Use DMBIS and *not* DMSET or else we clobber incoming bits */ 473 if (dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS) & DML_DCD) 474 tp->t_state |= TS_CARR_ON; 475 while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) && 476 !(tp->t_state & TS_CARR_ON)) { 477 tp->t_wopen++; 478 error = ttysleep(tp, &tp->t_rawq.c_cv, true, 0); 479 tp->t_wopen--; 480 if (error) 481 break; 482 } 483 mutex_spin_exit(&tty_lock); 484 if (error) 485 return (error); 486 return ((*tp->t_linesw->l_open)(dev, tp)); 487 } 488 489 /*ARGSUSED*/ 490 int 491 dhuclose(dev, flag, mode, l) 492 dev_t dev; 493 int flag, mode; 494 struct lwp *l; 495 { 496 struct tty *tp; 497 int unit, line; 498 struct dhu_softc *sc; 499 500 unit = DHU_M2U(minor(dev)); 501 line = DHU_LINE(minor(dev)); 502 503 sc = dhu_cd.cd_devs[unit]; 504 505 tp = sc->sc_dhu[line].dhu_tty; 506 507 (*tp->t_linesw->l_close)(tp, flag); 508 509 /* Make sure a BREAK state is not left enabled. */ 510 511 (void) dhumctl(sc, line, DML_BRK, DMBIC); 512 513 /* Do a hangup if so required. */ 514 515 if ((tp->t_cflag & HUPCL) || tp->t_wopen || 516 !(tp->t_state & TS_ISOPEN)) 517 (void) dhumctl(sc, line, 0, DMSET); 518 519 return (ttyclose(tp)); 520 } 521 522 int 523 dhuread(dev, uio, flag) 524 dev_t dev; 525 struct uio *uio; 526 int flag; 527 { 528 struct dhu_softc *sc; 529 struct tty *tp; 530 531 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 532 533 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 534 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 535 } 536 537 int 538 dhuwrite(dev, uio, flag) 539 dev_t dev; 540 struct uio *uio; 541 int flag; 542 { 543 struct dhu_softc *sc; 544 struct tty *tp; 545 546 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 547 548 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 549 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 550 } 551 552 int 553 dhupoll(dev, events, l) 554 dev_t dev; 555 int events; 556 struct lwp *l; 557 { 558 struct dhu_softc *sc; 559 struct tty *tp; 560 561 sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 562 563 tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 564 return ((*tp->t_linesw->l_poll)(tp, events, l)); 565 } 566 567 /*ARGSUSED*/ 568 int 569 dhuioctl(dev, cmd, data, flag, l) 570 dev_t dev; 571 u_long cmd; 572 void *data; 573 int flag; 574 struct lwp *l; 575 { 576 struct dhu_softc *sc; 577 struct tty *tp; 578 int unit, line; 579 int error; 580 581 unit = DHU_M2U(minor(dev)); 582 line = DHU_LINE(minor(dev)); 583 sc = dhu_cd.cd_devs[unit]; 584 tp = sc->sc_dhu[line].dhu_tty; 585 586 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 587 if (error != EPASSTHROUGH) 588 return (error); 589 590 error = ttioctl(tp, cmd, data, flag, l); 591 if (error != EPASSTHROUGH) 592 return (error); 593 594 switch (cmd) { 595 596 case TIOCSBRK: 597 (void) dhumctl(sc, line, DML_BRK, DMBIS); 598 break; 599 600 case TIOCCBRK: 601 (void) dhumctl(sc, line, DML_BRK, DMBIC); 602 break; 603 604 case TIOCSDTR: 605 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIS); 606 break; 607 608 case TIOCCDTR: 609 (void) dhumctl(sc, line, DML_DTR|DML_RTS, DMBIC); 610 break; 611 612 case TIOCMSET: 613 (void) dhumctl(sc, line, *(int *)data, DMSET); 614 break; 615 616 case TIOCMBIS: 617 (void) dhumctl(sc, line, *(int *)data, DMBIS); 618 break; 619 620 case TIOCMBIC: 621 (void) dhumctl(sc, line, *(int *)data, DMBIC); 622 break; 623 624 case TIOCMGET: 625 *(int *)data = (dhumctl(sc, line, 0, DMGET) & ~DML_BRK); 626 break; 627 628 default: 629 return (EPASSTHROUGH); 630 } 631 return (0); 632 } 633 634 struct tty * 635 dhutty(dev) 636 dev_t dev; 637 { 638 struct dhu_softc *sc = dhu_cd.cd_devs[DHU_M2U(minor(dev))]; 639 struct tty *tp = sc->sc_dhu[DHU_LINE(minor(dev))].dhu_tty; 640 return (tp); 641 } 642 643 /*ARGSUSED*/ 644 void 645 dhustop(tp, flag) 646 struct tty *tp; 647 int flag; 648 { 649 struct dhu_softc *sc; 650 int line; 651 int s; 652 653 s = spltty(); 654 655 if (tp->t_state & TS_BUSY) { 656 657 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 658 line = DHU_LINE(minor(tp->t_dev)); 659 660 if (sc->sc_dhu[line].dhu_state == STATE_DMA_RUNNING) { 661 662 sc->sc_dhu[line].dhu_state = STATE_DMA_STOPPED; 663 664 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 665 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 666 DHU_READ_WORD(DHU_UBA_LNCTRL) | 667 DHU_LNCTRL_DMA_ABORT); 668 } 669 670 if (!(tp->t_state & TS_TTSTOP)) 671 tp->t_state |= TS_FLUSH; 672 } 673 (void) splx(s); 674 } 675 676 static void 677 dhustart(tp) 678 struct tty *tp; 679 { 680 struct dhu_softc *sc; 681 int line, cc; 682 int addr; 683 int s; 684 685 s = spltty(); 686 if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP)) 687 goto out; 688 if (tp->t_outq.c_cc <= tp->t_lowat) { 689 if (tp->t_state & TS_ASLEEP) { 690 tp->t_state &= ~TS_ASLEEP; 691 wakeup((void *)&tp->t_outq); 692 } 693 selwakeup(&tp->t_wsel); 694 } 695 if (tp->t_outq.c_cc == 0) 696 goto out; 697 cc = ndqb(&tp->t_outq, 0); 698 if (cc == 0) 699 goto out; 700 701 tp->t_state |= TS_BUSY; 702 703 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 704 705 line = DHU_LINE(minor(tp->t_dev)); 706 707 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 708 709 sc->sc_dhu[line].dhu_cc = cc; 710 711 if (cc == 1 && sc->sc_type == IS_DHV) { 712 713 sc->sc_dhu[line].dhu_state = STATE_TX_ONE_CHAR; 714 715 DHU_WRITE_WORD(DHU_UBA_TXCHAR, 716 DHU_TXCHAR_DATA_VALID | *tp->t_outq.c_cf); 717 718 } else { 719 720 sc->sc_dhu[line].dhu_state = STATE_DMA_RUNNING; 721 722 addr = sc->sc_dhu[line].dhu_dmah->dm_segs[0].ds_addr + 723 (tp->t_outq.c_cf - tp->t_outq.c_cs); 724 725 DHU_WRITE_WORD(DHU_UBA_TBUFCNT, cc); 726 DHU_WRITE_WORD(DHU_UBA_TBUFAD1, addr & 0xFFFF); 727 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, ((addr>>16) & 0x3F) | 728 DHU_TBUFAD2_TX_ENABLE); 729 DHU_WRITE_WORD(DHU_UBA_LNCTRL, 730 DHU_READ_WORD(DHU_UBA_LNCTRL) & ~DHU_LNCTRL_DMA_ABORT); 731 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 732 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_DMA_START); 733 } 734 out: 735 (void) splx(s); 736 return; 737 } 738 739 static int 740 dhuparam(tp, t) 741 struct tty *tp; 742 struct termios *t; 743 { 744 struct dhu_softc *sc; 745 int cflag = t->c_cflag; 746 int ispeed = ttspeedtab(t->c_ispeed, dhuspeedtab); 747 int ospeed = ttspeedtab(t->c_ospeed, dhuspeedtab); 748 unsigned lpr, lnctrl; 749 int unit, line; 750 int s; 751 752 unit = DHU_M2U(minor(tp->t_dev)); 753 line = DHU_LINE(minor(tp->t_dev)); 754 755 sc = dhu_cd.cd_devs[unit]; 756 757 /* check requested parameters */ 758 if (ospeed < 0 || ispeed < 0) 759 return (EINVAL); 760 761 tp->t_ispeed = t->c_ispeed; 762 tp->t_ospeed = t->c_ospeed; 763 tp->t_cflag = cflag; 764 765 if (ospeed == 0) { 766 (void) dhumctl(sc, line, 0, DMSET); /* hang up line */ 767 return (0); 768 } 769 770 s = spltty(); 771 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 772 773 lpr = ((ispeed&017)<<8) | ((ospeed&017)<<12) ; 774 775 switch (cflag & CSIZE) { 776 777 case CS5: 778 lpr |= DHU_LPR_5_BIT_CHAR; 779 break; 780 781 case CS6: 782 lpr |= DHU_LPR_6_BIT_CHAR; 783 break; 784 785 case CS7: 786 lpr |= DHU_LPR_7_BIT_CHAR; 787 break; 788 789 default: 790 lpr |= DHU_LPR_8_BIT_CHAR; 791 break; 792 } 793 794 if (cflag & PARENB) 795 lpr |= DHU_LPR_PARENB; 796 if (!(cflag & PARODD)) 797 lpr |= DHU_LPR_EPAR; 798 if (cflag & CSTOPB) 799 lpr |= DHU_LPR_2_STOP; 800 801 DHU_WRITE_WORD(DHU_UBA_LPR, lpr); 802 803 DHU_WRITE_WORD(DHU_UBA_TBUFAD2, 804 DHU_READ_WORD(DHU_UBA_TBUFAD2) | DHU_TBUFAD2_TX_ENABLE); 805 806 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 807 808 /* Setting LINK.TYPE enables modem signal change interrupts. */ 809 810 lnctrl |= (DHU_LNCTRL_RX_ENABLE | DHU_LNCTRL_LINK_TYPE); 811 812 /* Enable the auto XON/XOFF feature on the controller */ 813 814 if (t->c_iflag & IXON) 815 lnctrl |= DHU_LNCTRL_OAUTO; 816 else 817 lnctrl &= ~DHU_LNCTRL_OAUTO; 818 819 if (t->c_iflag & IXOFF) 820 lnctrl |= DHU_LNCTRL_IAUTO; 821 else 822 lnctrl &= ~DHU_LNCTRL_IAUTO; 823 824 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 825 826 (void) splx(s); 827 return (0); 828 } 829 830 static int 831 dhuiflow(tp, flag) 832 struct tty *tp; 833 int flag; 834 { 835 struct dhu_softc *sc; 836 int line = DHU_LINE(minor(tp->t_dev)); 837 838 if (tp->t_cflag & CRTSCTS) { 839 sc = dhu_cd.cd_devs[DHU_M2U(minor(tp->t_dev))]; 840 (void) dhumctl(sc, line, DML_RTS, ((flag)? DMBIC: DMBIS)); 841 return (1); 842 } 843 return (0); 844 } 845 846 static unsigned 847 dhumctl(sc, line, bits, how) 848 struct dhu_softc *sc; 849 int line, bits, how; 850 { 851 unsigned status; 852 unsigned lnctrl; 853 unsigned mbits; 854 int s; 855 856 s = spltty(); 857 858 DHU_WRITE_BYTE(DHU_UBA_CSR, DHU_CSR_RXIE | line); 859 860 mbits = 0; 861 862 /* external signals as seen from the port */ 863 864 status = DHU_READ_WORD(DHU_UBA_STAT); 865 866 if (status & DHU_STAT_CTS) 867 mbits |= DML_CTS; 868 869 if (status & DHU_STAT_DCD) 870 mbits |= DML_DCD; 871 872 if (status & DHU_STAT_DSR) 873 mbits |= DML_DSR; 874 875 if (status & DHU_STAT_RI) 876 mbits |= DML_RI; 877 878 /* internal signals/state delivered to port */ 879 880 lnctrl = DHU_READ_WORD(DHU_UBA_LNCTRL); 881 882 if (lnctrl & DHU_LNCTRL_RTS) 883 mbits |= DML_RTS; 884 885 if (lnctrl & DHU_LNCTRL_DTR) 886 mbits |= DML_DTR; 887 888 if (lnctrl & DHU_LNCTRL_BREAK) 889 mbits |= DML_BRK; 890 891 switch (how) { 892 893 case DMSET: 894 mbits = bits; 895 break; 896 897 case DMBIS: 898 mbits |= bits; 899 break; 900 901 case DMBIC: 902 mbits &= ~bits; 903 break; 904 905 case DMGET: 906 (void) splx(s); 907 return (mbits); 908 } 909 910 if (mbits & DML_RTS) 911 lnctrl |= DHU_LNCTRL_RTS; 912 else 913 lnctrl &= ~DHU_LNCTRL_RTS; 914 915 if (mbits & DML_DTR) 916 lnctrl |= DHU_LNCTRL_DTR; 917 else 918 lnctrl &= ~DHU_LNCTRL_DTR; 919 920 if (mbits & DML_BRK) 921 lnctrl |= DHU_LNCTRL_BREAK; 922 else 923 lnctrl &= ~DHU_LNCTRL_BREAK; 924 925 DHU_WRITE_WORD(DHU_UBA_LNCTRL, lnctrl); 926 927 (void) splx(s); 928 return (mbits); 929 } 930
Indexes created Tue Sep 23 07:09:52 GMT 2025