Home | History | Annotate | Line # | Download | only in qbus
dz_uba.c revision 1.10.2.1 
      1 /*	$NetBSD: dz_uba.c,v 1.10.2.1 2000/06/22 17:07:50 minoura Exp $ */
      2 /*
      3  * Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved.
      4  * Copyright (c) 1996  Ken C. Wellsch.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *      This product includes software developed at Ludd, University of
     17  *      Lule}, Sweden and its contributors.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #include <sys/param.h>
     34 #include <sys/systm.h>
     35 #include <sys/ioctl.h>
     36 #include <sys/tty.h>
     37 #include <sys/proc.h>
     38 #include <sys/map.h>
     39 #include <sys/buf.h>
     40 #include <sys/conf.h>
     41 #include <sys/file.h>
     42 #include <sys/uio.h>
     43 #include <sys/kernel.h>
     44 #include <sys/syslog.h>
     45 #include <sys/device.h>
     46 
     47 #include <machine/bus.h>
     48 #include <machine/pte.h>
     49 #include <machine/trap.h>
     50 #include <machine/scb.h>
     51 
     52 #include <dev/qbus/ubavar.h>
     53 
     54 #include <dev/qbus/dzreg.h>
     55 #include <dev/qbus/dzvar.h>
     56 
     57 #include "ioconf.h"
     58 
     59 static	int	dz_uba_match __P((struct device *, struct cfdata *, void *));
     60 static	void	dz_uba_attach __P((struct device *, struct device *, void *));
     61 
     62 struct	cfattach dz_uba_ca = {
     63 	sizeof(struct dz_softc), dz_uba_match, dz_uba_attach
     64 };
     65 
     66 /* Autoconfig handles: setup the controller to interrupt, */
     67 /* then complete the housecleaning for full operation */
     68 
     69 static int
     70 dz_uba_match(parent, cf, aux)
     71         struct device *parent;
     72 	struct cfdata *cf;
     73         void *aux;
     74 {
     75 	struct uba_attach_args *ua = aux;
     76 	bus_space_tag_t	iot = ua->ua_iot;
     77 	bus_space_handle_t ioh = ua->ua_ioh;
     78 	int n;
     79 
     80 	iot = iot; /* Silly GCC */
     81 	/* Reset controller to initialize, enable TX interrupts */
     82 	/* to catch floating vector info elsewhere when completed */
     83 
     84 	bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_MSE | DZ_CSR_TXIE);
     85 	bus_space_write_1(iot, ioh, DZ_UBA_TCR, 1);
     86 
     87 	DELAY(100000);	/* delay 1/10 second */
     88 
     89 	bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_RESET);
     90 
     91 	/* Now wait up to 3 seconds for reset/clear to complete. */
     92 
     93 	for (n = 0; n < 300; n++) {
     94 		DELAY(10000);
     95 		if ((bus_space_read_2(iot, ioh, DZ_UBA_CSR)&DZ_CSR_RESET) == 0)
     96 			break;
     97 	}
     98 
     99 	/* If the RESET did not clear after 3 seconds, */
    100 	/* the controller must be broken. */
    101 
    102 	if (n >= 300)
    103 		return (0);
    104 
    105 	/* Register the TX interrupt handler */
    106 
    107 
    108        	return (1);
    109 }
    110 
    111 static void
    112 dz_uba_attach(parent, self, aux)
    113         struct device *parent, *self;
    114         void *aux;
    115 {
    116 	struct dz_softc *sc = (void *)self;
    117 	struct uba_attach_args *ua = aux;
    118 
    119 	sc->sc_iot = ua->ua_iot;
    120 	sc->sc_ioh = ua->ua_ioh;
    121 
    122 	sc->sc_dr.dr_csr = DZ_UBA_CSR;
    123 	sc->sc_dr.dr_rbuf = DZ_UBA_RBUF;
    124 	sc->sc_dr.dr_dtr = DZ_UBA_DTR;
    125 	sc->sc_dr.dr_break = DZ_UBA_BREAK;
    126 	sc->sc_dr.dr_tbuf = DZ_UBA_TBUF;
    127 	sc->sc_dr.dr_tcr = DZ_UBA_TCR;
    128 	sc->sc_dr.dr_dcd = DZ_UBA_DCD;
    129 	sc->sc_dr.dr_ring = DZ_UBA_RING;
    130 
    131 	sc->sc_type = DZ_DZ;
    132 
    133 	/* Now register the TX & RX interrupt handlers */
    134 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
    135 		dzxint, sc, &sc->sc_tintrcnt);
    136 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec - 4,
    137 		dzrint, sc, &sc->sc_rintrcnt);
    138 	uba_reset_establish(dzreset, self);
    139 
    140 	dzattach(sc, ua->ua_evcnt);
    141 }
    142