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dz_uba.c revision 1.29 
      1 /*	$NetBSD: dz_uba.c,v 1.29 2017/05/22 17:22:29 ragge Exp $ */
      2 /*
      3  * Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved.
      4  * Copyright (c) 1996  Ken C. Wellsch.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: dz_uba.c,v 1.29 2017/05/22 17:22:29 ragge Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/systm.h>
     34 #include <sys/ioctl.h>
     35 #include <sys/tty.h>
     36 #include <sys/proc.h>
     37 #include <sys/buf.h>
     38 #include <sys/conf.h>
     39 #include <sys/file.h>
     40 #include <sys/uio.h>
     41 #include <sys/kernel.h>
     42 #include <sys/syslog.h>
     43 #include <sys/device.h>
     44 
     45 #include <sys/bus.h>
     46 #include <machine/pte.h>
     47 #include <machine/trap.h>
     48 #include <machine/scb.h>
     49 
     50 #include <dev/qbus/ubavar.h>
     51 
     52 #include <dev/dec/dzreg.h>
     53 #include <dev/dec/dzvar.h>
     54 
     55 #include "ioconf.h"
     56 
     57 static	int	dz_uba_match(device_t, cfdata_t, void *);
     58 static	void	dz_uba_attach(device_t, device_t, void *);
     59 
     60 CFATTACH_DECL_NEW(dz_uba, sizeof(struct dz_softc),
     61     dz_uba_match, dz_uba_attach, NULL, NULL);
     62 
     63 /* Autoconfig handles: setup the controller to interrupt, */
     64 /* then complete the housecleaning for full operation */
     65 
     66 static int
     67 dz_uba_match(device_t parent, cfdata_t cf, void *aux)
     68 {
     69 	struct uba_attach_args *ua = aux;
     70 	bus_space_tag_t	iot = ua->ua_iot;
     71 	bus_space_handle_t ioh = ua->ua_ioh;
     72 	int n;
     73 
     74 	iot = iot; /* Silly GCC */
     75 	/* Reset controller to initialize, enable TX interrupts */
     76 	/* to catch floating vector info elsewhere when completed */
     77 
     78 	bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_MSE | DZ_CSR_TXIE);
     79 	bus_space_write_1(iot, ioh, DZ_UBA_TCR, 1);
     80 
     81 	DELAY(100000);	/* delay 1/10 second */
     82 
     83 	bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_RESET);
     84 
     85 	/* Now wait up to 3 seconds for reset/clear to complete. */
     86 
     87 	for (n = 0; n < 300; n++) {
     88 		DELAY(10000);
     89 		if ((bus_space_read_2(iot, ioh, DZ_UBA_CSR)&DZ_CSR_RESET) == 0)
     90 			break;
     91 	}
     92 
     93 	/* If the RESET did not clear after 3 seconds, */
     94 	/* the controller must be broken. */
     95 
     96 	if (n >= 300)
     97 		return (0);
     98 
     99 	/* Register the TX interrupt handler */
    100 
    101 
    102 	return (1);
    103 }
    104 
    105 static void
    106 dz_uba_attach(device_t parent, device_t self, void *aux)
    107 {
    108 	struct dz_softc *sc = device_private(self);
    109 	struct uba_attach_args *ua = aux;
    110 
    111 	sc->sc_dev = self;
    112 	sc->sc_iot = ua->ua_iot;
    113 	sc->sc_ioh = ua->ua_ioh;
    114 
    115 	sc->sc_dr.dr_csr = DZ_UBA_CSR;
    116 	sc->sc_dr.dr_rbuf = DZ_UBA_RBUF;
    117 	sc->sc_dr.dr_dtr = DZ_UBA_DTR;
    118 	sc->sc_dr.dr_break = DZ_UBA_BREAK;
    119 	sc->sc_dr.dr_tbuf = DZ_UBA_TBUF;
    120 	sc->sc_dr.dr_tcr = DZ_UBA_TCR;
    121 	sc->sc_dr.dr_dcd = DZ_UBA_DCD;
    122 	sc->sc_dr.dr_ring = DZ_UBA_RING;
    123 
    124 	sc->sc_dr.dr_firstreg = DZ_UBA_FIRSTREG;
    125 	sc->sc_dr.dr_winsize = DZ_UBA_WINSIZE;
    126 
    127 	sc->sc_type = DZ_DZ;
    128 
    129 	/* Now register the TX & RX interrupt handlers */
    130 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec,
    131 		dzxint, sc, &sc->sc_tintrcnt);
    132 	uba_intr_establish(ua->ua_icookie, ua->ua_cvec - 4,
    133 		dzrint, sc, &sc->sc_rintrcnt);
    134 	uba_reset_establish(dzreset, self);
    135 
    136 	dzattach(sc, ua->ua_evcnt, -1);
    137 }
    138