if_de.c revision 1.8 1 1.8 thorpej /* $NetBSD: if_de.c,v 1.8 2000/12/14 07:15:45 thorpej Exp $ */
2 1.5 ragge
3 1.1 ragge /*
4 1.1 ragge * Copyright (c) 1982, 1986, 1989 Regents of the University of California.
5 1.1 ragge * Copyright (c) 2000 Ludd, University of Lule}, Sweden.
6 1.1 ragge * All rights reserved.
7 1.1 ragge *
8 1.1 ragge *
9 1.1 ragge * Redistribution and use in source and binary forms, with or without
10 1.1 ragge * modification, are permitted provided that the following conditions
11 1.1 ragge * are met:
12 1.1 ragge * 1. Redistributions of source code must retain the above copyright
13 1.1 ragge * notice, this list of conditions and the following disclaimer.
14 1.1 ragge * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 ragge * notice, this list of conditions and the following disclaimer in the
16 1.1 ragge * documentation and/or other materials provided with the distribution.
17 1.1 ragge * 3. All advertising materials mentioning features or use of this software
18 1.1 ragge * must display the following acknowledgement:
19 1.1 ragge * This product includes software developed by the University of
20 1.1 ragge * California, Berkeley and its contributors.
21 1.1 ragge * 4. Neither the name of the University nor the names of its contributors
22 1.1 ragge * may be used to endorse or promote products derived from this software
23 1.1 ragge * without specific prior written permission.
24 1.1 ragge *
25 1.1 ragge * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 1.1 ragge * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 1.1 ragge * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 1.1 ragge * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 1.1 ragge * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 1.1 ragge * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 1.1 ragge * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 1.1 ragge * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 1.1 ragge * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 1.1 ragge * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 1.1 ragge * SUCH DAMAGE.
36 1.1 ragge *
37 1.1 ragge * @(#)if_de.c 7.12 (Berkeley) 12/16/90
38 1.1 ragge */
39 1.1 ragge
40 1.1 ragge /*
41 1.1 ragge * DEC DEUNA interface
42 1.1 ragge *
43 1.1 ragge * Lou Salkind
44 1.1 ragge * New York University
45 1.1 ragge *
46 1.2 ragge * Rewritten by Ragge 30 April 2000 to match new world.
47 1.1 ragge *
48 1.1 ragge * TODO:
49 1.1 ragge * timeout routine (get statistics)
50 1.1 ragge */
51 1.1 ragge
52 1.1 ragge #include "opt_inet.h"
53 1.2 ragge #include "bpfilter.h"
54 1.1 ragge
55 1.1 ragge #include <sys/param.h>
56 1.1 ragge #include <sys/systm.h>
57 1.1 ragge #include <sys/mbuf.h>
58 1.1 ragge #include <sys/buf.h>
59 1.1 ragge #include <sys/protosw.h>
60 1.1 ragge #include <sys/socket.h>
61 1.1 ragge #include <sys/ioctl.h>
62 1.1 ragge #include <sys/errno.h>
63 1.1 ragge #include <sys/syslog.h>
64 1.1 ragge #include <sys/device.h>
65 1.1 ragge
66 1.1 ragge #include <net/if.h>
67 1.1 ragge #include <net/if_ether.h>
68 1.1 ragge #include <net/if_dl.h>
69 1.1 ragge
70 1.1 ragge #ifdef INET
71 1.1 ragge #include <netinet/in.h>
72 1.1 ragge #include <netinet/if_inarp.h>
73 1.1 ragge #endif
74 1.1 ragge
75 1.2 ragge #if NBPFILTER > 0
76 1.2 ragge #include <net/bpf.h>
77 1.2 ragge #include <net/bpfdesc.h>
78 1.1 ragge #endif
79 1.1 ragge
80 1.1 ragge #include <machine/bus.h>
81 1.1 ragge
82 1.1 ragge #include <dev/qbus/ubavar.h>
83 1.1 ragge #include <dev/qbus/if_dereg.h>
84 1.1 ragge
85 1.1 ragge #include "ioconf.h"
86 1.1 ragge
87 1.1 ragge /*
88 1.1 ragge * Be careful with transmit/receive buffers, each entry steals 4 map
89 1.1 ragge * registers, and there is only 496 on one unibus...
90 1.1 ragge */
91 1.1 ragge #define NRCV 10 /* number of receive buffers (must be > 1) */
92 1.2 ragge #define NXMT 10 /* number of transmit buffers */
93 1.1 ragge
94 1.1 ragge /*
95 1.1 ragge * Structure containing the elements that must be in DMA-safe memory.
96 1.1 ragge */
97 1.1 ragge struct de_cdata {
98 1.1 ragge /* the following structures are always mapped in */
99 1.1 ragge struct de_pcbb dc_pcbb; /* port control block */
100 1.1 ragge struct de_ring dc_xrent[NXMT]; /* transmit ring entrys */
101 1.1 ragge struct de_ring dc_rrent[NRCV]; /* receive ring entrys */
102 1.1 ragge struct de_udbbuf dc_udbbuf; /* UNIBUS data buffer */
103 1.2 ragge char dc_xbuf[NXMT][ETHER_MAX_LEN];
104 1.1 ragge /* end mapped area */
105 1.1 ragge };
106 1.1 ragge
107 1.1 ragge /*
108 1.1 ragge * Ethernet software status per interface.
109 1.1 ragge *
110 1.1 ragge * Each interface is referenced by a network interface structure,
111 1.1 ragge * ds_if, which the routing code uses to locate the interface.
112 1.1 ragge * This structure contains the output queue for the interface, its address, ...
113 1.1 ragge * We also have, for each interface, a UBA interface structure, which
114 1.1 ragge * contains information about the UNIBUS resources held by the interface:
115 1.1 ragge * map registers, buffered data paths, etc. Information is cached in this
116 1.1 ragge * structure for use by the if_uba.c routines in running the interface
117 1.1 ragge * efficiently.
118 1.1 ragge */
119 1.1 ragge struct de_softc {
120 1.1 ragge struct device sc_dev; /* Configuration common part */
121 1.3 matt struct evcnt sc_intrcnt; /* Interrupt counting */
122 1.1 ragge struct ethercom sc_ec; /* Ethernet common part */
123 1.1 ragge #define sc_if sc_ec.ec_if /* network-visible interface */
124 1.1 ragge bus_space_tag_t sc_iot;
125 1.1 ragge bus_addr_t sc_ioh;
126 1.1 ragge bus_dma_tag_t sc_dmat;
127 1.2 ragge bus_dmamap_t sc_cmap;
128 1.1 ragge struct de_cdata *sc_dedata; /* Control structure */
129 1.1 ragge struct de_cdata *sc_pdedata; /* Bus-mapped control structure */
130 1.2 ragge bus_dmamap_t sc_rcvmap[NRCV]; /* unibus receive maps */
131 1.1 ragge struct mbuf *sc_rxmbuf[NRCV];
132 1.5 ragge int sc_xindex; /* UNA index into transmit chain */
133 1.5 ragge int sc_rindex; /* UNA index into receive chain */
134 1.5 ragge int sc_xfree; /* index for next transmit buffer */
135 1.5 ragge int sc_nxmit; /* # of transmits in progress */
136 1.2 ragge void *sc_sh; /* shutdownhook cookie */
137 1.1 ragge };
138 1.1 ragge
139 1.1 ragge static int dematch(struct device *, struct cfdata *, void *);
140 1.1 ragge static void deattach(struct device *, struct device *, void *);
141 1.2 ragge static void dewait(struct de_softc *, char *);
142 1.1 ragge static void deinit(struct de_softc *);
143 1.1 ragge static int deioctl(struct ifnet *, u_long, caddr_t);
144 1.1 ragge static void dereset(struct device *);
145 1.1 ragge static void destart(struct ifnet *);
146 1.1 ragge static void derecv(struct de_softc *);
147 1.1 ragge static void deintr(void *);
148 1.1 ragge static int de_add_rxbuf(struct de_softc *, int);
149 1.2 ragge static void deshutdown(void *);
150 1.1 ragge
151 1.1 ragge struct cfattach de_ca = {
152 1.1 ragge sizeof(struct de_softc), dematch, deattach
153 1.1 ragge };
154 1.1 ragge
155 1.1 ragge #define DE_WCSR(csr, val) \
156 1.1 ragge bus_space_write_2(sc->sc_iot, sc->sc_ioh, csr, val)
157 1.1 ragge #define DE_WLOW(val) \
158 1.1 ragge bus_space_write_1(sc->sc_iot, sc->sc_ioh, DE_PCSR0, val)
159 1.1 ragge #define DE_WHIGH(val) \
160 1.1 ragge bus_space_write_1(sc->sc_iot, sc->sc_ioh, DE_PCSR0 + 1, val)
161 1.1 ragge #define DE_RCSR(csr) \
162 1.1 ragge bus_space_read_2(sc->sc_iot, sc->sc_ioh, csr)
163 1.1 ragge
164 1.1 ragge #define LOWORD(x) ((int)(x) & 0xffff)
165 1.1 ragge #define HIWORD(x) (((int)(x) >> 16) & 0x3)
166 1.1 ragge /*
167 1.1 ragge * Interface exists: make available by filling in network interface
168 1.1 ragge * record. System will initialize the interface when it is ready
169 1.1 ragge * to accept packets. We get the ethernet address here.
170 1.1 ragge */
171 1.1 ragge void
172 1.1 ragge deattach(struct device *parent, struct device *self, void *aux)
173 1.1 ragge {
174 1.1 ragge struct uba_attach_args *ua = aux;
175 1.1 ragge struct de_softc *sc = (struct de_softc *)self;
176 1.1 ragge struct ifnet *ifp = &sc->sc_if;
177 1.1 ragge u_int8_t myaddr[ETHER_ADDR_LEN];
178 1.2 ragge int csr1, rseg, error, i;
179 1.1 ragge bus_dma_segment_t seg;
180 1.1 ragge char *c;
181 1.1 ragge
182 1.1 ragge sc->sc_iot = ua->ua_iot;
183 1.1 ragge sc->sc_ioh = ua->ua_ioh;
184 1.1 ragge sc->sc_dmat = ua->ua_dmat;
185 1.1 ragge
186 1.1 ragge /*
187 1.1 ragge * What kind of a board is this?
188 1.1 ragge * The error bits 4-6 in pcsr1 are a device id as long as
189 1.1 ragge * the high byte is zero.
190 1.1 ragge */
191 1.1 ragge csr1 = DE_RCSR(DE_PCSR1);
192 1.1 ragge if (csr1 & 0xff60)
193 1.1 ragge c = "broken";
194 1.1 ragge else if (csr1 & 0x10)
195 1.1 ragge c = "delua";
196 1.1 ragge else
197 1.1 ragge c = "deuna";
198 1.1 ragge
199 1.1 ragge /*
200 1.1 ragge * Reset the board and temporarily map
201 1.1 ragge * the pcbb buffer onto the Unibus.
202 1.1 ragge */
203 1.1 ragge DE_WCSR(DE_PCSR0, 0); /* reset INTE */
204 1.1 ragge DELAY(100);
205 1.1 ragge DE_WCSR(DE_PCSR0, PCSR0_RSET);
206 1.2 ragge dewait(sc, "reset");
207 1.1 ragge
208 1.1 ragge if ((error = bus_dmamem_alloc(sc->sc_dmat,
209 1.1 ragge sizeof(struct de_cdata), NBPG, 0, &seg, 1, &rseg,
210 1.1 ragge BUS_DMA_NOWAIT)) != 0) {
211 1.1 ragge printf(": unable to allocate control data, error = %d\n",
212 1.1 ragge error);
213 1.1 ragge goto fail_0;
214 1.1 ragge }
215 1.1 ragge if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
216 1.1 ragge sizeof(struct de_cdata), (caddr_t *)&sc->sc_dedata,
217 1.1 ragge BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
218 1.1 ragge printf(": unable to map control data, error = %d\n", error);
219 1.1 ragge goto fail_1;
220 1.1 ragge }
221 1.1 ragge
222 1.2 ragge if ((error = bus_dmamap_create(sc->sc_dmat, sizeof(struct de_cdata),
223 1.2 ragge 1, sizeof(struct de_cdata), 0, BUS_DMA_NOWAIT,
224 1.2 ragge &sc->sc_cmap)) != 0) {
225 1.2 ragge printf(": unable to create control data DMA map, error = %d\n",
226 1.2 ragge error);
227 1.2 ragge goto fail_2;
228 1.2 ragge }
229 1.2 ragge
230 1.2 ragge if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap,
231 1.2 ragge sc->sc_dedata, sizeof(struct de_cdata), NULL,
232 1.2 ragge BUS_DMA_NOWAIT)) != 0) {
233 1.2 ragge printf(": unable to load control data DMA map, error = %d\n",
234 1.2 ragge error);
235 1.2 ragge goto fail_3;
236 1.2 ragge }
237 1.2 ragge
238 1.2 ragge bzero(sc->sc_dedata, sizeof(struct de_cdata));
239 1.2 ragge sc->sc_pdedata = (struct de_cdata *)sc->sc_cmap->dm_segs[0].ds_addr;
240 1.2 ragge
241 1.1 ragge /*
242 1.1 ragge * Create receive buffer DMA maps.
243 1.1 ragge */
244 1.1 ragge for (i = 0; i < NRCV; i++) {
245 1.1 ragge if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
246 1.2 ragge MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
247 1.1 ragge &sc->sc_rcvmap[i]))) {
248 1.1 ragge printf(": unable to create rx DMA map %d, error = %d\n",
249 1.1 ragge i, error);
250 1.1 ragge goto fail_5;
251 1.1 ragge }
252 1.1 ragge }
253 1.1 ragge
254 1.1 ragge /*
255 1.1 ragge * Pre-allocate the receive buffers.
256 1.1 ragge */
257 1.1 ragge for (i = 0; i < NRCV; i++) {
258 1.1 ragge if ((error = de_add_rxbuf(sc, i)) != 0) {
259 1.1 ragge printf(": unable to allocate or map rx buffer %d\n,"
260 1.1 ragge " error = %d\n", i, error);
261 1.1 ragge goto fail_6;
262 1.1 ragge }
263 1.1 ragge }
264 1.1 ragge
265 1.1 ragge /*
266 1.1 ragge * Tell the DEUNA about our PCB
267 1.1 ragge */
268 1.1 ragge DE_WCSR(DE_PCSR2, LOWORD(sc->sc_pdedata));
269 1.1 ragge DE_WCSR(DE_PCSR3, HIWORD(sc->sc_pdedata));
270 1.1 ragge DE_WLOW(CMD_GETPCBB);
271 1.2 ragge dewait(sc, "pcbb");
272 1.1 ragge
273 1.1 ragge sc->sc_dedata->dc_pcbb.pcbb0 = FC_RDPHYAD;
274 1.1 ragge DE_WLOW(CMD_GETCMD);
275 1.2 ragge dewait(sc, "read addr ");
276 1.1 ragge
277 1.1 ragge bcopy((caddr_t)&sc->sc_dedata->dc_pcbb.pcbb2, myaddr, sizeof (myaddr));
278 1.2 ragge printf("\n%s: %s, hardware address %s\n", sc->sc_dev.dv_xname, c,
279 1.1 ragge ether_sprintf(myaddr));
280 1.1 ragge
281 1.5 ragge uba_intr_establish(ua->ua_icookie, ua->ua_cvec, deintr, sc,
282 1.5 ragge &sc->sc_intrcnt);
283 1.1 ragge uba_reset_establish(dereset, &sc->sc_dev);
284 1.4 matt evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
285 1.5 ragge sc->sc_dev.dv_xname, "intr");
286 1.1 ragge
287 1.1 ragge strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
288 1.1 ragge ifp->if_softc = sc;
289 1.5 ragge ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST|IFF_ALLMULTI;
290 1.1 ragge ifp->if_ioctl = deioctl;
291 1.1 ragge ifp->if_start = destart;
292 1.8 thorpej IFQ_SET_READY(&ifp->if_snd);
293 1.8 thorpej
294 1.1 ragge if_attach(ifp);
295 1.1 ragge ether_ifattach(ifp, myaddr);
296 1.7 thorpej
297 1.2 ragge sc->sc_sh = shutdownhook_establish(deshutdown, sc);
298 1.1 ragge return;
299 1.1 ragge
300 1.1 ragge /*
301 1.1 ragge * Free any resources we've allocated during the failed attach
302 1.1 ragge * attempt. Do this in reverse order and fall through.
303 1.1 ragge */
304 1.1 ragge fail_6:
305 1.1 ragge for (i = 0; i < NRCV; i++) {
306 1.1 ragge if (sc->sc_rxmbuf[i] != NULL) {
307 1.2 ragge bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]);
308 1.1 ragge m_freem(sc->sc_rxmbuf[i]);
309 1.1 ragge }
310 1.1 ragge }
311 1.1 ragge fail_5:
312 1.1 ragge for (i = 0; i < NRCV; i++) {
313 1.2 ragge if (sc->sc_rcvmap[i] != NULL)
314 1.2 ragge bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]);
315 1.1 ragge }
316 1.5 ragge
317 1.2 ragge fail_3:
318 1.2 ragge bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap);
319 1.2 ragge fail_2:
320 1.1 ragge bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dedata,
321 1.1 ragge sizeof(struct de_cdata));
322 1.1 ragge fail_1:
323 1.1 ragge bus_dmamem_free(sc->sc_dmat, &seg, rseg);
324 1.1 ragge fail_0:
325 1.1 ragge return;
326 1.1 ragge }
327 1.1 ragge
328 1.1 ragge /*
329 1.1 ragge * Reset of interface after UNIBUS reset.
330 1.1 ragge */
331 1.1 ragge void
332 1.1 ragge dereset(struct device *dev)
333 1.1 ragge {
334 1.1 ragge struct de_softc *sc = (void *)dev;
335 1.1 ragge
336 1.1 ragge sc->sc_if.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
337 1.5 ragge sc->sc_pdedata = NULL; /* All mappings lost */
338 1.1 ragge DE_WCSR(DE_PCSR0, PCSR0_RSET);
339 1.2 ragge dewait(sc, "reset");
340 1.1 ragge deinit(sc);
341 1.1 ragge }
342 1.1 ragge
343 1.1 ragge /*
344 1.1 ragge * Initialization of interface; clear recorded pending
345 1.1 ragge * operations, and reinitialize UNIBUS usage.
346 1.1 ragge */
347 1.1 ragge void
348 1.1 ragge deinit(struct de_softc *sc)
349 1.1 ragge {
350 1.2 ragge struct de_cdata *dc, *pdc;
351 1.1 ragge int s, i;
352 1.1 ragge
353 1.2 ragge if (sc->sc_if.if_flags & IFF_RUNNING)
354 1.1 ragge return;
355 1.1 ragge /*
356 1.1 ragge * Tell the DEUNA about our PCB
357 1.1 ragge */
358 1.1 ragge DE_WCSR(DE_PCSR2, LOWORD(sc->sc_pdedata));
359 1.1 ragge DE_WCSR(DE_PCSR3, HIWORD(sc->sc_pdedata));
360 1.1 ragge DE_WLOW(0); /* reset INTE */
361 1.1 ragge DELAY(500);
362 1.1 ragge DE_WLOW(CMD_GETPCBB);
363 1.2 ragge dewait(sc, "pcbb");
364 1.1 ragge
365 1.1 ragge dc = sc->sc_dedata;
366 1.2 ragge pdc = sc->sc_pdedata;
367 1.1 ragge /* set the transmit and receive ring header addresses */
368 1.1 ragge dc->dc_pcbb.pcbb0 = FC_WTRING;
369 1.2 ragge dc->dc_pcbb.pcbb2 = LOWORD(&pdc->dc_udbbuf);
370 1.2 ragge dc->dc_pcbb.pcbb4 = HIWORD(&pdc->dc_udbbuf);
371 1.1 ragge
372 1.2 ragge dc->dc_udbbuf.b_tdrbl = LOWORD(&pdc->dc_xrent[0]);
373 1.2 ragge dc->dc_udbbuf.b_tdrbh = HIWORD(&pdc->dc_xrent[0]);
374 1.1 ragge dc->dc_udbbuf.b_telen = sizeof (struct de_ring) / sizeof(u_int16_t);
375 1.1 ragge dc->dc_udbbuf.b_trlen = NXMT;
376 1.2 ragge dc->dc_udbbuf.b_rdrbl = LOWORD(&pdc->dc_rrent[0]);
377 1.2 ragge dc->dc_udbbuf.b_rdrbh = HIWORD(&pdc->dc_rrent[0]);
378 1.1 ragge dc->dc_udbbuf.b_relen = sizeof (struct de_ring) / sizeof(u_int16_t);
379 1.1 ragge dc->dc_udbbuf.b_rrlen = NRCV;
380 1.1 ragge
381 1.1 ragge DE_WLOW(CMD_GETCMD);
382 1.2 ragge dewait(sc, "wtring");
383 1.1 ragge
384 1.5 ragge sc->sc_dedata->dc_pcbb.pcbb0 = FC_WTMODE;
385 1.5 ragge sc->sc_dedata->dc_pcbb.pcbb2 = MOD_TPAD|MOD_HDX|MOD_DRDC|MOD_ENAL;
386 1.5 ragge DE_WLOW(CMD_GETCMD);
387 1.5 ragge dewait(sc, "wtmode");
388 1.1 ragge
389 1.5 ragge /* set up the receive and transmit ring entries */
390 1.1 ragge for (i = 0; i < NXMT; i++) {
391 1.1 ragge dc->dc_xrent[i].r_flags = 0;
392 1.2 ragge dc->dc_xrent[i].r_segbl = LOWORD(&pdc->dc_xbuf[i][0]);
393 1.2 ragge dc->dc_xrent[i].r_segbh = HIWORD(&pdc->dc_xbuf[i][0]);
394 1.1 ragge }
395 1.2 ragge
396 1.1 ragge for (i = 0; i < NRCV; i++)
397 1.1 ragge dc->dc_rrent[i].r_flags = RFLG_OWN;
398 1.1 ragge
399 1.1 ragge /* start up the board (rah rah) */
400 1.1 ragge s = splnet();
401 1.5 ragge sc->sc_rindex = sc->sc_xindex = sc->sc_xfree = sc->sc_nxmit = 0;
402 1.1 ragge sc->sc_if.if_flags |= IFF_RUNNING;
403 1.5 ragge DE_WLOW(PCSR0_INTE); /* avoid interlock */
404 1.5 ragge destart(&sc->sc_if); /* queue output packets */
405 1.1 ragge DE_WLOW(CMD_START|PCSR0_INTE);
406 1.1 ragge splx(s);
407 1.1 ragge }
408 1.1 ragge
409 1.1 ragge /*
410 1.1 ragge * Setup output on interface.
411 1.1 ragge * Get another datagram to send off of the interface queue,
412 1.1 ragge * and map it to the interface before starting the output.
413 1.1 ragge * Must be called from ipl >= our interrupt level.
414 1.1 ragge */
415 1.1 ragge void
416 1.1 ragge destart(struct ifnet *ifp)
417 1.1 ragge {
418 1.1 ragge struct de_softc *sc = ifp->if_softc;
419 1.2 ragge struct de_cdata *dc;
420 1.5 ragge struct de_ring *rp;
421 1.2 ragge struct mbuf *m;
422 1.5 ragge int nxmit;
423 1.1 ragge
424 1.1 ragge /*
425 1.1 ragge * the following test is necessary, since
426 1.1 ragge * the code is not reentrant and we have
427 1.1 ragge * multiple transmission buffers.
428 1.1 ragge */
429 1.5 ragge if (sc->sc_if.if_flags & IFF_OACTIVE)
430 1.1 ragge return;
431 1.2 ragge dc = sc->sc_dedata;
432 1.5 ragge for (nxmit = sc->sc_nxmit; nxmit < NXMT; nxmit++) {
433 1.8 thorpej IFQ_DEQUEUE(&ifp->if_snd, m);
434 1.1 ragge if (m == 0)
435 1.5 ragge break;
436 1.5 ragge rp = &dc->dc_xrent[sc->sc_xfree];
437 1.5 ragge if (rp->r_flags & XFLG_OWN)
438 1.5 ragge panic("deuna xmit in progress");
439 1.5 ragge m_copydata(m, 0, m->m_pkthdr.len, &dc->dc_xbuf[sc->sc_xfree][0]);
440 1.5 ragge rp->r_slen = m->m_pkthdr.len;
441 1.5 ragge rp->r_tdrerr = 0;
442 1.5 ragge rp->r_flags = XFLG_STP|XFLG_ENP|XFLG_OWN;
443 1.1 ragge
444 1.1 ragge #if NBPFILTER > 0
445 1.1 ragge if (ifp->if_bpf)
446 1.1 ragge bpf_mtap(ifp->if_bpf, m);
447 1.1 ragge #endif
448 1.5 ragge
449 1.2 ragge m_freem(m);
450 1.5 ragge sc->sc_xfree++;
451 1.5 ragge if (sc->sc_xfree == NXMT)
452 1.5 ragge sc->sc_xfree = 0;
453 1.5 ragge }
454 1.5 ragge if (sc->sc_nxmit != nxmit) {
455 1.5 ragge sc->sc_nxmit = nxmit;
456 1.5 ragge if (ifp->if_flags & IFF_RUNNING)
457 1.5 ragge DE_WLOW(PCSR0_INTE|CMD_PDMD);
458 1.1 ragge }
459 1.1 ragge }
460 1.1 ragge
461 1.1 ragge /*
462 1.1 ragge * Command done interrupt.
463 1.1 ragge */
464 1.1 ragge void
465 1.1 ragge deintr(void *arg)
466 1.1 ragge {
467 1.5 ragge struct de_cdata *dc;
468 1.1 ragge struct de_softc *sc = arg;
469 1.5 ragge struct de_ring *rp;
470 1.5 ragge short csr0;
471 1.1 ragge
472 1.1 ragge /* save flags right away - clear out interrupt bits */
473 1.1 ragge csr0 = DE_RCSR(DE_PCSR0);
474 1.1 ragge DE_WHIGH(csr0 >> 8);
475 1.1 ragge
476 1.1 ragge
477 1.5 ragge sc->sc_if.if_flags |= IFF_OACTIVE; /* prevent entering destart */
478 1.5 ragge /*
479 1.5 ragge * if receive, put receive buffer on mbuf
480 1.5 ragge * and hang the request again
481 1.5 ragge */
482 1.5 ragge derecv(sc);
483 1.1 ragge
484 1.1 ragge /*
485 1.1 ragge * Poll transmit ring and check status.
486 1.5 ragge * Be careful about loopback requests.
487 1.1 ragge * Then free buffer space and check for
488 1.1 ragge * more transmit requests.
489 1.1 ragge */
490 1.5 ragge dc = sc->sc_dedata;
491 1.5 ragge for ( ; sc->sc_nxmit > 0; sc->sc_nxmit--) {
492 1.5 ragge rp = &dc->dc_xrent[sc->sc_xindex];
493 1.5 ragge if (rp->r_flags & XFLG_OWN)
494 1.2 ragge break;
495 1.5 ragge sc->sc_if.if_opackets++;
496 1.5 ragge /* check for unusual conditions */
497 1.1 ragge if (rp->r_flags & (XFLG_ERRS|XFLG_MTCH|XFLG_ONE|XFLG_MORE)) {
498 1.1 ragge if (rp->r_flags & XFLG_ERRS) {
499 1.5 ragge /* output error */
500 1.5 ragge sc->sc_if.if_oerrors++;
501 1.1 ragge } else if (rp->r_flags & XFLG_ONE) {
502 1.5 ragge /* one collision */
503 1.5 ragge sc->sc_if.if_collisions++;
504 1.1 ragge } else if (rp->r_flags & XFLG_MORE) {
505 1.5 ragge /* more than one collision */
506 1.5 ragge sc->sc_if.if_collisions += 2; /* guess */
507 1.1 ragge }
508 1.1 ragge }
509 1.5 ragge /* check if next transmit buffer also finished */
510 1.5 ragge sc->sc_xindex++;
511 1.5 ragge if (sc->sc_xindex == NXMT)
512 1.5 ragge sc->sc_xindex = 0;
513 1.5 ragge }
514 1.5 ragge sc->sc_if.if_flags &= ~IFF_OACTIVE;
515 1.5 ragge destart(&sc->sc_if);
516 1.5 ragge
517 1.5 ragge if (csr0 & PCSR0_RCBI) {
518 1.5 ragge DE_WLOW(PCSR0_INTE|CMD_PDMD);
519 1.5 ragge }
520 1.1 ragge }
521 1.1 ragge
522 1.1 ragge /*
523 1.1 ragge * Ethernet interface receiver interface.
524 1.1 ragge * If input error just drop packet.
525 1.1 ragge * Otherwise purge input buffered data path and examine
526 1.1 ragge * packet to determine type. If can't determine length
527 1.1 ragge * from type, then have to drop packet. Othewise decapsulate
528 1.1 ragge * packet based on type and pass to type specific higher-level
529 1.1 ragge * input routine.
530 1.1 ragge */
531 1.1 ragge void
532 1.1 ragge derecv(struct de_softc *sc)
533 1.1 ragge {
534 1.1 ragge struct ifnet *ifp = &sc->sc_if;
535 1.1 ragge struct de_ring *rp;
536 1.5 ragge struct de_cdata *dc;
537 1.1 ragge struct mbuf *m;
538 1.1 ragge int len;
539 1.1 ragge
540 1.5 ragge dc = sc->sc_dedata;
541 1.5 ragge rp = &dc->dc_rrent[sc->sc_rindex];
542 1.1 ragge while ((rp->r_flags & RFLG_OWN) == 0) {
543 1.5 ragge sc->sc_if.if_ipackets++;
544 1.5 ragge len = (rp->r_lenerr&RERR_MLEN) - ETHER_CRC_LEN;
545 1.1 ragge /* check for errors */
546 1.1 ragge if ((rp->r_flags & (RFLG_ERRS|RFLG_FRAM|RFLG_OFLO|RFLG_CRC)) ||
547 1.2 ragge (rp->r_lenerr & (RERR_BUFL|RERR_UBTO))) {
548 1.5 ragge sc->sc_if.if_ierrors++;
549 1.1 ragge goto next;
550 1.1 ragge }
551 1.5 ragge m = sc->sc_rxmbuf[sc->sc_rindex];
552 1.1 ragge #if NBPFILTER > 0
553 1.6 thorpej if (ifp->if_bpf)
554 1.1 ragge bpf_mtap(ifp->if_bpf, m);
555 1.1 ragge #endif
556 1.5 ragge
557 1.5 ragge if (de_add_rxbuf(sc, sc->sc_rindex) == 0) {
558 1.5 ragge m->m_pkthdr.rcvif = ifp;
559 1.5 ragge m->m_pkthdr.len = m->m_len = len;
560 1.5 ragge (*ifp->if_input)(ifp, m);
561 1.5 ragge } else
562 1.5 ragge sc->sc_if.if_ierrors++;
563 1.1 ragge
564 1.1 ragge /* hang the receive buffer again */
565 1.1 ragge next: rp->r_lenerr = 0;
566 1.1 ragge rp->r_flags = RFLG_OWN;
567 1.1 ragge
568 1.1 ragge /* check next receive buffer */
569 1.5 ragge sc->sc_rindex++;
570 1.5 ragge if (sc->sc_rindex == NRCV)
571 1.5 ragge sc->sc_rindex = 0;
572 1.5 ragge rp = &dc->dc_rrent[sc->sc_rindex];
573 1.1 ragge }
574 1.1 ragge }
575 1.1 ragge
576 1.1 ragge /*
577 1.1 ragge * Add a receive buffer to the indicated descriptor.
578 1.1 ragge */
579 1.1 ragge int
580 1.1 ragge de_add_rxbuf(sc, i)
581 1.1 ragge struct de_softc *sc;
582 1.1 ragge int i;
583 1.1 ragge {
584 1.1 ragge struct mbuf *m;
585 1.1 ragge struct de_ring *rp;
586 1.1 ragge vaddr_t addr;
587 1.1 ragge int error;
588 1.1 ragge
589 1.1 ragge MGETHDR(m, M_DONTWAIT, MT_DATA);
590 1.1 ragge if (m == NULL)
591 1.1 ragge return (ENOBUFS);
592 1.1 ragge
593 1.1 ragge MCLGET(m, M_DONTWAIT);
594 1.1 ragge if ((m->m_flags & M_EXT) == 0) {
595 1.1 ragge m_freem(m);
596 1.1 ragge return (ENOBUFS);
597 1.1 ragge }
598 1.1 ragge
599 1.1 ragge if (sc->sc_rxmbuf[i] != NULL)
600 1.1 ragge bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]);
601 1.1 ragge
602 1.1 ragge error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i],
603 1.1 ragge m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
604 1.1 ragge if (error)
605 1.1 ragge panic("%s: can't load rx DMA map %d, error = %d\n",
606 1.1 ragge sc->sc_dev.dv_xname, i, error);
607 1.1 ragge sc->sc_rxmbuf[i] = m;
608 1.1 ragge
609 1.1 ragge bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0,
610 1.1 ragge sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD);
611 1.1 ragge
612 1.1 ragge /*
613 1.1 ragge * We know that the mbuf cluster is page aligned. Also, be sure
614 1.1 ragge * that the IP header will be longword aligned.
615 1.1 ragge */
616 1.1 ragge m->m_data += 2;
617 1.1 ragge addr = sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2;
618 1.1 ragge rp = &sc->sc_dedata->dc_rrent[i];
619 1.1 ragge rp->r_lenerr = 0;
620 1.1 ragge rp->r_segbl = LOWORD(addr);
621 1.1 ragge rp->r_segbh = HIWORD(addr);
622 1.1 ragge rp->r_slen = m->m_ext.ext_size - 2;
623 1.1 ragge rp->r_flags = RFLG_OWN;
624 1.1 ragge
625 1.1 ragge return (0);
626 1.1 ragge }
627 1.1 ragge
628 1.1 ragge
629 1.1 ragge /*
630 1.1 ragge * Process an ioctl request.
631 1.1 ragge */
632 1.1 ragge int
633 1.1 ragge deioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
634 1.1 ragge {
635 1.1 ragge struct ifaddr *ifa = (struct ifaddr *)data;
636 1.2 ragge struct ifreq *ifr = (struct ifreq *)data;
637 1.1 ragge struct de_softc *sc = ifp->if_softc;
638 1.1 ragge int s = splnet(), error = 0;
639 1.1 ragge
640 1.1 ragge switch (cmd) {
641 1.1 ragge
642 1.1 ragge case SIOCSIFADDR:
643 1.1 ragge ifp->if_flags |= IFF_UP;
644 1.1 ragge switch (ifa->ifa_addr->sa_family) {
645 1.1 ragge #ifdef INET
646 1.1 ragge case AF_INET:
647 1.2 ragge deinit(sc);
648 1.1 ragge arp_ifinit(ifp, ifa);
649 1.1 ragge break;
650 1.1 ragge #endif
651 1.1 ragge }
652 1.1 ragge break;
653 1.1 ragge
654 1.1 ragge case SIOCSIFFLAGS:
655 1.1 ragge if ((ifp->if_flags & IFF_UP) == 0 &&
656 1.2 ragge (ifp->if_flags & IFF_RUNNING) != 0) {
657 1.2 ragge /*
658 1.2 ragge * If interface is marked down and it is running,
659 1.2 ragge * stop it.
660 1.2 ragge */
661 1.5 ragge DE_WLOW(0);
662 1.5 ragge DELAY(5000);
663 1.5 ragge DE_WLOW(PCSR0_RSET);
664 1.2 ragge ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
665 1.2 ragge } else if ((ifp->if_flags & IFF_UP) != 0 &&
666 1.2 ragge (ifp->if_flags & IFF_RUNNING) == 0) {
667 1.2 ragge /*
668 1.2 ragge * If interface it marked up and it is stopped, then
669 1.2 ragge * start it.
670 1.2 ragge */
671 1.1 ragge deinit(sc);
672 1.2 ragge } else if ((ifp->if_flags & IFF_UP) != 0) {
673 1.2 ragge /*
674 1.2 ragge * Send a new setup packet to match any new changes.
675 1.2 ragge * (Like IFF_PROMISC etc)
676 1.2 ragge */
677 1.5 ragge sc->sc_dedata->dc_pcbb.pcbb0 = FC_WTMODE;
678 1.5 ragge sc->sc_dedata->dc_pcbb.pcbb2 =
679 1.5 ragge MOD_TPAD|MOD_HDX|MOD_DRDC|MOD_ENAL;
680 1.5 ragge if (ifp->if_flags & IFF_PROMISC)
681 1.5 ragge sc->sc_dedata->dc_pcbb.pcbb2 |= MOD_PROM;
682 1.5 ragge DE_WLOW(CMD_GETCMD|PCSR0_INTE);
683 1.5 ragge dewait(sc, "chgmode");
684 1.2 ragge }
685 1.2 ragge break;
686 1.2 ragge
687 1.2 ragge case SIOCADDMULTI:
688 1.2 ragge case SIOCDELMULTI:
689 1.2 ragge /*
690 1.2 ragge * Update our multicast list.
691 1.2 ragge */
692 1.2 ragge error = (cmd == SIOCADDMULTI) ?
693 1.2 ragge ether_addmulti(ifr, &sc->sc_ec):
694 1.2 ragge ether_delmulti(ifr, &sc->sc_ec);
695 1.2 ragge
696 1.2 ragge if (error == ENETRESET) {
697 1.2 ragge /*
698 1.2 ragge * Multicast list has changed; set the hardware filter
699 1.2 ragge * accordingly.
700 1.2 ragge */
701 1.2 ragge error = 0;
702 1.2 ragge }
703 1.1 ragge break;
704 1.1 ragge
705 1.1 ragge default:
706 1.1 ragge error = EINVAL;
707 1.1 ragge }
708 1.1 ragge splx(s);
709 1.1 ragge return (error);
710 1.1 ragge }
711 1.1 ragge
712 1.1 ragge /*
713 1.1 ragge * Await completion of the named function
714 1.1 ragge * and check for errors.
715 1.1 ragge */
716 1.2 ragge void
717 1.1 ragge dewait(struct de_softc *sc, char *fn)
718 1.1 ragge {
719 1.5 ragge int csr0;
720 1.1 ragge
721 1.1 ragge while ((DE_RCSR(DE_PCSR0) & PCSR0_INTR) == 0)
722 1.1 ragge ;
723 1.1 ragge csr0 = DE_RCSR(DE_PCSR0);
724 1.1 ragge DE_WHIGH(csr0 >> 8);
725 1.1 ragge if (csr0 & PCSR0_PCEI) {
726 1.1 ragge char bits[64];
727 1.1 ragge printf("%s: %s failed, csr0=%s ", sc->sc_dev.dv_xname, fn,
728 1.1 ragge bitmask_snprintf(csr0, PCSR0_BITS, bits, sizeof(bits)));
729 1.1 ragge printf("csr1=%s\n", bitmask_snprintf(DE_RCSR(DE_PCSR1),
730 1.1 ragge PCSR1_BITS, bits, sizeof(bits)));
731 1.1 ragge }
732 1.1 ragge }
733 1.1 ragge
734 1.1 ragge int
735 1.1 ragge dematch(struct device *parent, struct cfdata *cf, void *aux)
736 1.1 ragge {
737 1.1 ragge struct uba_attach_args *ua = aux;
738 1.1 ragge struct de_softc ssc;
739 1.1 ragge struct de_softc *sc = &ssc;
740 1.1 ragge int i;
741 1.1 ragge
742 1.1 ragge sc->sc_iot = ua->ua_iot;
743 1.1 ragge sc->sc_ioh = ua->ua_ioh;
744 1.1 ragge /*
745 1.1 ragge * Make sure self-test is finished before we screw with the board.
746 1.1 ragge * Self-test on a DELUA can take 15 seconds (argh).
747 1.1 ragge */
748 1.1 ragge for (i = 0;
749 1.1 ragge (i < 160) &&
750 1.1 ragge (DE_RCSR(DE_PCSR0) & PCSR0_FATI) == 0 &&
751 1.1 ragge (DE_RCSR(DE_PCSR1) & PCSR1_STMASK) == STAT_RESET;
752 1.1 ragge ++i)
753 1.1 ragge DELAY(50000);
754 1.1 ragge if (((DE_RCSR(DE_PCSR0) & PCSR0_FATI) != 0) ||
755 1.1 ragge (((DE_RCSR(DE_PCSR1) & PCSR1_STMASK) != STAT_READY) &&
756 1.1 ragge ((DE_RCSR(DE_PCSR1) & PCSR1_STMASK) != STAT_RUN)))
757 1.1 ragge return(0);
758 1.1 ragge
759 1.1 ragge DE_WCSR(DE_PCSR0, 0);
760 1.1 ragge DELAY(5000);
761 1.1 ragge DE_WCSR(DE_PCSR0, PCSR0_RSET);
762 1.1 ragge while ((DE_RCSR(DE_PCSR0) & PCSR0_INTR) == 0)
763 1.1 ragge ;
764 1.1 ragge /* make board interrupt by executing a GETPCBB command */
765 1.1 ragge DE_WCSR(DE_PCSR0, PCSR0_INTE);
766 1.1 ragge DE_WCSR(DE_PCSR2, 0);
767 1.1 ragge DE_WCSR(DE_PCSR3, 0);
768 1.1 ragge DE_WCSR(DE_PCSR0, PCSR0_INTE|CMD_GETPCBB);
769 1.1 ragge DELAY(50000);
770 1.1 ragge
771 1.1 ragge return 1;
772 1.1 ragge }
773 1.2 ragge
774 1.2 ragge void
775 1.2 ragge deshutdown(void *arg)
776 1.2 ragge {
777 1.2 ragge struct de_softc *sc = arg;
778 1.2 ragge
779 1.5 ragge DE_WCSR(DE_PCSR0, 0);
780 1.5 ragge DELAY(1000);
781 1.2 ragge DE_WCSR(DE_PCSR0, PCSR0_RSET);
782 1.2 ragge dewait(sc, "shutdown");
783 1.2 ragge }
784