if_qe.c revision 1.37
1 /* $NetBSD: if_qe.c,v 1.37 1999/06/20 00:04:47 ragge Exp $ */ 2 /* 3 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for DEQNA/DELQA ethernet cards. 34 * Things that is still to do: 35 * Have a timeout check for hang transmit logic. 36 * Handle ubaresets. Does not work at all right now. 37 * Fix ALLMULTI reception. But someone must tell me how... 38 * Collect statistics. 39 */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 44 #include <sys/param.h> 45 #include <sys/mbuf.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/systm.h> 49 #include <sys/sockio.h> 50 51 #include <net/if.h> 52 #include <net/if_ether.h> 53 #include <net/if_dl.h> 54 55 #include <netinet/in.h> 56 #include <netinet/if_inarp.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #include <net/bpfdesc.h> 61 #endif 62 63 #include <machine/bus.h> 64 65 #include <dev/qbus/ubavar.h> 66 #include <dev/qbus/if_qereg.h> 67 68 #include "ioconf.h" 69 70 #define RXDESCS 30 /* # of receive descriptors */ 71 #define TXDESCS 60 /* # transmit descs */ 72 73 /* 74 * Structure containing the elements that must be in DMA-safe memory. 75 */ 76 struct qe_cdata { 77 struct qe_ring qc_recv[RXDESCS+1]; /* Receive descriptors */ 78 struct qe_ring qc_xmit[TXDESCS+1]; /* Transmit descriptors */ 79 u_int8_t qc_setup[128]; /* Setup packet layout */ 80 }; 81 82 struct qe_softc { 83 struct device sc_dev; /* Configuration common part */ 84 struct ethercom sc_ec; /* Ethernet common part */ 85 #define sc_if sc_ec.ec_if /* network-visible interface */ 86 bus_space_tag_t sc_iot; 87 bus_addr_t sc_ioh; 88 bus_dma_tag_t sc_dmat; 89 struct qe_cdata *sc_qedata; /* Descriptor struct */ 90 struct qe_cdata *sc_pqedata; /* Unibus address of above */ 91 bus_dmamap_t sc_cmap; /* Map for control structures */ 92 struct mbuf* sc_txmbuf[TXDESCS]; 93 struct mbuf* sc_rxmbuf[RXDESCS]; 94 bus_dmamap_t sc_xmtmap[TXDESCS]; 95 bus_dmamap_t sc_rcvmap[RXDESCS]; 96 int sc_intvec; /* Interrupt vector */ 97 int sc_nexttx; 98 int sc_inq; 99 int sc_lastack; 100 int sc_nextrx; 101 int sc_setup; /* Setup packet in queue */ 102 }; 103 104 static int qematch __P((struct device *, struct cfdata *, void *)); 105 static void qeattach __P((struct device *, struct device *, void *)); 106 static void qeinit __P((struct qe_softc *)); 107 static void qestart __P((struct ifnet *)); 108 static void qeintr __P((int)); 109 static int qeioctl __P((struct ifnet *, u_long, caddr_t)); 110 static int qe_add_rxbuf __P((struct qe_softc *, int)); 111 static void qe_setup __P((struct qe_softc *)); 112 113 struct cfattach qe_ca = { 114 sizeof(struct qe_softc), qematch, qeattach 115 }; 116 117 #define QE_WCSR(csr, val) \ 118 bus_space_write_2(sc->sc_iot, sc->sc_ioh, csr, val) 119 #define QE_RCSR(csr) \ 120 bus_space_read_2(sc->sc_iot, sc->sc_ioh, csr) 121 122 #define LOWORD(x) ((int)(x) & 0xffff) 123 #define HIWORD(x) (((int)(x) >> 16) & 0x3f) 124 125 /* 126 * Check for present DEQNA. Done by sending a fake setup packet 127 * and wait for interrupt. 128 */ 129 int 130 qematch(parent, cf, aux) 131 struct device *parent; 132 struct cfdata *cf; 133 void *aux; 134 { 135 bus_dmamap_t cmap; 136 struct qe_softc ssc; 137 struct qe_softc *sc = &ssc; 138 struct uba_attach_args *ua = aux; 139 struct uba_softc *ubasc = (struct uba_softc *)parent; 140 141 #define PROBESIZE (sizeof(struct qe_ring) * 4 + 128) 142 struct qe_ring ring[15]; /* For diag purposes only */ 143 struct qe_ring *rp; 144 int error; 145 146 bzero(sc, sizeof(struct qe_softc)); 147 bzero(ring, PROBESIZE); 148 sc->sc_iot = ua->ua_iot; 149 sc->sc_ioh = ua->ua_ioh; 150 sc->sc_dmat = ua->ua_dmat; 151 152 ubasc->uh_lastiv -= 4; 153 QE_WCSR(QE_CSR_CSR, QE_RESET); 154 QE_WCSR(QE_CSR_VECTOR, ubasc->uh_lastiv); 155 156 /* 157 * Map the ring area. Actually this is done only to be able to 158 * send and receive a internal packet; some junk is loopbacked 159 * so that the DEQNA has a reason to interrupt. 160 */ 161 if ((error = bus_dmamap_create(sc->sc_dmat, PROBESIZE, 1, PROBESIZE, 0, 162 BUS_DMA_NOWAIT, &cmap))) { 163 printf("qematch: bus_dmamap_create failed = %d\n", error); 164 return 0; 165 } 166 if ((error = bus_dmamap_load(sc->sc_dmat, cmap, ring, PROBESIZE, 0, 167 BUS_DMA_NOWAIT))) { 168 printf("qematch: bus_dmamap_load failed = %d\n", error); 169 bus_dmamap_destroy(sc->sc_dmat, cmap); 170 return 0; 171 } 172 173 /* 174 * Init a simple "fake" receive and transmit descriptor that 175 * points to some unused area. Send a fake setup packet. 176 */ 177 rp = (void *)cmap->dm_segs[0].ds_addr; 178 ring[0].qe_flag = ring[0].qe_status1 = QE_NOTYET; 179 ring[0].qe_addr_lo = LOWORD(&rp[4]); 180 ring[0].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID | QE_EOMSG | QE_SETUP; 181 ring[0].qe_buf_len = 128; 182 183 ring[2].qe_flag = ring[2].qe_status1 = QE_NOTYET; 184 ring[2].qe_addr_lo = LOWORD(&rp[4]); 185 ring[2].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID; 186 ring[2].qe_buf_len = 128; 187 188 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 189 DELAY(1000); 190 191 /* 192 * Start the interface and wait for the packet. 193 */ 194 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 195 QE_WCSR(QE_CSR_RCLL, LOWORD(&rp[2])); 196 QE_WCSR(QE_CSR_RCLH, HIWORD(&rp[2])); 197 QE_WCSR(QE_CSR_XMTL, LOWORD(rp)); 198 QE_WCSR(QE_CSR_XMTH, HIWORD(rp)); 199 DELAY(10000); 200 201 /* 202 * All done with the bus resources. 203 */ 204 bus_dmamap_unload(sc->sc_dmat, cmap); 205 bus_dmamap_destroy(sc->sc_dmat, cmap); 206 ua->ua_ivec = qeintr; 207 return 1; 208 } 209 210 /* 211 * Interface exists: make available by filling in network interface 212 * record. System will initialize the interface when it is ready 213 * to accept packets. 214 */ 215 void 216 qeattach(parent, self, aux) 217 struct device *parent, *self; 218 void *aux; 219 { 220 struct uba_attach_args *ua = aux; 221 struct uba_softc *ubasc = (struct uba_softc *)parent; 222 struct qe_softc *sc = (struct qe_softc *)self; 223 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 224 struct qe_ring *rp; 225 u_int8_t enaddr[ETHER_ADDR_LEN]; 226 bus_dma_segment_t seg; 227 int i, rseg, error; 228 229 sc->sc_iot = ua->ua_iot; 230 sc->sc_ioh = ua->ua_ioh; 231 sc->sc_dmat = ua->ua_dmat; 232 233 /* 234 * Allocate DMA safe memory for descriptors and setup memory. 235 */ 236 if ((error = bus_dmamem_alloc(sc->sc_dmat, 237 sizeof(struct qe_cdata), NBPG, 0, &seg, 1, &rseg, 238 BUS_DMA_NOWAIT)) != 0) { 239 printf(": unable to allocate control data, error = %d\n", 240 error); 241 goto fail_0; 242 } 243 244 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 245 sizeof(struct qe_cdata), (caddr_t *)&sc->sc_qedata, 246 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 247 printf(": unable to map control data, error = %d\n", error); 248 goto fail_1; 249 } 250 251 if ((error = bus_dmamap_create(sc->sc_dmat, 252 sizeof(struct qe_cdata), 1, 253 sizeof(struct qe_cdata), 0, BUS_DMA_NOWAIT, 254 &sc->sc_cmap)) != 0) { 255 printf(": unable to create control data DMA map, error = %d\n", 256 error); 257 goto fail_2; 258 } 259 260 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap, 261 sc->sc_qedata, sizeof(struct qe_cdata), NULL, 262 BUS_DMA_NOWAIT)) != 0) { 263 printf(": unable to load control data DMA map, error = %d\n", 264 error); 265 goto fail_3; 266 } 267 268 /* 269 * Zero the newly allocated memory. 270 */ 271 bzero(sc->sc_qedata, sizeof(struct qe_cdata)); 272 /* 273 * Create the transmit descriptor DMA maps. We take advantage 274 * of the fact that the Qbus address space is big, and therefore 275 * allocate map registers for all transmit descriptors also, 276 * so that we can avoid this each time we send a packet. 277 */ 278 for (i = 0; i < TXDESCS; i++) { 279 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 280 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 281 &sc->sc_xmtmap[i]))) { 282 printf(": unable to create tx DMA map %d, error = %d\n", 283 i, error); 284 goto fail_4; 285 } 286 } 287 288 /* 289 * Create receive buffer DMA maps. 290 */ 291 for (i = 0; i < RXDESCS; i++) { 292 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 293 MCLBYTES, 0, BUS_DMA_NOWAIT, 294 &sc->sc_rcvmap[i]))) { 295 printf(": unable to create rx DMA map %d, error = %d\n", 296 i, error); 297 goto fail_5; 298 } 299 } 300 /* 301 * Pre-allocate the receive buffers. 302 */ 303 for (i = 0; i < RXDESCS; i++) { 304 if ((error = qe_add_rxbuf(sc, i)) != 0) { 305 printf(": unable to allocate or map rx buffer %d\n," 306 " error = %d\n", i, error); 307 goto fail_6; 308 } 309 } 310 311 /* 312 * Create ring loops of the buffer chains. 313 * This is only done once. 314 */ 315 sc->sc_pqedata = (struct qe_cdata *)sc->sc_cmap->dm_segs[0].ds_addr; 316 317 rp = sc->sc_qedata->qc_recv; 318 rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]); 319 rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) | 320 QE_VALID | QE_CHAIN; 321 rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET; 322 323 rp = sc->sc_qedata->qc_xmit; 324 rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]); 325 rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) | 326 QE_VALID | QE_CHAIN; 327 rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET; 328 329 /* 330 * Get the vector that were set at match time, and remember it. 331 */ 332 sc->sc_intvec = ubasc->uh_lastiv; 333 QE_WCSR(QE_CSR_CSR, QE_RESET); 334 DELAY(1000); 335 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 336 337 /* 338 * Read out ethernet address and tell which type this card is. 339 */ 340 for (i = 0; i < 6; i++) 341 enaddr[i] = QE_RCSR(i * 2) & 0xff; 342 343 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1); 344 printf("\n%s: %s, hardware address %s\n", sc->sc_dev.dv_xname, 345 QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna", 346 ether_sprintf(enaddr)); 347 348 QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */ 349 350 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 351 ifp->if_softc = sc; 352 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 353 ifp->if_start = qestart; 354 ifp->if_ioctl = qeioctl; 355 356 /* 357 * Attach the interface. 358 */ 359 if_attach(ifp); 360 ether_ifattach(ifp, enaddr); 361 362 #if NBPFILTER > 0 363 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 364 #endif 365 return; 366 367 /* 368 * Free any resources we've allocated during the failed attach 369 * attempt. Do this in reverse order and fall through. 370 */ 371 fail_6: 372 for (i = 0; i < RXDESCS; i++) { 373 if (sc->sc_rxmbuf[i] != NULL) { 374 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 375 m_freem(sc->sc_rxmbuf[i]); 376 } 377 } 378 fail_5: 379 for (i = 0; i < RXDESCS; i++) { 380 if (sc->sc_xmtmap[i] != NULL) 381 bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]); 382 } 383 fail_4: 384 for (i = 0; i < TXDESCS; i++) { 385 if (sc->sc_rcvmap[i] != NULL) 386 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]); 387 } 388 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmap); 389 fail_3: 390 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap); 391 fail_2: 392 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_qedata, 393 sizeof(struct qe_cdata)); 394 fail_1: 395 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 396 fail_0: 397 return; 398 } 399 400 /* 401 * Initialization of interface. 402 */ 403 void 404 qeinit(sc) 405 struct qe_softc *sc; 406 { 407 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 408 struct qe_cdata *qc = sc->sc_qedata; 409 int i; 410 411 412 /* 413 * Reset the interface. 414 */ 415 QE_WCSR(QE_CSR_CSR, QE_RESET); 416 DELAY(1000); 417 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 418 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec); 419 420 sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0; 421 /* 422 * Release and init transmit descriptors. 423 */ 424 for (i = 0; i < TXDESCS; i++) { 425 if (sc->sc_txmbuf[i]) { 426 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 427 m_freem(sc->sc_txmbuf[i]); 428 sc->sc_txmbuf[i] = 0; 429 } 430 qc->qc_xmit[i].qe_addr_hi = 0; /* Clear valid bit */ 431 qc->qc_xmit[i].qe_status1 = qc->qc_xmit[i].qe_flag = QE_NOTYET; 432 } 433 434 435 /* 436 * Init receive descriptors. 437 */ 438 for (i = 0; i < RXDESCS; i++) 439 qc->qc_recv[i].qe_status1 = qc->qc_recv[i].qe_flag = QE_NOTYET; 440 sc->sc_nextrx = 0; 441 442 /* 443 * Write the descriptor addresses to the device. 444 * Receiving packets will be enabled in the interrupt routine. 445 */ 446 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 447 QE_WCSR(QE_CSR_RCLL, LOWORD(sc->sc_pqedata->qc_recv)); 448 QE_WCSR(QE_CSR_RCLH, HIWORD(sc->sc_pqedata->qc_recv)); 449 450 ifp->if_flags |= IFF_RUNNING; 451 ifp->if_flags &= ~IFF_OACTIVE; 452 453 /* 454 * Send a setup frame. 455 * This will start the transmit machinery as well. 456 */ 457 qe_setup(sc); 458 459 } 460 461 /* 462 * Start output on interface. 463 */ 464 void 465 qestart(ifp) 466 struct ifnet *ifp; 467 { 468 struct qe_softc *sc = ifp->if_softc; 469 struct qe_cdata *qc = sc->sc_qedata; 470 paddr_t buffer; 471 struct mbuf *m, *m0; 472 int idx, len, s, i, oldidx = 0; 473 short orword; 474 475 if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_ENABLE) == 0) 476 return; 477 478 s = splimp(); 479 while (sc->sc_inq < (TXDESCS - 1)) { 480 481 if (sc->sc_setup) { 482 qe_setup(sc); 483 continue; 484 } 485 idx = sc->sc_nexttx; 486 IF_DEQUEUE(&sc->sc_if.if_snd, m); 487 if (m == 0) 488 goto out; 489 /* 490 * Count number of mbufs in chain. 491 * Always do DMA directly from mbufs, therefore the transmit 492 * ring is really big. 493 */ 494 for (m0 = m, i = 0; m0; m0 = m0->m_next) 495 i++; 496 if (i >= TXDESCS) 497 panic("qestart"); 498 499 if ((i + sc->sc_inq) >= (TXDESCS - 1)) { 500 IF_PREPEND(&sc->sc_if.if_snd, m); 501 goto out; 502 } 503 504 #if NBPFILTER > 0 505 if (ifp->if_bpf) 506 bpf_mtap(ifp->if_bpf, m); 507 #endif 508 /* 509 * m now points to a mbuf chain that can be loaded. 510 * Loop around and set it. 511 */ 512 for (m0 = m; m0; m0 = m0->m_next) { 513 bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx], 514 mtod(m0, void *), m0->m_len, 0, 0); 515 buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr; 516 len = m0->m_len; 517 518 /* Word alignment calc */ 519 orword = 0; 520 if (!m0->m_next) { 521 if (m->m_pkthdr.len < ETHER_MIN_LEN) 522 len += (ETHER_MIN_LEN - 523 m->m_pkthdr.len); 524 orword |= QE_EOMSG; 525 } 526 if ((buffer & 1) || (len & 1)) 527 len += 2; 528 if (buffer & 1) 529 orword |= QE_ODDBEGIN; 530 if ((buffer + len) & 1) 531 orword |= QE_ODDEND; 532 qc->qc_xmit[idx].qe_buf_len = -(len/2); 533 qc->qc_xmit[idx].qe_addr_lo = LOWORD(buffer); 534 qc->qc_xmit[idx].qe_addr_hi = HIWORD(buffer); 535 qc->qc_xmit[idx].qe_flag = 536 qc->qc_xmit[idx].qe_status1 = QE_NOTYET; 537 qc->qc_xmit[idx].qe_addr_hi |= (QE_VALID | orword); 538 oldidx = idx; 539 if (++idx == TXDESCS) 540 idx = 0; 541 sc->sc_inq++; 542 } 543 sc->sc_txmbuf[oldidx] = m; 544 545 /* 546 * Kick off the transmit logic, if it is stopped. 547 */ 548 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 549 QE_WCSR(QE_CSR_XMTL, 550 LOWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 551 QE_WCSR(QE_CSR_XMTH, 552 HIWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 553 } 554 sc->sc_nexttx = idx; 555 } 556 if (sc->sc_inq == (TXDESCS - 1)) 557 ifp->if_flags |= IFF_OACTIVE; 558 out: splx(s); 559 } 560 561 void 562 qeintr(unit) 563 int unit; 564 { 565 struct qe_softc *sc = qe_cd.cd_devs[unit]; 566 struct qe_cdata *qc = sc->sc_qedata; 567 struct ifnet *ifp = &sc->sc_if; 568 struct ether_header *eh; 569 struct mbuf *m; 570 int csr, status1, status2, len; 571 572 csr = QE_RCSR(QE_CSR_CSR); 573 574 QE_WCSR(QE_CSR_CSR, QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 575 QE_RCV_INT | QE_ILOOP); 576 577 if (csr & QE_RCV_INT) 578 while (qc->qc_recv[sc->sc_nextrx].qe_status1 != QE_NOTYET) { 579 status1 = qc->qc_recv[sc->sc_nextrx].qe_status1; 580 status2 = qc->qc_recv[sc->sc_nextrx].qe_status2; 581 m = sc->sc_rxmbuf[sc->sc_nextrx]; 582 len = ((status1 & QE_RBL_HI) | 583 (status2 & QE_RBL_LO)) + 60; 584 qe_add_rxbuf(sc, sc->sc_nextrx); 585 m->m_pkthdr.rcvif = ifp; 586 m->m_pkthdr.len = m->m_len = len; 587 if (++sc->sc_nextrx == RXDESCS) 588 sc->sc_nextrx = 0; 589 eh = mtod(m, struct ether_header *); 590 #if NBPFILTER > 0 591 if (ifp->if_bpf) { 592 bpf_mtap(ifp->if_bpf, m); 593 if ((ifp->if_flags & IFF_PROMISC) != 0 && 594 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 595 ETHER_ADDR_LEN) != 0 && 596 ((eh->ether_dhost[0] & 1) == 0)) { 597 m_freem(m); 598 continue; 599 } 600 } 601 #endif 602 /* 603 * ALLMULTI means PROMISC in this driver. 604 */ 605 if ((ifp->if_flags & IFF_ALLMULTI) && 606 ((eh->ether_dhost[0] & 1) == 0) && 607 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 608 ETHER_ADDR_LEN)) { 609 m_freem(m); 610 continue; 611 } 612 613 (*ifp->if_input)(ifp, m); 614 } 615 616 if (csr & QE_XMIT_INT) { 617 while (qc->qc_xmit[sc->sc_lastack].qe_status1 != QE_NOTYET) { 618 int idx = sc->sc_lastack; 619 620 sc->sc_inq--; 621 if (++sc->sc_lastack == TXDESCS) 622 sc->sc_lastack = 0; 623 624 /* XXX collect statistics */ 625 qc->qc_xmit[idx].qe_addr_hi &= ~QE_VALID; 626 qc->qc_xmit[idx].qe_status1 = 627 qc->qc_xmit[idx].qe_flag = QE_NOTYET; 628 629 if (qc->qc_xmit[idx].qe_addr_hi & QE_SETUP) 630 continue; 631 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]); 632 if (sc->sc_txmbuf[idx]) { 633 m_freem(sc->sc_txmbuf[idx]); 634 sc->sc_txmbuf[idx] = 0; 635 } 636 } 637 ifp->if_flags &= ~IFF_OACTIVE; 638 qestart(ifp); /* Put in more in queue */ 639 } 640 /* 641 * How can the receive list get invalid??? 642 * Verified that it happens anyway. 643 */ 644 if ((qc->qc_recv[sc->sc_nextrx].qe_status1 == QE_NOTYET) && 645 (QE_RCSR(QE_CSR_CSR) & QE_RL_INVALID)) { 646 QE_WCSR(QE_CSR_RCLL, 647 LOWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 648 QE_WCSR(QE_CSR_RCLH, 649 HIWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 650 } 651 } 652 653 /* 654 * Process an ioctl request. 655 */ 656 int 657 qeioctl(ifp, cmd, data) 658 register struct ifnet *ifp; 659 u_long cmd; 660 caddr_t data; 661 { 662 struct qe_softc *sc = ifp->if_softc; 663 struct ifreq *ifr = (struct ifreq *)data; 664 struct ifaddr *ifa = (struct ifaddr *)data; 665 int s = splnet(), error = 0; 666 667 switch (cmd) { 668 669 case SIOCSIFADDR: 670 ifp->if_flags |= IFF_UP; 671 switch(ifa->ifa_addr->sa_family) { 672 #ifdef INET 673 case AF_INET: 674 qeinit(sc); 675 arp_ifinit(ifp, ifa); 676 break; 677 #endif 678 } 679 break; 680 681 case SIOCSIFFLAGS: 682 if ((ifp->if_flags & IFF_UP) == 0 && 683 (ifp->if_flags & IFF_RUNNING) != 0) { 684 /* 685 * If interface is marked down and it is running, 686 * stop it. (by disabling receive mechanism). 687 */ 688 QE_WCSR(QE_CSR_CSR, 689 QE_RCSR(QE_CSR_CSR) & ~QE_RCV_ENABLE); 690 ifp->if_flags &= ~IFF_RUNNING; 691 } else if ((ifp->if_flags & IFF_UP) != 0 && 692 (ifp->if_flags & IFF_RUNNING) == 0) { 693 /* 694 * If interface it marked up and it is stopped, then 695 * start it. 696 */ 697 qeinit(sc); 698 } else if ((ifp->if_flags & IFF_UP) != 0) { 699 /* 700 * Send a new setup packet to match any new changes. 701 * (Like IFF_PROMISC etc) 702 */ 703 qe_setup(sc); 704 } 705 break; 706 707 case SIOCADDMULTI: 708 case SIOCDELMULTI: 709 /* 710 * Update our multicast list. 711 */ 712 error = (cmd == SIOCADDMULTI) ? 713 ether_addmulti(ifr, &sc->sc_ec): 714 ether_delmulti(ifr, &sc->sc_ec); 715 716 if (error == ENETRESET) { 717 /* 718 * Multicast list has changed; set the hardware filter 719 * accordingly. 720 */ 721 qe_setup(sc); 722 error = 0; 723 } 724 break; 725 726 default: 727 error = EINVAL; 728 729 } 730 splx(s); 731 return (error); 732 } 733 734 /* 735 * Add a receive buffer to the indicated descriptor. 736 */ 737 int 738 qe_add_rxbuf(sc, i) 739 struct qe_softc *sc; 740 int i; 741 { 742 struct mbuf *m; 743 struct qe_ring *rp; 744 vaddr_t addr; 745 int error; 746 747 MGETHDR(m, M_DONTWAIT, MT_DATA); 748 if (m == NULL) 749 return (ENOBUFS); 750 751 MCLGET(m, M_DONTWAIT); 752 if ((m->m_flags & M_EXT) == 0) { 753 m_freem(m); 754 return (ENOBUFS); 755 } 756 757 if (sc->sc_rxmbuf[i] != NULL) 758 bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]); 759 760 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i], 761 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 762 if (error) 763 panic("%s: can't load rx DMA map %d, error = %d\n", 764 sc->sc_dev.dv_xname, i, error); 765 sc->sc_rxmbuf[i] = m; 766 767 bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0, 768 sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 769 770 /* 771 * We know that the mbuf cluster is page aligned. Also, be sure 772 * that the IP header will be longword aligned. 773 */ 774 m->m_data += 2; 775 addr = sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2; 776 rp = &sc->sc_qedata->qc_recv[i]; 777 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 778 rp->qe_addr_lo = LOWORD(addr); 779 rp->qe_addr_hi = HIWORD(addr) | QE_VALID; 780 rp->qe_buf_len = -(m->m_ext.ext_size - 2)/2; 781 782 return (0); 783 } 784 785 /* 786 * Create a setup packet and put in queue for sending. 787 */ 788 void 789 qe_setup(sc) 790 struct qe_softc *sc; 791 { 792 struct ether_multi *enm; 793 struct ether_multistep step; 794 struct qe_cdata *qc = sc->sc_qedata; 795 struct ifnet *ifp = &sc->sc_if; 796 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 797 int i, j, k, idx, s; 798 799 s = splimp(); 800 if (sc->sc_inq == (TXDESCS - 1)) { 801 sc->sc_setup = 1; 802 splx(s); 803 return; 804 } 805 sc->sc_setup = 0; 806 /* 807 * Init the setup packet with valid info. 808 */ 809 memset(qc->qc_setup, 0xff, sizeof(qc->qc_setup)); /* Broadcast */ 810 for (i = 0; i < ETHER_ADDR_LEN; i++) 811 qc->qc_setup[i * 8 + 1] = enaddr[i]; /* Own address */ 812 813 /* 814 * Multicast handling. The DEQNA can handle up to 12 direct 815 * ethernet addresses. 816 */ 817 j = 3; k = 0; 818 ifp->if_flags &= ~IFF_ALLMULTI; 819 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 820 while (enm != NULL) { 821 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 822 ifp->if_flags |= IFF_ALLMULTI; 823 break; 824 } 825 for (i = 0; i < ETHER_ADDR_LEN; i++) 826 qc->qc_setup[i * 8 + j + k] = enm->enm_addrlo[i]; 827 j++; 828 if (j == 8) { 829 j = 1; k += 64; 830 } 831 if (k > 64) { 832 ifp->if_flags |= IFF_ALLMULTI; 833 break; 834 } 835 ETHER_NEXT_MULTI(step, enm); 836 } 837 idx = sc->sc_nexttx; 838 qc->qc_xmit[idx].qe_buf_len = -64; 839 840 /* 841 * How is the DEQNA turned in ALLMULTI mode??? 842 * Until someone tells me, fall back to PROMISC when more than 843 * 12 ethernet addresses. 844 */ 845 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 846 qc->qc_xmit[idx].qe_buf_len = -65; 847 848 qc->qc_xmit[idx].qe_addr_lo = LOWORD(sc->sc_pqedata->qc_setup); 849 qc->qc_xmit[idx].qe_addr_hi = 850 HIWORD(sc->sc_pqedata->qc_setup) | QE_SETUP | QE_EOMSG; 851 qc->qc_xmit[idx].qe_status1 = qc->qc_xmit[idx].qe_flag = QE_NOTYET; 852 qc->qc_xmit[idx].qe_addr_hi |= QE_VALID; 853 854 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 855 QE_WCSR(QE_CSR_XMTL, 856 LOWORD(&sc->sc_pqedata->qc_xmit[idx])); 857 QE_WCSR(QE_CSR_XMTH, 858 HIWORD(&sc->sc_pqedata->qc_xmit[idx])); 859 } 860 861 sc->sc_inq++; 862 if (++sc->sc_nexttx == TXDESCS) 863 sc->sc_nexttx = 0; 864 splx(s); 865 } 866
Indexes created Tue Sep 30 20:09:53 GMT 2025