if_qe.c revision 1.38
1 /* $NetBSD: if_qe.c,v 1.38 1999/08/01 15:25:41 ragge Exp $ */ 2 /* 3 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for DEQNA/DELQA ethernet cards. 34 * Things that is still to do: 35 * Have a timeout check for hang transmit logic. 36 * Handle ubaresets. Does not work at all right now. 37 * Fix ALLMULTI reception. But someone must tell me how... 38 * Collect statistics. 39 */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 44 #include <sys/param.h> 45 #include <sys/mbuf.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/systm.h> 49 #include <sys/sockio.h> 50 51 #include <net/if.h> 52 #include <net/if_ether.h> 53 #include <net/if_dl.h> 54 55 #include <netinet/in.h> 56 #include <netinet/if_inarp.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #include <net/bpfdesc.h> 61 #endif 62 63 #include <machine/bus.h> 64 65 #include <dev/qbus/ubavar.h> 66 #include <dev/qbus/if_qereg.h> 67 68 #include "ioconf.h" 69 70 #define RXDESCS 30 /* # of receive descriptors */ 71 #define TXDESCS 60 /* # transmit descs */ 72 73 /* 74 * Structure containing the elements that must be in DMA-safe memory. 75 */ 76 struct qe_cdata { 77 struct qe_ring qc_recv[RXDESCS+1]; /* Receive descriptors */ 78 struct qe_ring qc_xmit[TXDESCS+1]; /* Transmit descriptors */ 79 u_int8_t qc_setup[128]; /* Setup packet layout */ 80 }; 81 82 struct qe_softc { 83 struct device sc_dev; /* Configuration common part */ 84 struct ethercom sc_ec; /* Ethernet common part */ 85 #define sc_if sc_ec.ec_if /* network-visible interface */ 86 bus_space_tag_t sc_iot; 87 bus_addr_t sc_ioh; 88 bus_dma_tag_t sc_dmat; 89 struct qe_cdata *sc_qedata; /* Descriptor struct */ 90 struct qe_cdata *sc_pqedata; /* Unibus address of above */ 91 bus_dmamap_t sc_cmap; /* Map for control structures */ 92 struct mbuf* sc_txmbuf[TXDESCS]; 93 struct mbuf* sc_rxmbuf[RXDESCS]; 94 bus_dmamap_t sc_xmtmap[TXDESCS]; 95 bus_dmamap_t sc_rcvmap[RXDESCS]; 96 int sc_intvec; /* Interrupt vector */ 97 int sc_nexttx; 98 int sc_inq; 99 int sc_lastack; 100 int sc_nextrx; 101 int sc_setup; /* Setup packet in queue */ 102 }; 103 104 static int qematch __P((struct device *, struct cfdata *, void *)); 105 static void qeattach __P((struct device *, struct device *, void *)); 106 static void qeinit __P((struct qe_softc *)); 107 static void qestart __P((struct ifnet *)); 108 static void qeintr __P((int)); 109 static int qeioctl __P((struct ifnet *, u_long, caddr_t)); 110 static int qe_add_rxbuf __P((struct qe_softc *, int)); 111 static void qe_setup __P((struct qe_softc *)); 112 static void qetimeout __P((struct ifnet *)); 113 114 struct cfattach qe_ca = { 115 sizeof(struct qe_softc), qematch, qeattach 116 }; 117 118 #define QE_WCSR(csr, val) \ 119 bus_space_write_2(sc->sc_iot, sc->sc_ioh, csr, val) 120 #define QE_RCSR(csr) \ 121 bus_space_read_2(sc->sc_iot, sc->sc_ioh, csr) 122 123 #define LOWORD(x) ((int)(x) & 0xffff) 124 #define HIWORD(x) (((int)(x) >> 16) & 0x3f) 125 126 /* 127 * Check for present DEQNA. Done by sending a fake setup packet 128 * and wait for interrupt. 129 */ 130 int 131 qematch(parent, cf, aux) 132 struct device *parent; 133 struct cfdata *cf; 134 void *aux; 135 { 136 bus_dmamap_t cmap; 137 struct qe_softc ssc; 138 struct qe_softc *sc = &ssc; 139 struct uba_attach_args *ua = aux; 140 struct uba_softc *ubasc = (struct uba_softc *)parent; 141 142 #define PROBESIZE (sizeof(struct qe_ring) * 4 + 128) 143 struct qe_ring ring[15]; /* For diag purposes only */ 144 struct qe_ring *rp; 145 int error; 146 147 bzero(sc, sizeof(struct qe_softc)); 148 bzero(ring, PROBESIZE); 149 sc->sc_iot = ua->ua_iot; 150 sc->sc_ioh = ua->ua_ioh; 151 sc->sc_dmat = ua->ua_dmat; 152 153 ubasc->uh_lastiv -= 4; 154 QE_WCSR(QE_CSR_CSR, QE_RESET); 155 QE_WCSR(QE_CSR_VECTOR, ubasc->uh_lastiv); 156 157 /* 158 * Map the ring area. Actually this is done only to be able to 159 * send and receive a internal packet; some junk is loopbacked 160 * so that the DEQNA has a reason to interrupt. 161 */ 162 if ((error = bus_dmamap_create(sc->sc_dmat, PROBESIZE, 1, PROBESIZE, 0, 163 BUS_DMA_NOWAIT, &cmap))) { 164 printf("qematch: bus_dmamap_create failed = %d\n", error); 165 return 0; 166 } 167 if ((error = bus_dmamap_load(sc->sc_dmat, cmap, ring, PROBESIZE, 0, 168 BUS_DMA_NOWAIT))) { 169 printf("qematch: bus_dmamap_load failed = %d\n", error); 170 bus_dmamap_destroy(sc->sc_dmat, cmap); 171 return 0; 172 } 173 174 /* 175 * Init a simple "fake" receive and transmit descriptor that 176 * points to some unused area. Send a fake setup packet. 177 */ 178 rp = (void *)cmap->dm_segs[0].ds_addr; 179 ring[0].qe_flag = ring[0].qe_status1 = QE_NOTYET; 180 ring[0].qe_addr_lo = LOWORD(&rp[4]); 181 ring[0].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID | QE_EOMSG | QE_SETUP; 182 ring[0].qe_buf_len = 128; 183 184 ring[2].qe_flag = ring[2].qe_status1 = QE_NOTYET; 185 ring[2].qe_addr_lo = LOWORD(&rp[4]); 186 ring[2].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID; 187 ring[2].qe_buf_len = 128; 188 189 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 190 DELAY(1000); 191 192 /* 193 * Start the interface and wait for the packet. 194 */ 195 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 196 QE_WCSR(QE_CSR_RCLL, LOWORD(&rp[2])); 197 QE_WCSR(QE_CSR_RCLH, HIWORD(&rp[2])); 198 QE_WCSR(QE_CSR_XMTL, LOWORD(rp)); 199 QE_WCSR(QE_CSR_XMTH, HIWORD(rp)); 200 DELAY(10000); 201 202 /* 203 * All done with the bus resources. 204 */ 205 bus_dmamap_unload(sc->sc_dmat, cmap); 206 bus_dmamap_destroy(sc->sc_dmat, cmap); 207 ua->ua_ivec = qeintr; 208 return 1; 209 } 210 211 /* 212 * Interface exists: make available by filling in network interface 213 * record. System will initialize the interface when it is ready 214 * to accept packets. 215 */ 216 void 217 qeattach(parent, self, aux) 218 struct device *parent, *self; 219 void *aux; 220 { 221 struct uba_attach_args *ua = aux; 222 struct uba_softc *ubasc = (struct uba_softc *)parent; 223 struct qe_softc *sc = (struct qe_softc *)self; 224 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 225 struct qe_ring *rp; 226 u_int8_t enaddr[ETHER_ADDR_LEN]; 227 bus_dma_segment_t seg; 228 int i, rseg, error; 229 230 sc->sc_iot = ua->ua_iot; 231 sc->sc_ioh = ua->ua_ioh; 232 sc->sc_dmat = ua->ua_dmat; 233 234 /* 235 * Allocate DMA safe memory for descriptors and setup memory. 236 */ 237 if ((error = bus_dmamem_alloc(sc->sc_dmat, 238 sizeof(struct qe_cdata), NBPG, 0, &seg, 1, &rseg, 239 BUS_DMA_NOWAIT)) != 0) { 240 printf(": unable to allocate control data, error = %d\n", 241 error); 242 goto fail_0; 243 } 244 245 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 246 sizeof(struct qe_cdata), (caddr_t *)&sc->sc_qedata, 247 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 248 printf(": unable to map control data, error = %d\n", error); 249 goto fail_1; 250 } 251 252 if ((error = bus_dmamap_create(sc->sc_dmat, 253 sizeof(struct qe_cdata), 1, 254 sizeof(struct qe_cdata), 0, BUS_DMA_NOWAIT, 255 &sc->sc_cmap)) != 0) { 256 printf(": unable to create control data DMA map, error = %d\n", 257 error); 258 goto fail_2; 259 } 260 261 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap, 262 sc->sc_qedata, sizeof(struct qe_cdata), NULL, 263 BUS_DMA_NOWAIT)) != 0) { 264 printf(": unable to load control data DMA map, error = %d\n", 265 error); 266 goto fail_3; 267 } 268 269 /* 270 * Zero the newly allocated memory. 271 */ 272 bzero(sc->sc_qedata, sizeof(struct qe_cdata)); 273 /* 274 * Create the transmit descriptor DMA maps. We take advantage 275 * of the fact that the Qbus address space is big, and therefore 276 * allocate map registers for all transmit descriptors also, 277 * so that we can avoid this each time we send a packet. 278 */ 279 for (i = 0; i < TXDESCS; i++) { 280 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 281 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 282 &sc->sc_xmtmap[i]))) { 283 printf(": unable to create tx DMA map %d, error = %d\n", 284 i, error); 285 goto fail_4; 286 } 287 } 288 289 /* 290 * Create receive buffer DMA maps. 291 */ 292 for (i = 0; i < RXDESCS; i++) { 293 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 294 MCLBYTES, 0, BUS_DMA_NOWAIT, 295 &sc->sc_rcvmap[i]))) { 296 printf(": unable to create rx DMA map %d, error = %d\n", 297 i, error); 298 goto fail_5; 299 } 300 } 301 /* 302 * Pre-allocate the receive buffers. 303 */ 304 for (i = 0; i < RXDESCS; i++) { 305 if ((error = qe_add_rxbuf(sc, i)) != 0) { 306 printf(": unable to allocate or map rx buffer %d\n," 307 " error = %d\n", i, error); 308 goto fail_6; 309 } 310 } 311 312 /* 313 * Create ring loops of the buffer chains. 314 * This is only done once. 315 */ 316 sc->sc_pqedata = (struct qe_cdata *)sc->sc_cmap->dm_segs[0].ds_addr; 317 318 rp = sc->sc_qedata->qc_recv; 319 rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]); 320 rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) | 321 QE_VALID | QE_CHAIN; 322 rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET; 323 324 rp = sc->sc_qedata->qc_xmit; 325 rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]); 326 rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) | 327 QE_VALID | QE_CHAIN; 328 rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET; 329 330 /* 331 * Get the vector that were set at match time, and remember it. 332 */ 333 sc->sc_intvec = ubasc->uh_lastiv; 334 QE_WCSR(QE_CSR_CSR, QE_RESET); 335 DELAY(1000); 336 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 337 338 /* 339 * Read out ethernet address and tell which type this card is. 340 */ 341 for (i = 0; i < 6; i++) 342 enaddr[i] = QE_RCSR(i * 2) & 0xff; 343 344 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1); 345 printf("\n%s: %s, hardware address %s\n", sc->sc_dev.dv_xname, 346 QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna", 347 ether_sprintf(enaddr)); 348 349 QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */ 350 351 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 352 ifp->if_softc = sc; 353 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 354 ifp->if_start = qestart; 355 ifp->if_ioctl = qeioctl; 356 ifp->if_watchdog = qetimeout; 357 358 /* 359 * Attach the interface. 360 */ 361 if_attach(ifp); 362 ether_ifattach(ifp, enaddr); 363 364 #if NBPFILTER > 0 365 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 366 #endif 367 return; 368 369 /* 370 * Free any resources we've allocated during the failed attach 371 * attempt. Do this in reverse order and fall through. 372 */ 373 fail_6: 374 for (i = 0; i < RXDESCS; i++) { 375 if (sc->sc_rxmbuf[i] != NULL) { 376 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 377 m_freem(sc->sc_rxmbuf[i]); 378 } 379 } 380 fail_5: 381 for (i = 0; i < RXDESCS; i++) { 382 if (sc->sc_xmtmap[i] != NULL) 383 bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]); 384 } 385 fail_4: 386 for (i = 0; i < TXDESCS; i++) { 387 if (sc->sc_rcvmap[i] != NULL) 388 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]); 389 } 390 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmap); 391 fail_3: 392 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap); 393 fail_2: 394 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_qedata, 395 sizeof(struct qe_cdata)); 396 fail_1: 397 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 398 fail_0: 399 return; 400 } 401 402 /* 403 * Initialization of interface. 404 */ 405 void 406 qeinit(sc) 407 struct qe_softc *sc; 408 { 409 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 410 struct qe_cdata *qc = sc->sc_qedata; 411 int i; 412 413 414 /* 415 * Reset the interface. 416 */ 417 QE_WCSR(QE_CSR_CSR, QE_RESET); 418 DELAY(1000); 419 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 420 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec); 421 422 sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0; 423 /* 424 * Release and init transmit descriptors. 425 */ 426 for (i = 0; i < TXDESCS; i++) { 427 if (sc->sc_txmbuf[i]) { 428 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 429 m_freem(sc->sc_txmbuf[i]); 430 sc->sc_txmbuf[i] = 0; 431 } 432 qc->qc_xmit[i].qe_addr_hi = 0; /* Clear valid bit */ 433 qc->qc_xmit[i].qe_status1 = qc->qc_xmit[i].qe_flag = QE_NOTYET; 434 } 435 436 437 /* 438 * Init receive descriptors. 439 */ 440 for (i = 0; i < RXDESCS; i++) 441 qc->qc_recv[i].qe_status1 = qc->qc_recv[i].qe_flag = QE_NOTYET; 442 sc->sc_nextrx = 0; 443 444 /* 445 * Write the descriptor addresses to the device. 446 * Receiving packets will be enabled in the interrupt routine. 447 */ 448 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 449 QE_WCSR(QE_CSR_RCLL, LOWORD(sc->sc_pqedata->qc_recv)); 450 QE_WCSR(QE_CSR_RCLH, HIWORD(sc->sc_pqedata->qc_recv)); 451 452 ifp->if_flags |= IFF_RUNNING; 453 ifp->if_flags &= ~IFF_OACTIVE; 454 455 /* 456 * Send a setup frame. 457 * This will start the transmit machinery as well. 458 */ 459 qe_setup(sc); 460 461 } 462 463 /* 464 * Start output on interface. 465 */ 466 void 467 qestart(ifp) 468 struct ifnet *ifp; 469 { 470 struct qe_softc *sc = ifp->if_softc; 471 struct qe_cdata *qc = sc->sc_qedata; 472 paddr_t buffer; 473 struct mbuf *m, *m0; 474 int idx, len, s, i, totlen, error; 475 short orword; 476 477 if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_ENABLE) == 0) 478 return; 479 480 s = splimp(); 481 while (sc->sc_inq < (TXDESCS - 1)) { 482 483 if (sc->sc_setup) { 484 qe_setup(sc); 485 continue; 486 } 487 idx = sc->sc_nexttx; 488 IF_DEQUEUE(&sc->sc_if.if_snd, m); 489 if (m == 0) 490 goto out; 491 /* 492 * Count number of mbufs in chain. 493 * Always do DMA directly from mbufs, therefore the transmit 494 * ring is really big. 495 */ 496 for (m0 = m, i = 0; m0; m0 = m0->m_next) 497 if (m0->m_len) 498 i++; 499 if (i >= TXDESCS) 500 panic("qestart"); 501 502 if ((i + sc->sc_inq) >= (TXDESCS - 1)) { 503 IF_PREPEND(&sc->sc_if.if_snd, m); 504 ifp->if_flags |= IFF_OACTIVE; 505 goto out; 506 } 507 508 #if NBPFILTER > 0 509 if (ifp->if_bpf) 510 bpf_mtap(ifp->if_bpf, m); 511 #endif 512 /* 513 * m now points to a mbuf chain that can be loaded. 514 * Loop around and set it. 515 */ 516 totlen = 0; 517 for (m0 = m; m0; m0 = m0->m_next) { 518 error = bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx], 519 mtod(m0, void *), m0->m_len, 0, 0); 520 buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr; 521 len = m0->m_len; 522 if (len == 0) 523 continue; 524 525 totlen += len; 526 /* Word alignment calc */ 527 orword = 0; 528 if (totlen == m->m_pkthdr.len) { 529 if (totlen < ETHER_MIN_LEN) 530 len += (ETHER_MIN_LEN - totlen); 531 orword |= QE_EOMSG; 532 sc->sc_txmbuf[idx] = m; 533 } 534 if ((buffer & 1) || (len & 1)) 535 len += 2; 536 if (buffer & 1) 537 orword |= QE_ODDBEGIN; 538 if ((buffer + len) & 1) 539 orword |= QE_ODDEND; 540 qc->qc_xmit[idx].qe_buf_len = -(len/2); 541 qc->qc_xmit[idx].qe_addr_lo = LOWORD(buffer); 542 qc->qc_xmit[idx].qe_addr_hi = HIWORD(buffer); 543 qc->qc_xmit[idx].qe_flag = 544 qc->qc_xmit[idx].qe_status1 = QE_NOTYET; 545 qc->qc_xmit[idx].qe_addr_hi |= (QE_VALID | orword); 546 if (++idx == TXDESCS) 547 idx = 0; 548 sc->sc_inq++; 549 } 550 #ifdef DIAGNOSTIC 551 if (totlen != m->m_pkthdr.len) 552 panic("qestart: len fault"); 553 #endif 554 555 /* 556 * Kick off the transmit logic, if it is stopped. 557 */ 558 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 559 QE_WCSR(QE_CSR_XMTL, 560 LOWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 561 QE_WCSR(QE_CSR_XMTH, 562 HIWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 563 } 564 sc->sc_nexttx = idx; 565 } 566 if (sc->sc_inq == (TXDESCS - 1)) 567 ifp->if_flags |= IFF_OACTIVE; 568 569 out: if (sc->sc_inq) 570 ifp->if_timer = 5; /* If transmit logic dies */ 571 splx(s); 572 } 573 574 void 575 qeintr(unit) 576 int unit; 577 { 578 struct qe_softc *sc = qe_cd.cd_devs[unit]; 579 struct qe_cdata *qc = sc->sc_qedata; 580 struct ifnet *ifp = &sc->sc_if; 581 struct ether_header *eh; 582 struct mbuf *m; 583 int csr, status1, status2, len; 584 585 csr = QE_RCSR(QE_CSR_CSR); 586 587 QE_WCSR(QE_CSR_CSR, QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 588 QE_RCV_INT | QE_ILOOP); 589 590 if (csr & QE_RCV_INT) 591 while (qc->qc_recv[sc->sc_nextrx].qe_status1 != QE_NOTYET) { 592 status1 = qc->qc_recv[sc->sc_nextrx].qe_status1; 593 status2 = qc->qc_recv[sc->sc_nextrx].qe_status2; 594 m = sc->sc_rxmbuf[sc->sc_nextrx]; 595 len = ((status1 & QE_RBL_HI) | 596 (status2 & QE_RBL_LO)) + 60; 597 qe_add_rxbuf(sc, sc->sc_nextrx); 598 m->m_pkthdr.rcvif = ifp; 599 m->m_pkthdr.len = m->m_len = len; 600 if (++sc->sc_nextrx == RXDESCS) 601 sc->sc_nextrx = 0; 602 eh = mtod(m, struct ether_header *); 603 #if NBPFILTER > 0 604 if (ifp->if_bpf) { 605 bpf_mtap(ifp->if_bpf, m); 606 if ((ifp->if_flags & IFF_PROMISC) != 0 && 607 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 608 ETHER_ADDR_LEN) != 0 && 609 ((eh->ether_dhost[0] & 1) == 0)) { 610 m_freem(m); 611 continue; 612 } 613 } 614 #endif 615 /* 616 * ALLMULTI means PROMISC in this driver. 617 */ 618 if ((ifp->if_flags & IFF_ALLMULTI) && 619 ((eh->ether_dhost[0] & 1) == 0) && 620 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 621 ETHER_ADDR_LEN)) { 622 m_freem(m); 623 continue; 624 } 625 (*ifp->if_input)(ifp, m); 626 } 627 628 if (csr & QE_XMIT_INT) { 629 while (qc->qc_xmit[sc->sc_lastack].qe_status1 != QE_NOTYET) { 630 int idx = sc->sc_lastack; 631 632 sc->sc_inq--; 633 if (++sc->sc_lastack == TXDESCS) 634 sc->sc_lastack = 0; 635 636 /* XXX collect statistics */ 637 qc->qc_xmit[idx].qe_addr_hi &= ~QE_VALID; 638 qc->qc_xmit[idx].qe_status1 = 639 qc->qc_xmit[idx].qe_flag = QE_NOTYET; 640 641 if (qc->qc_xmit[idx].qe_addr_hi & QE_SETUP) 642 continue; 643 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]); 644 if (sc->sc_txmbuf[idx]) { 645 m_freem(sc->sc_txmbuf[idx]); 646 sc->sc_txmbuf[idx] = 0; 647 } 648 } 649 ifp->if_timer = 0; 650 ifp->if_flags &= ~IFF_OACTIVE; 651 qestart(ifp); /* Put in more in queue */ 652 } 653 /* 654 * How can the receive list get invalid??? 655 * Verified that it happens anyway. 656 */ 657 if ((qc->qc_recv[sc->sc_nextrx].qe_status1 == QE_NOTYET) && 658 (QE_RCSR(QE_CSR_CSR) & QE_RL_INVALID)) { 659 QE_WCSR(QE_CSR_RCLL, 660 LOWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 661 QE_WCSR(QE_CSR_RCLH, 662 HIWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 663 } 664 } 665 666 /* 667 * Process an ioctl request. 668 */ 669 int 670 qeioctl(ifp, cmd, data) 671 register struct ifnet *ifp; 672 u_long cmd; 673 caddr_t data; 674 { 675 struct qe_softc *sc = ifp->if_softc; 676 struct ifreq *ifr = (struct ifreq *)data; 677 struct ifaddr *ifa = (struct ifaddr *)data; 678 int s = splnet(), error = 0; 679 680 switch (cmd) { 681 682 case SIOCSIFADDR: 683 ifp->if_flags |= IFF_UP; 684 switch(ifa->ifa_addr->sa_family) { 685 #ifdef INET 686 case AF_INET: 687 qeinit(sc); 688 arp_ifinit(ifp, ifa); 689 break; 690 #endif 691 } 692 break; 693 694 case SIOCSIFFLAGS: 695 if ((ifp->if_flags & IFF_UP) == 0 && 696 (ifp->if_flags & IFF_RUNNING) != 0) { 697 /* 698 * If interface is marked down and it is running, 699 * stop it. (by disabling receive mechanism). 700 */ 701 QE_WCSR(QE_CSR_CSR, 702 QE_RCSR(QE_CSR_CSR) & ~QE_RCV_ENABLE); 703 ifp->if_flags &= ~IFF_RUNNING; 704 } else if ((ifp->if_flags & IFF_UP) != 0 && 705 (ifp->if_flags & IFF_RUNNING) == 0) { 706 /* 707 * If interface it marked up and it is stopped, then 708 * start it. 709 */ 710 qeinit(sc); 711 } else if ((ifp->if_flags & IFF_UP) != 0) { 712 /* 713 * Send a new setup packet to match any new changes. 714 * (Like IFF_PROMISC etc) 715 */ 716 qe_setup(sc); 717 } 718 break; 719 720 case SIOCADDMULTI: 721 case SIOCDELMULTI: 722 /* 723 * Update our multicast list. 724 */ 725 error = (cmd == SIOCADDMULTI) ? 726 ether_addmulti(ifr, &sc->sc_ec): 727 ether_delmulti(ifr, &sc->sc_ec); 728 729 if (error == ENETRESET) { 730 /* 731 * Multicast list has changed; set the hardware filter 732 * accordingly. 733 */ 734 qe_setup(sc); 735 error = 0; 736 } 737 break; 738 739 default: 740 error = EINVAL; 741 742 } 743 splx(s); 744 return (error); 745 } 746 747 /* 748 * Add a receive buffer to the indicated descriptor. 749 */ 750 int 751 qe_add_rxbuf(sc, i) 752 struct qe_softc *sc; 753 int i; 754 { 755 struct mbuf *m; 756 struct qe_ring *rp; 757 vaddr_t addr; 758 int error; 759 760 MGETHDR(m, M_DONTWAIT, MT_DATA); 761 if (m == NULL) 762 return (ENOBUFS); 763 764 MCLGET(m, M_DONTWAIT); 765 if ((m->m_flags & M_EXT) == 0) { 766 m_freem(m); 767 return (ENOBUFS); 768 } 769 770 if (sc->sc_rxmbuf[i] != NULL) 771 bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]); 772 773 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i], 774 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 775 if (error) 776 panic("%s: can't load rx DMA map %d, error = %d\n", 777 sc->sc_dev.dv_xname, i, error); 778 sc->sc_rxmbuf[i] = m; 779 780 bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0, 781 sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 782 783 /* 784 * We know that the mbuf cluster is page aligned. Also, be sure 785 * that the IP header will be longword aligned. 786 */ 787 m->m_data += 2; 788 addr = sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2; 789 rp = &sc->sc_qedata->qc_recv[i]; 790 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 791 rp->qe_addr_lo = LOWORD(addr); 792 rp->qe_addr_hi = HIWORD(addr) | QE_VALID; 793 rp->qe_buf_len = -(m->m_ext.ext_size - 2)/2; 794 795 return (0); 796 } 797 798 /* 799 * Create a setup packet and put in queue for sending. 800 */ 801 void 802 qe_setup(sc) 803 struct qe_softc *sc; 804 { 805 struct ether_multi *enm; 806 struct ether_multistep step; 807 struct qe_cdata *qc = sc->sc_qedata; 808 struct ifnet *ifp = &sc->sc_if; 809 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 810 int i, j, k, idx, s; 811 812 s = splimp(); 813 if (sc->sc_inq == (TXDESCS - 1)) { 814 sc->sc_setup = 1; 815 splx(s); 816 return; 817 } 818 sc->sc_setup = 0; 819 /* 820 * Init the setup packet with valid info. 821 */ 822 memset(qc->qc_setup, 0xff, sizeof(qc->qc_setup)); /* Broadcast */ 823 for (i = 0; i < ETHER_ADDR_LEN; i++) 824 qc->qc_setup[i * 8 + 1] = enaddr[i]; /* Own address */ 825 826 /* 827 * Multicast handling. The DEQNA can handle up to 12 direct 828 * ethernet addresses. 829 */ 830 j = 3; k = 0; 831 ifp->if_flags &= ~IFF_ALLMULTI; 832 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 833 while (enm != NULL) { 834 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 835 ifp->if_flags |= IFF_ALLMULTI; 836 break; 837 } 838 for (i = 0; i < ETHER_ADDR_LEN; i++) 839 qc->qc_setup[i * 8 + j + k] = enm->enm_addrlo[i]; 840 j++; 841 if (j == 8) { 842 j = 1; k += 64; 843 } 844 if (k > 64) { 845 ifp->if_flags |= IFF_ALLMULTI; 846 break; 847 } 848 ETHER_NEXT_MULTI(step, enm); 849 } 850 idx = sc->sc_nexttx; 851 qc->qc_xmit[idx].qe_buf_len = -64; 852 853 /* 854 * How is the DEQNA turned in ALLMULTI mode??? 855 * Until someone tells me, fall back to PROMISC when more than 856 * 12 ethernet addresses. 857 */ 858 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 859 qc->qc_xmit[idx].qe_buf_len = -65; 860 861 qc->qc_xmit[idx].qe_addr_lo = LOWORD(sc->sc_pqedata->qc_setup); 862 qc->qc_xmit[idx].qe_addr_hi = 863 HIWORD(sc->sc_pqedata->qc_setup) | QE_SETUP | QE_EOMSG; 864 qc->qc_xmit[idx].qe_status1 = qc->qc_xmit[idx].qe_flag = QE_NOTYET; 865 qc->qc_xmit[idx].qe_addr_hi |= QE_VALID; 866 867 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 868 QE_WCSR(QE_CSR_XMTL, 869 LOWORD(&sc->sc_pqedata->qc_xmit[idx])); 870 QE_WCSR(QE_CSR_XMTH, 871 HIWORD(&sc->sc_pqedata->qc_xmit[idx])); 872 } 873 874 sc->sc_inq++; 875 if (++sc->sc_nexttx == TXDESCS) 876 sc->sc_nexttx = 0; 877 splx(s); 878 } 879 880 /* 881 * Check for dead transmit logic. Not uncommon. 882 */ 883 void 884 qetimeout(ifp) 885 struct ifnet *ifp; 886 { 887 struct qe_softc *sc = ifp->if_softc; 888 889 if (sc->sc_inq == 0) 890 return; 891 892 printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname); 893 /* 894 * Do a reset of interface, to get it going again. 895 * Will it work by just restart the transmit logic? 896 */ 897 qeinit(sc); 898 } 899
Indexes created Tue Sep 30 07:10:03 GMT 2025