if_qe.c revision 1.38.2.2
1 /* $NetBSD: if_qe.c,v 1.38.2.2 2000/11/22 16:04:44 bouyer Exp $ */ 2 /* 3 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for DEQNA/DELQA ethernet cards. 34 * Things that is still to do: 35 * Have a timeout check for hang transmit logic. 36 * Handle ubaresets. Does not work at all right now. 37 * Fix ALLMULTI reception. But someone must tell me how... 38 * Collect statistics. 39 */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 44 #include <sys/param.h> 45 #include <sys/mbuf.h> 46 #include <sys/socket.h> 47 #include <sys/device.h> 48 #include <sys/systm.h> 49 #include <sys/sockio.h> 50 51 #include <net/if.h> 52 #include <net/if_ether.h> 53 #include <net/if_dl.h> 54 55 #include <netinet/in.h> 56 #include <netinet/if_inarp.h> 57 58 #if NBPFILTER > 0 59 #include <net/bpf.h> 60 #include <net/bpfdesc.h> 61 #endif 62 63 #include <machine/bus.h> 64 65 #include <dev/qbus/ubavar.h> 66 #include <dev/qbus/if_qereg.h> 67 68 #include "ioconf.h" 69 70 #define RXDESCS 30 /* # of receive descriptors */ 71 #define TXDESCS 60 /* # transmit descs */ 72 73 /* 74 * Structure containing the elements that must be in DMA-safe memory. 75 */ 76 struct qe_cdata { 77 struct qe_ring qc_recv[RXDESCS+1]; /* Receive descriptors */ 78 struct qe_ring qc_xmit[TXDESCS+1]; /* Transmit descriptors */ 79 u_int8_t qc_setup[128]; /* Setup packet layout */ 80 }; 81 82 struct qe_softc { 83 struct device sc_dev; /* Configuration common part */ 84 struct evcnt sc_intrcnt; /* Interrupt counting */ 85 struct ethercom sc_ec; /* Ethernet common part */ 86 #define sc_if sc_ec.ec_if /* network-visible interface */ 87 bus_space_tag_t sc_iot; 88 bus_addr_t sc_ioh; 89 bus_dma_tag_t sc_dmat; 90 struct qe_cdata *sc_qedata; /* Descriptor struct */ 91 struct qe_cdata *sc_pqedata; /* Unibus address of above */ 92 bus_dmamap_t sc_cmap; /* Map for control structures */ 93 struct mbuf* sc_txmbuf[TXDESCS]; 94 struct mbuf* sc_rxmbuf[RXDESCS]; 95 bus_dmamap_t sc_xmtmap[TXDESCS]; 96 bus_dmamap_t sc_rcvmap[RXDESCS]; 97 int sc_intvec; /* Interrupt vector */ 98 int sc_nexttx; 99 int sc_inq; 100 int sc_lastack; 101 int sc_nextrx; 102 int sc_setup; /* Setup packet in queue */ 103 }; 104 105 static int qematch __P((struct device *, struct cfdata *, void *)); 106 static void qeattach __P((struct device *, struct device *, void *)); 107 static void qeinit __P((struct qe_softc *)); 108 static void qestart __P((struct ifnet *)); 109 static void qeintr __P((void *)); 110 static int qeioctl __P((struct ifnet *, u_long, caddr_t)); 111 static int qe_add_rxbuf __P((struct qe_softc *, int)); 112 static void qe_setup __P((struct qe_softc *)); 113 static void qetimeout __P((struct ifnet *)); 114 115 struct cfattach qe_ca = { 116 sizeof(struct qe_softc), qematch, qeattach 117 }; 118 119 #define QE_WCSR(csr, val) \ 120 bus_space_write_2(sc->sc_iot, sc->sc_ioh, csr, val) 121 #define QE_RCSR(csr) \ 122 bus_space_read_2(sc->sc_iot, sc->sc_ioh, csr) 123 124 #define LOWORD(x) ((int)(x) & 0xffff) 125 #define HIWORD(x) (((int)(x) >> 16) & 0x3f) 126 127 /* 128 * Check for present DEQNA. Done by sending a fake setup packet 129 * and wait for interrupt. 130 */ 131 int 132 qematch(parent, cf, aux) 133 struct device *parent; 134 struct cfdata *cf; 135 void *aux; 136 { 137 bus_dmamap_t cmap; 138 struct qe_softc ssc; 139 struct qe_softc *sc = &ssc; 140 struct uba_attach_args *ua = aux; 141 struct uba_softc *ubasc = (struct uba_softc *)parent; 142 143 #define PROBESIZE (sizeof(struct qe_ring) * 4 + 128) 144 struct qe_ring ring[15]; /* For diag purposes only */ 145 struct qe_ring *rp; 146 int error; 147 148 bzero(sc, sizeof(struct qe_softc)); 149 bzero(ring, PROBESIZE); 150 sc->sc_iot = ua->ua_iot; 151 sc->sc_ioh = ua->ua_ioh; 152 sc->sc_dmat = ua->ua_dmat; 153 154 ubasc->uh_lastiv -= 4; 155 QE_WCSR(QE_CSR_CSR, QE_RESET); 156 QE_WCSR(QE_CSR_VECTOR, ubasc->uh_lastiv); 157 158 /* 159 * Map the ring area. Actually this is done only to be able to 160 * send and receive a internal packet; some junk is loopbacked 161 * so that the DEQNA has a reason to interrupt. 162 */ 163 if ((error = bus_dmamap_create(sc->sc_dmat, PROBESIZE, 1, PROBESIZE, 0, 164 BUS_DMA_NOWAIT, &cmap))) { 165 printf("qematch: bus_dmamap_create failed = %d\n", error); 166 return 0; 167 } 168 if ((error = bus_dmamap_load(sc->sc_dmat, cmap, ring, PROBESIZE, 0, 169 BUS_DMA_NOWAIT))) { 170 printf("qematch: bus_dmamap_load failed = %d\n", error); 171 bus_dmamap_destroy(sc->sc_dmat, cmap); 172 return 0; 173 } 174 175 /* 176 * Init a simple "fake" receive and transmit descriptor that 177 * points to some unused area. Send a fake setup packet. 178 */ 179 rp = (void *)cmap->dm_segs[0].ds_addr; 180 ring[0].qe_flag = ring[0].qe_status1 = QE_NOTYET; 181 ring[0].qe_addr_lo = LOWORD(&rp[4]); 182 ring[0].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID | QE_EOMSG | QE_SETUP; 183 ring[0].qe_buf_len = 128; 184 185 ring[2].qe_flag = ring[2].qe_status1 = QE_NOTYET; 186 ring[2].qe_addr_lo = LOWORD(&rp[4]); 187 ring[2].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID; 188 ring[2].qe_buf_len = 128; 189 190 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 191 DELAY(1000); 192 193 /* 194 * Start the interface and wait for the packet. 195 */ 196 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 197 QE_WCSR(QE_CSR_RCLL, LOWORD(&rp[2])); 198 QE_WCSR(QE_CSR_RCLH, HIWORD(&rp[2])); 199 QE_WCSR(QE_CSR_XMTL, LOWORD(rp)); 200 QE_WCSR(QE_CSR_XMTH, HIWORD(rp)); 201 DELAY(10000); 202 203 /* 204 * All done with the bus resources. 205 */ 206 bus_dmamap_unload(sc->sc_dmat, cmap); 207 bus_dmamap_destroy(sc->sc_dmat, cmap); 208 return 1; 209 } 210 211 /* 212 * Interface exists: make available by filling in network interface 213 * record. System will initialize the interface when it is ready 214 * to accept packets. 215 */ 216 void 217 qeattach(parent, self, aux) 218 struct device *parent, *self; 219 void *aux; 220 { 221 struct uba_attach_args *ua = aux; 222 struct uba_softc *ubasc = (struct uba_softc *)parent; 223 struct qe_softc *sc = (struct qe_softc *)self; 224 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 225 struct qe_ring *rp; 226 u_int8_t enaddr[ETHER_ADDR_LEN]; 227 bus_dma_segment_t seg; 228 int i, rseg, error; 229 230 sc->sc_iot = ua->ua_iot; 231 sc->sc_ioh = ua->ua_ioh; 232 sc->sc_dmat = ua->ua_dmat; 233 234 /* 235 * Allocate DMA safe memory for descriptors and setup memory. 236 */ 237 if ((error = bus_dmamem_alloc(sc->sc_dmat, 238 sizeof(struct qe_cdata), NBPG, 0, &seg, 1, &rseg, 239 BUS_DMA_NOWAIT)) != 0) { 240 printf(": unable to allocate control data, error = %d\n", 241 error); 242 goto fail_0; 243 } 244 245 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 246 sizeof(struct qe_cdata), (caddr_t *)&sc->sc_qedata, 247 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 248 printf(": unable to map control data, error = %d\n", error); 249 goto fail_1; 250 } 251 252 if ((error = bus_dmamap_create(sc->sc_dmat, 253 sizeof(struct qe_cdata), 1, 254 sizeof(struct qe_cdata), 0, BUS_DMA_NOWAIT, 255 &sc->sc_cmap)) != 0) { 256 printf(": unable to create control data DMA map, error = %d\n", 257 error); 258 goto fail_2; 259 } 260 261 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap, 262 sc->sc_qedata, sizeof(struct qe_cdata), NULL, 263 BUS_DMA_NOWAIT)) != 0) { 264 printf(": unable to load control data DMA map, error = %d\n", 265 error); 266 goto fail_3; 267 } 268 269 /* 270 * Zero the newly allocated memory. 271 */ 272 bzero(sc->sc_qedata, sizeof(struct qe_cdata)); 273 /* 274 * Create the transmit descriptor DMA maps. We take advantage 275 * of the fact that the Qbus address space is big, and therefore 276 * allocate map registers for all transmit descriptors also, 277 * so that we can avoid this each time we send a packet. 278 */ 279 for (i = 0; i < TXDESCS; i++) { 280 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 281 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 282 &sc->sc_xmtmap[i]))) { 283 printf(": unable to create tx DMA map %d, error = %d\n", 284 i, error); 285 goto fail_4; 286 } 287 } 288 289 /* 290 * Create receive buffer DMA maps. 291 */ 292 for (i = 0; i < RXDESCS; i++) { 293 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 294 MCLBYTES, 0, BUS_DMA_NOWAIT, 295 &sc->sc_rcvmap[i]))) { 296 printf(": unable to create rx DMA map %d, error = %d\n", 297 i, error); 298 goto fail_5; 299 } 300 } 301 /* 302 * Pre-allocate the receive buffers. 303 */ 304 for (i = 0; i < RXDESCS; i++) { 305 if ((error = qe_add_rxbuf(sc, i)) != 0) { 306 printf(": unable to allocate or map rx buffer %d\n," 307 " error = %d\n", i, error); 308 goto fail_6; 309 } 310 } 311 312 /* 313 * Create ring loops of the buffer chains. 314 * This is only done once. 315 */ 316 sc->sc_pqedata = (struct qe_cdata *)sc->sc_cmap->dm_segs[0].ds_addr; 317 318 rp = sc->sc_qedata->qc_recv; 319 rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]); 320 rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) | 321 QE_VALID | QE_CHAIN; 322 rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET; 323 324 rp = sc->sc_qedata->qc_xmit; 325 rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]); 326 rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) | 327 QE_VALID | QE_CHAIN; 328 rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET; 329 330 /* 331 * Get the vector that were set at match time, and remember it. 332 */ 333 sc->sc_intvec = ubasc->uh_lastiv; 334 QE_WCSR(QE_CSR_CSR, QE_RESET); 335 DELAY(1000); 336 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 337 338 /* 339 * Read out ethernet address and tell which type this card is. 340 */ 341 for (i = 0; i < 6; i++) 342 enaddr[i] = QE_RCSR(i * 2) & 0xff; 343 344 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1); 345 printf("\n%s: %s, hardware address %s\n", sc->sc_dev.dv_xname, 346 QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna", 347 ether_sprintf(enaddr)); 348 349 QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */ 350 351 uba_intr_establish(ua->ua_icookie, ua->ua_cvec, qeintr, 352 sc, &sc->sc_intrcnt); 353 evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt, 354 sc->sc_dev.dv_xname, "intr"); 355 356 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 357 ifp->if_softc = sc; 358 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 359 ifp->if_start = qestart; 360 ifp->if_ioctl = qeioctl; 361 ifp->if_watchdog = qetimeout; 362 363 /* 364 * Attach the interface. 365 */ 366 if_attach(ifp); 367 ether_ifattach(ifp, enaddr); 368 369 return; 370 371 /* 372 * Free any resources we've allocated during the failed attach 373 * attempt. Do this in reverse order and fall through. 374 */ 375 fail_6: 376 for (i = 0; i < RXDESCS; i++) { 377 if (sc->sc_rxmbuf[i] != NULL) { 378 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 379 m_freem(sc->sc_rxmbuf[i]); 380 } 381 } 382 fail_5: 383 for (i = 0; i < RXDESCS; i++) { 384 if (sc->sc_xmtmap[i] != NULL) 385 bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]); 386 } 387 fail_4: 388 for (i = 0; i < TXDESCS; i++) { 389 if (sc->sc_rcvmap[i] != NULL) 390 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]); 391 } 392 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmap); 393 fail_3: 394 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap); 395 fail_2: 396 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_qedata, 397 sizeof(struct qe_cdata)); 398 fail_1: 399 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 400 fail_0: 401 return; 402 } 403 404 /* 405 * Initialization of interface. 406 */ 407 void 408 qeinit(sc) 409 struct qe_softc *sc; 410 { 411 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 412 struct qe_cdata *qc = sc->sc_qedata; 413 int i; 414 415 416 /* 417 * Reset the interface. 418 */ 419 QE_WCSR(QE_CSR_CSR, QE_RESET); 420 DELAY(1000); 421 QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET); 422 QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec); 423 424 sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0; 425 /* 426 * Release and init transmit descriptors. 427 */ 428 for (i = 0; i < TXDESCS; i++) { 429 if (sc->sc_txmbuf[i]) { 430 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 431 m_freem(sc->sc_txmbuf[i]); 432 sc->sc_txmbuf[i] = 0; 433 } 434 qc->qc_xmit[i].qe_addr_hi = 0; /* Clear valid bit */ 435 qc->qc_xmit[i].qe_status1 = qc->qc_xmit[i].qe_flag = QE_NOTYET; 436 } 437 438 439 /* 440 * Init receive descriptors. 441 */ 442 for (i = 0; i < RXDESCS; i++) 443 qc->qc_recv[i].qe_status1 = qc->qc_recv[i].qe_flag = QE_NOTYET; 444 sc->sc_nextrx = 0; 445 446 /* 447 * Write the descriptor addresses to the device. 448 * Receiving packets will be enabled in the interrupt routine. 449 */ 450 QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT); 451 QE_WCSR(QE_CSR_RCLL, LOWORD(sc->sc_pqedata->qc_recv)); 452 QE_WCSR(QE_CSR_RCLH, HIWORD(sc->sc_pqedata->qc_recv)); 453 454 ifp->if_flags |= IFF_RUNNING; 455 ifp->if_flags &= ~IFF_OACTIVE; 456 457 /* 458 * Send a setup frame. 459 * This will start the transmit machinery as well. 460 */ 461 qe_setup(sc); 462 463 } 464 465 /* 466 * Start output on interface. 467 */ 468 void 469 qestart(ifp) 470 struct ifnet *ifp; 471 { 472 struct qe_softc *sc = ifp->if_softc; 473 struct qe_cdata *qc = sc->sc_qedata; 474 paddr_t buffer; 475 struct mbuf *m, *m0; 476 int idx, len, s, i, totlen, error; 477 short orword; 478 479 if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_ENABLE) == 0) 480 return; 481 482 s = splimp(); 483 while (sc->sc_inq < (TXDESCS - 1)) { 484 485 if (sc->sc_setup) { 486 qe_setup(sc); 487 continue; 488 } 489 idx = sc->sc_nexttx; 490 IF_DEQUEUE(&sc->sc_if.if_snd, m); 491 if (m == 0) 492 goto out; 493 /* 494 * Count number of mbufs in chain. 495 * Always do DMA directly from mbufs, therefore the transmit 496 * ring is really big. 497 */ 498 for (m0 = m, i = 0; m0; m0 = m0->m_next) 499 if (m0->m_len) 500 i++; 501 if (i >= TXDESCS) 502 panic("qestart"); 503 504 if ((i + sc->sc_inq) >= (TXDESCS - 1)) { 505 IF_PREPEND(&sc->sc_if.if_snd, m); 506 ifp->if_flags |= IFF_OACTIVE; 507 goto out; 508 } 509 510 #if NBPFILTER > 0 511 if (ifp->if_bpf) 512 bpf_mtap(ifp->if_bpf, m); 513 #endif 514 /* 515 * m now points to a mbuf chain that can be loaded. 516 * Loop around and set it. 517 */ 518 totlen = 0; 519 for (m0 = m; m0; m0 = m0->m_next) { 520 error = bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx], 521 mtod(m0, void *), m0->m_len, 0, 0); 522 buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr; 523 len = m0->m_len; 524 if (len == 0) 525 continue; 526 527 totlen += len; 528 /* Word alignment calc */ 529 orword = 0; 530 if (totlen == m->m_pkthdr.len) { 531 if (totlen < ETHER_MIN_LEN) 532 len += (ETHER_MIN_LEN - totlen); 533 orword |= QE_EOMSG; 534 sc->sc_txmbuf[idx] = m; 535 } 536 if ((buffer & 1) || (len & 1)) 537 len += 2; 538 if (buffer & 1) 539 orword |= QE_ODDBEGIN; 540 if ((buffer + len) & 1) 541 orword |= QE_ODDEND; 542 qc->qc_xmit[idx].qe_buf_len = -(len/2); 543 qc->qc_xmit[idx].qe_addr_lo = LOWORD(buffer); 544 qc->qc_xmit[idx].qe_addr_hi = HIWORD(buffer); 545 qc->qc_xmit[idx].qe_flag = 546 qc->qc_xmit[idx].qe_status1 = QE_NOTYET; 547 qc->qc_xmit[idx].qe_addr_hi |= (QE_VALID | orword); 548 if (++idx == TXDESCS) 549 idx = 0; 550 sc->sc_inq++; 551 } 552 #ifdef DIAGNOSTIC 553 if (totlen != m->m_pkthdr.len) 554 panic("qestart: len fault"); 555 #endif 556 557 /* 558 * Kick off the transmit logic, if it is stopped. 559 */ 560 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 561 QE_WCSR(QE_CSR_XMTL, 562 LOWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 563 QE_WCSR(QE_CSR_XMTH, 564 HIWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx])); 565 } 566 sc->sc_nexttx = idx; 567 } 568 if (sc->sc_inq == (TXDESCS - 1)) 569 ifp->if_flags |= IFF_OACTIVE; 570 571 out: if (sc->sc_inq) 572 ifp->if_timer = 5; /* If transmit logic dies */ 573 splx(s); 574 } 575 576 static void 577 qeintr(arg) 578 void *arg; 579 { 580 struct qe_softc *sc = arg; 581 struct qe_cdata *qc = sc->sc_qedata; 582 struct ifnet *ifp = &sc->sc_if; 583 struct ether_header *eh; 584 struct mbuf *m; 585 int csr, status1, status2, len; 586 587 csr = QE_RCSR(QE_CSR_CSR); 588 589 QE_WCSR(QE_CSR_CSR, QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT | 590 QE_RCV_INT | QE_ILOOP); 591 592 if (csr & QE_RCV_INT) 593 while (qc->qc_recv[sc->sc_nextrx].qe_status1 != QE_NOTYET) { 594 status1 = qc->qc_recv[sc->sc_nextrx].qe_status1; 595 status2 = qc->qc_recv[sc->sc_nextrx].qe_status2; 596 m = sc->sc_rxmbuf[sc->sc_nextrx]; 597 len = ((status1 & QE_RBL_HI) | 598 (status2 & QE_RBL_LO)) + 60; 599 qe_add_rxbuf(sc, sc->sc_nextrx); 600 m->m_pkthdr.rcvif = ifp; 601 m->m_pkthdr.len = m->m_len = len; 602 if (++sc->sc_nextrx == RXDESCS) 603 sc->sc_nextrx = 0; 604 eh = mtod(m, struct ether_header *); 605 #if NBPFILTER > 0 606 if (ifp->if_bpf) 607 bpf_mtap(ifp->if_bpf, m); 608 #endif 609 (*ifp->if_input)(ifp, m); 610 } 611 612 if (csr & QE_XMIT_INT) { 613 while (qc->qc_xmit[sc->sc_lastack].qe_status1 != QE_NOTYET) { 614 int idx = sc->sc_lastack; 615 616 sc->sc_inq--; 617 if (++sc->sc_lastack == TXDESCS) 618 sc->sc_lastack = 0; 619 620 /* XXX collect statistics */ 621 qc->qc_xmit[idx].qe_addr_hi &= ~QE_VALID; 622 qc->qc_xmit[idx].qe_status1 = 623 qc->qc_xmit[idx].qe_flag = QE_NOTYET; 624 625 if (qc->qc_xmit[idx].qe_addr_hi & QE_SETUP) 626 continue; 627 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]); 628 if (sc->sc_txmbuf[idx]) { 629 m_freem(sc->sc_txmbuf[idx]); 630 sc->sc_txmbuf[idx] = 0; 631 } 632 } 633 ifp->if_timer = 0; 634 ifp->if_flags &= ~IFF_OACTIVE; 635 qestart(ifp); /* Put in more in queue */ 636 } 637 /* 638 * How can the receive list get invalid??? 639 * Verified that it happens anyway. 640 */ 641 if ((qc->qc_recv[sc->sc_nextrx].qe_status1 == QE_NOTYET) && 642 (QE_RCSR(QE_CSR_CSR) & QE_RL_INVALID)) { 643 QE_WCSR(QE_CSR_RCLL, 644 LOWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 645 QE_WCSR(QE_CSR_RCLH, 646 HIWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx])); 647 } 648 } 649 650 /* 651 * Process an ioctl request. 652 */ 653 int 654 qeioctl(ifp, cmd, data) 655 struct ifnet *ifp; 656 u_long cmd; 657 caddr_t data; 658 { 659 struct qe_softc *sc = ifp->if_softc; 660 struct ifreq *ifr = (struct ifreq *)data; 661 struct ifaddr *ifa = (struct ifaddr *)data; 662 int s = splnet(), error = 0; 663 664 switch (cmd) { 665 666 case SIOCSIFADDR: 667 ifp->if_flags |= IFF_UP; 668 switch(ifa->ifa_addr->sa_family) { 669 #ifdef INET 670 case AF_INET: 671 qeinit(sc); 672 arp_ifinit(ifp, ifa); 673 break; 674 #endif 675 } 676 break; 677 678 case SIOCSIFFLAGS: 679 if ((ifp->if_flags & IFF_UP) == 0 && 680 (ifp->if_flags & IFF_RUNNING) != 0) { 681 /* 682 * If interface is marked down and it is running, 683 * stop it. (by disabling receive mechanism). 684 */ 685 QE_WCSR(QE_CSR_CSR, 686 QE_RCSR(QE_CSR_CSR) & ~QE_RCV_ENABLE); 687 ifp->if_flags &= ~IFF_RUNNING; 688 } else if ((ifp->if_flags & IFF_UP) != 0 && 689 (ifp->if_flags & IFF_RUNNING) == 0) { 690 /* 691 * If interface it marked up and it is stopped, then 692 * start it. 693 */ 694 qeinit(sc); 695 } else if ((ifp->if_flags & IFF_UP) != 0) { 696 /* 697 * Send a new setup packet to match any new changes. 698 * (Like IFF_PROMISC etc) 699 */ 700 qe_setup(sc); 701 } 702 break; 703 704 case SIOCADDMULTI: 705 case SIOCDELMULTI: 706 /* 707 * Update our multicast list. 708 */ 709 error = (cmd == SIOCADDMULTI) ? 710 ether_addmulti(ifr, &sc->sc_ec): 711 ether_delmulti(ifr, &sc->sc_ec); 712 713 if (error == ENETRESET) { 714 /* 715 * Multicast list has changed; set the hardware filter 716 * accordingly. 717 */ 718 qe_setup(sc); 719 error = 0; 720 } 721 break; 722 723 default: 724 error = EINVAL; 725 726 } 727 splx(s); 728 return (error); 729 } 730 731 /* 732 * Add a receive buffer to the indicated descriptor. 733 */ 734 int 735 qe_add_rxbuf(sc, i) 736 struct qe_softc *sc; 737 int i; 738 { 739 struct mbuf *m; 740 struct qe_ring *rp; 741 vaddr_t addr; 742 int error; 743 744 MGETHDR(m, M_DONTWAIT, MT_DATA); 745 if (m == NULL) 746 return (ENOBUFS); 747 748 MCLGET(m, M_DONTWAIT); 749 if ((m->m_flags & M_EXT) == 0) { 750 m_freem(m); 751 return (ENOBUFS); 752 } 753 754 if (sc->sc_rxmbuf[i] != NULL) 755 bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]); 756 757 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i], 758 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 759 if (error) 760 panic("%s: can't load rx DMA map %d, error = %d\n", 761 sc->sc_dev.dv_xname, i, error); 762 sc->sc_rxmbuf[i] = m; 763 764 bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0, 765 sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 766 767 /* 768 * We know that the mbuf cluster is page aligned. Also, be sure 769 * that the IP header will be longword aligned. 770 */ 771 m->m_data += 2; 772 addr = sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2; 773 rp = &sc->sc_qedata->qc_recv[i]; 774 rp->qe_flag = rp->qe_status1 = QE_NOTYET; 775 rp->qe_addr_lo = LOWORD(addr); 776 rp->qe_addr_hi = HIWORD(addr) | QE_VALID; 777 rp->qe_buf_len = -(m->m_ext.ext_size - 2)/2; 778 779 return (0); 780 } 781 782 /* 783 * Create a setup packet and put in queue for sending. 784 */ 785 void 786 qe_setup(sc) 787 struct qe_softc *sc; 788 { 789 struct ether_multi *enm; 790 struct ether_multistep step; 791 struct qe_cdata *qc = sc->sc_qedata; 792 struct ifnet *ifp = &sc->sc_if; 793 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 794 int i, j, k, idx, s; 795 796 s = splimp(); 797 if (sc->sc_inq == (TXDESCS - 1)) { 798 sc->sc_setup = 1; 799 splx(s); 800 return; 801 } 802 sc->sc_setup = 0; 803 /* 804 * Init the setup packet with valid info. 805 */ 806 memset(qc->qc_setup, 0xff, sizeof(qc->qc_setup)); /* Broadcast */ 807 for (i = 0; i < ETHER_ADDR_LEN; i++) 808 qc->qc_setup[i * 8 + 1] = enaddr[i]; /* Own address */ 809 810 /* 811 * Multicast handling. The DEQNA can handle up to 12 direct 812 * ethernet addresses. 813 */ 814 j = 3; k = 0; 815 ifp->if_flags &= ~IFF_ALLMULTI; 816 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 817 while (enm != NULL) { 818 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 819 ifp->if_flags |= IFF_ALLMULTI; 820 break; 821 } 822 for (i = 0; i < ETHER_ADDR_LEN; i++) 823 qc->qc_setup[i * 8 + j + k] = enm->enm_addrlo[i]; 824 j++; 825 if (j == 8) { 826 j = 1; k += 64; 827 } 828 if (k > 64) { 829 ifp->if_flags |= IFF_ALLMULTI; 830 break; 831 } 832 ETHER_NEXT_MULTI(step, enm); 833 } 834 idx = sc->sc_nexttx; 835 qc->qc_xmit[idx].qe_buf_len = -64; 836 837 /* 838 * How is the DEQNA turned in ALLMULTI mode??? 839 * Until someone tells me, fall back to PROMISC when more than 840 * 12 ethernet addresses. 841 */ 842 if (ifp->if_flags & IFF_ALLMULTI) 843 ifp->if_flags |= IFF_PROMISC; 844 else if (ifp->if_pcount == 0) 845 ifp->if_flags &= ~IFF_PROMISC; 846 if (ifp->if_flags & IFF_PROMISC) 847 qc->qc_xmit[idx].qe_buf_len = -65; 848 849 qc->qc_xmit[idx].qe_addr_lo = LOWORD(sc->sc_pqedata->qc_setup); 850 qc->qc_xmit[idx].qe_addr_hi = 851 HIWORD(sc->sc_pqedata->qc_setup) | QE_SETUP | QE_EOMSG; 852 qc->qc_xmit[idx].qe_status1 = qc->qc_xmit[idx].qe_flag = QE_NOTYET; 853 qc->qc_xmit[idx].qe_addr_hi |= QE_VALID; 854 855 if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) { 856 QE_WCSR(QE_CSR_XMTL, 857 LOWORD(&sc->sc_pqedata->qc_xmit[idx])); 858 QE_WCSR(QE_CSR_XMTH, 859 HIWORD(&sc->sc_pqedata->qc_xmit[idx])); 860 } 861 862 sc->sc_inq++; 863 if (++sc->sc_nexttx == TXDESCS) 864 sc->sc_nexttx = 0; 865 splx(s); 866 } 867 868 /* 869 * Check for dead transmit logic. Not uncommon. 870 */ 871 void 872 qetimeout(ifp) 873 struct ifnet *ifp; 874 { 875 struct qe_softc *sc = ifp->if_softc; 876 877 if (sc->sc_inq == 0) 878 return; 879 880 printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname); 881 /* 882 * Do a reset of interface, to get it going again. 883 * Will it work by just restart the transmit logic? 884 */ 885 qeinit(sc); 886 } 887
Indexes created Fri Oct 17 09:09:57 GMT 2025