be.c revision 1.17 1 1.17 thorpej /* $NetBSD: be.c,v 1.17 2000/03/23 07:01:43 thorpej Exp $ */
2 1.1 pk
3 1.1 pk /*-
4 1.1 pk * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 1.1 pk * All rights reserved.
6 1.1 pk *
7 1.1 pk * This code is derived from software contributed to The NetBSD Foundation
8 1.1 pk * by Paul Kranenburg.
9 1.1 pk *
10 1.1 pk * Redistribution and use in source and binary forms, with or without
11 1.1 pk * modification, are permitted provided that the following conditions
12 1.1 pk * are met:
13 1.1 pk * 1. Redistributions of source code must retain the above copyright
14 1.1 pk * notice, this list of conditions and the following disclaimer.
15 1.1 pk * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 pk * notice, this list of conditions and the following disclaimer in the
17 1.1 pk * documentation and/or other materials provided with the distribution.
18 1.1 pk * 3. All advertising materials mentioning features or use of this software
19 1.1 pk * must display the following acknowledgement:
20 1.1 pk * This product includes software developed by the NetBSD
21 1.1 pk * Foundation, Inc. and its contributors.
22 1.1 pk * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 pk * contributors may be used to endorse or promote products derived
24 1.1 pk * from this software without specific prior written permission.
25 1.1 pk *
26 1.1 pk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 pk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 pk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 pk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 pk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 pk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 pk * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 pk * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 pk * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 pk * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 pk * POSSIBILITY OF SUCH DAMAGE.
37 1.1 pk */
38 1.1 pk
39 1.1 pk /*
40 1.1 pk * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
41 1.1 pk * All rights reserved.
42 1.1 pk *
43 1.1 pk * Redistribution and use in source and binary forms, with or without
44 1.1 pk * modification, are permitted provided that the following conditions
45 1.1 pk * are met:
46 1.1 pk * 1. Redistributions of source code must retain the above copyright
47 1.1 pk * notice, this list of conditions and the following disclaimer.
48 1.1 pk * 2. Redistributions in binary form must reproduce the above copyright
49 1.1 pk * notice, this list of conditions and the following disclaimer in the
50 1.1 pk * documentation and/or other materials provided with the distribution.
51 1.1 pk * 3. The name of the authors may not be used to endorse or promote products
52 1.1 pk * derived from this software without specific prior written permission.
53 1.1 pk *
54 1.1 pk * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
55 1.1 pk * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56 1.1 pk * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57 1.1 pk * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 1.1 pk * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59 1.1 pk * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 1.1 pk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 1.1 pk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 1.1 pk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63 1.1 pk * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 1.1 pk */
65 1.1 pk
66 1.1 pk #include "opt_ddb.h"
67 1.1 pk #include "opt_inet.h"
68 1.1 pk #include "opt_ccitt.h"
69 1.1 pk #include "opt_llc.h"
70 1.1 pk #include "opt_ns.h"
71 1.1 pk #include "bpfilter.h"
72 1.1 pk #include "rnd.h"
73 1.1 pk
74 1.1 pk #include <sys/param.h>
75 1.1 pk #include <sys/systm.h>
76 1.17 thorpej #include <sys/callout.h>
77 1.1 pk #include <sys/kernel.h>
78 1.1 pk #include <sys/errno.h>
79 1.1 pk #include <sys/ioctl.h>
80 1.1 pk #include <sys/mbuf.h>
81 1.1 pk #include <sys/socket.h>
82 1.1 pk #include <sys/syslog.h>
83 1.1 pk #include <sys/device.h>
84 1.1 pk #include <sys/malloc.h>
85 1.1 pk #if NRND > 0
86 1.1 pk #include <sys/rnd.h>
87 1.1 pk #endif
88 1.1 pk
89 1.1 pk #include <net/if.h>
90 1.1 pk #include <net/if_dl.h>
91 1.1 pk #include <net/if_types.h>
92 1.1 pk #include <net/netisr.h>
93 1.1 pk #include <net/if_media.h>
94 1.1 pk #include <net/if_ether.h>
95 1.1 pk
96 1.1 pk #ifdef INET
97 1.1 pk #include <netinet/in.h>
98 1.1 pk #include <netinet/if_inarp.h>
99 1.1 pk #include <netinet/in_systm.h>
100 1.1 pk #include <netinet/in_var.h>
101 1.1 pk #include <netinet/ip.h>
102 1.1 pk #endif
103 1.1 pk
104 1.3 pk #ifdef NS
105 1.3 pk #include <netns/ns.h>
106 1.3 pk #include <netns/ns_if.h>
107 1.3 pk #endif
108 1.3 pk
109 1.1 pk #if NBPFILTER > 0
110 1.1 pk #include <net/bpf.h>
111 1.1 pk #include <net/bpfdesc.h>
112 1.1 pk #endif
113 1.1 pk
114 1.1 pk #include <machine/autoconf.h>
115 1.1 pk #include <machine/cpu.h>
116 1.1 pk
117 1.1 pk #include <dev/sbus/sbusvar.h>
118 1.1 pk
119 1.1 pk #include <dev/mii/mii.h>
120 1.1 pk #include <dev/mii/miivar.h>
121 1.1 pk
122 1.1 pk #include <dev/sbus/qecreg.h>
123 1.1 pk #include <dev/sbus/qecvar.h>
124 1.1 pk #include <dev/sbus/bereg.h>
125 1.1 pk
126 1.1 pk struct be_softc {
127 1.1 pk struct device sc_dev;
128 1.1 pk struct sbusdev sc_sd; /* sbus device */
129 1.1 pk bus_space_tag_t sc_bustag; /* bus & dma tags */
130 1.1 pk bus_dma_tag_t sc_dmatag;
131 1.1 pk struct ethercom sc_ethercom;
132 1.1 pk /*struct ifmedia sc_ifmedia; -* interface media */
133 1.1 pk struct mii_data sc_mii; /* MII media control */
134 1.1 pk #define sc_media sc_mii.mii_media/* shorthand */
135 1.11 pk int sc_phys[2]; /* MII instance -> phy */
136 1.1 pk
137 1.17 thorpej struct callout sc_tick_ch;
138 1.17 thorpej
139 1.12 pk /*
140 1.12 pk * Some `mii_softc' items we need to emulate MII operation
141 1.12 pk * for our internal transceiver.
142 1.12 pk */
143 1.12 pk int sc_mii_inst; /* instance of internal phy */
144 1.12 pk int sc_mii_active; /* currently active medium */
145 1.12 pk int sc_mii_ticks; /* tick counter */
146 1.13 pk int sc_mii_flags; /* phy status flags */
147 1.13 pk #define MIIF_HAVELINK 0x04000000
148 1.13 pk int sc_intphy_curspeed; /* Established link speed */
149 1.12 pk
150 1.1 pk struct qec_softc *sc_qec; /* QEC parent */
151 1.1 pk
152 1.1 pk bus_space_handle_t sc_qr; /* QEC registers */
153 1.1 pk bus_space_handle_t sc_br; /* BE registers */
154 1.1 pk bus_space_handle_t sc_cr; /* channel registers */
155 1.1 pk bus_space_handle_t sc_tr; /* transceiver registers */
156 1.1 pk
157 1.1 pk u_int sc_rev;
158 1.1 pk
159 1.1 pk int sc_channel; /* channel number */
160 1.1 pk int sc_burst;
161 1.1 pk
162 1.2 pk struct qec_ring sc_rb; /* Packet Ring Buffer */
163 1.1 pk
164 1.1 pk /* MAC address */
165 1.1 pk u_int8_t sc_enaddr[6];
166 1.1 pk };
167 1.1 pk
168 1.1 pk int bematch __P((struct device *, struct cfdata *, void *));
169 1.1 pk void beattach __P((struct device *, struct device *, void *));
170 1.1 pk
171 1.1 pk void beinit __P((struct be_softc *));
172 1.1 pk void bestart __P((struct ifnet *));
173 1.1 pk void bestop __P((struct be_softc *));
174 1.1 pk void bewatchdog __P((struct ifnet *));
175 1.1 pk int beioctl __P((struct ifnet *, u_long, caddr_t));
176 1.1 pk void bereset __P((struct be_softc *));
177 1.1 pk
178 1.1 pk int beintr __P((void *));
179 1.1 pk int berint __P((struct be_softc *));
180 1.1 pk int betint __P((struct be_softc *));
181 1.1 pk int beqint __P((struct be_softc *, u_int32_t));
182 1.1 pk int beeint __P((struct be_softc *, u_int32_t));
183 1.1 pk
184 1.1 pk static void be_read __P((struct be_softc *, int, int));
185 1.1 pk static int be_put __P((struct be_softc *, int, struct mbuf *));
186 1.1 pk static struct mbuf *be_get __P((struct be_softc *, int, int));
187 1.1 pk
188 1.11 pk void be_pal_gate __P((struct be_softc *, int));
189 1.1 pk
190 1.1 pk /* ifmedia callbacks */
191 1.1 pk void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
192 1.1 pk int be_ifmedia_upd __P((struct ifnet *));
193 1.2 pk
194 1.1 pk void be_mcreset __P((struct be_softc *));
195 1.1 pk
196 1.1 pk /* MII methods & callbacks */
197 1.1 pk static int be_mii_readreg __P((struct device *, int, int));
198 1.1 pk static void be_mii_writereg __P((struct device *, int, int, int));
199 1.10 pk static void be_mii_statchg __P((struct device *));
200 1.1 pk
201 1.1 pk /* MII helpers */
202 1.1 pk static void be_mii_sync __P((struct be_softc *));
203 1.1 pk static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int));
204 1.1 pk static int be_mii_reset __P((struct be_softc *, int));
205 1.1 pk static int be_tcvr_read_bit __P((struct be_softc *, int));
206 1.1 pk static void be_tcvr_write_bit __P((struct be_softc *, int, int));
207 1.1 pk
208 1.12 pk void be_tick __P((void *));
209 1.12 pk void be_intphy_auto __P((struct be_softc *));
210 1.12 pk void be_intphy_status __P((struct be_softc *));
211 1.12 pk int be_intphy_service __P((struct be_softc *, struct mii_data *, int));
212 1.1 pk
213 1.1 pk
214 1.1 pk struct cfattach be_ca = {
215 1.1 pk sizeof(struct be_softc), bematch, beattach
216 1.1 pk };
217 1.1 pk
218 1.1 pk int
219 1.1 pk bematch(parent, cf, aux)
220 1.1 pk struct device *parent;
221 1.1 pk struct cfdata *cf;
222 1.1 pk void *aux;
223 1.1 pk {
224 1.1 pk struct sbus_attach_args *sa = aux;
225 1.1 pk
226 1.1 pk return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
227 1.1 pk }
228 1.1 pk
229 1.1 pk void
230 1.1 pk beattach(parent, self, aux)
231 1.1 pk struct device *parent, *self;
232 1.1 pk void *aux;
233 1.1 pk {
234 1.1 pk struct sbus_attach_args *sa = aux;
235 1.1 pk struct qec_softc *qec = (struct qec_softc *)parent;
236 1.1 pk struct be_softc *sc = (struct be_softc *)self;
237 1.1 pk struct ifnet *ifp = &sc->sc_ethercom.ec_if;
238 1.1 pk struct mii_data *mii = &sc->sc_mii;
239 1.11 pk struct mii_softc *child;
240 1.11 pk int instance;
241 1.1 pk int node = sa->sa_node;
242 1.1 pk bus_dma_segment_t seg;
243 1.1 pk bus_size_t size;
244 1.1 pk int rseg, error;
245 1.11 pk u_int32_t v;
246 1.1 pk extern void myetheraddr __P((u_char *));
247 1.1 pk
248 1.1 pk if (sa->sa_nreg < 3) {
249 1.1 pk printf("%s: only %d register sets\n",
250 1.1 pk self->dv_xname, sa->sa_nreg);
251 1.1 pk return;
252 1.1 pk }
253 1.1 pk
254 1.1 pk if (bus_space_map2(sa->sa_bustag,
255 1.1 pk (bus_type_t)sa->sa_reg[0].sbr_slot,
256 1.1 pk (bus_addr_t)sa->sa_reg[0].sbr_offset,
257 1.1 pk (bus_size_t)sa->sa_reg[0].sbr_size,
258 1.1 pk BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) {
259 1.1 pk printf("beattach: cannot map registers\n");
260 1.1 pk return;
261 1.1 pk }
262 1.1 pk
263 1.1 pk if (bus_space_map2(sa->sa_bustag,
264 1.1 pk (bus_type_t)sa->sa_reg[1].sbr_slot,
265 1.1 pk (bus_addr_t)sa->sa_reg[1].sbr_offset,
266 1.1 pk (bus_size_t)sa->sa_reg[1].sbr_size,
267 1.1 pk BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) {
268 1.1 pk printf("beattach: cannot map registers\n");
269 1.1 pk return;
270 1.1 pk }
271 1.1 pk
272 1.1 pk if (bus_space_map2(sa->sa_bustag,
273 1.1 pk (bus_type_t)sa->sa_reg[2].sbr_slot,
274 1.1 pk (bus_addr_t)sa->sa_reg[2].sbr_offset,
275 1.1 pk (bus_size_t)sa->sa_reg[2].sbr_size,
276 1.1 pk BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) {
277 1.1 pk printf("beattach: cannot map registers\n");
278 1.1 pk return;
279 1.1 pk }
280 1.1 pk
281 1.1 pk sc->sc_qec = qec;
282 1.1 pk sc->sc_qr = qec->sc_regs;
283 1.1 pk
284 1.1 pk sc->sc_rev = getpropint(node, "board-version", -1);
285 1.1 pk printf(" rev %x", sc->sc_rev);
286 1.1 pk
287 1.1 pk bestop(sc);
288 1.1 pk
289 1.1 pk sc->sc_channel = getpropint(node, "channel#", -1);
290 1.1 pk if (sc->sc_channel == -1)
291 1.1 pk sc->sc_channel = 0;
292 1.1 pk
293 1.1 pk sc->sc_burst = getpropint(node, "burst-sizes", -1);
294 1.1 pk if (sc->sc_burst == -1)
295 1.1 pk sc->sc_burst = qec->sc_burst;
296 1.1 pk
297 1.1 pk /* Clamp at parent's burst sizes */
298 1.1 pk sc->sc_burst &= qec->sc_burst;
299 1.1 pk
300 1.9 pk /* Establish interrupt handler */
301 1.9 pk if (sa->sa_nintr)
302 1.9 pk (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri,
303 1.9 pk 0, beintr, sc);
304 1.1 pk
305 1.1 pk myetheraddr(sc->sc_enaddr);
306 1.1 pk printf(" address %s\n", ether_sprintf(sc->sc_enaddr));
307 1.1 pk
308 1.1 pk /*
309 1.1 pk * Allocate descriptor ring and buffers.
310 1.1 pk */
311 1.2 pk
312 1.2 pk /* for now, allocate as many bufs as there are ring descriptors */
313 1.2 pk sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
314 1.2 pk sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
315 1.1 pk
316 1.1 pk size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
317 1.1 pk QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
318 1.2 pk sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ +
319 1.2 pk sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ;
320 1.1 pk if ((error = bus_dmamem_alloc(sa->sa_dmatag, size,
321 1.1 pk NBPG, 0,
322 1.1 pk &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
323 1.1 pk printf("%s: DMA buffer alloc error %d\n",
324 1.1 pk self->dv_xname, error);
325 1.1 pk return;
326 1.1 pk }
327 1.2 pk sc->sc_rb.rb_dmabase = seg.ds_addr;
328 1.1 pk
329 1.1 pk if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size,
330 1.2 pk &sc->sc_rb.rb_membase,
331 1.1 pk BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
332 1.1 pk printf("%s: DMA buffer map error %d\n",
333 1.1 pk self->dv_xname, error);
334 1.1 pk bus_dmamem_free(sa->sa_dmatag, &seg, rseg);
335 1.1 pk return;
336 1.1 pk }
337 1.1 pk
338 1.1 pk /*
339 1.1 pk * Initialize our media structures and MII info.
340 1.1 pk */
341 1.1 pk mii->mii_ifp = ifp;
342 1.1 pk mii->mii_readreg = be_mii_readreg;
343 1.1 pk mii->mii_writereg = be_mii_writereg;
344 1.10 pk mii->mii_statchg = be_mii_statchg;
345 1.1 pk
346 1.1 pk ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts);
347 1.1 pk
348 1.17 thorpej callout_init(&sc->sc_tick_ch);
349 1.17 thorpej
350 1.11 pk /*
351 1.11 pk * Initialize transceiver and determine which PHY connection to use.
352 1.11 pk */
353 1.11 pk be_mii_sync(sc);
354 1.11 pk v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL);
355 1.11 pk
356 1.11 pk instance = 0;
357 1.11 pk
358 1.11 pk if ((v & MGMT_PAL_EXT_MDIO) != 0) {
359 1.10 pk
360 1.14 thorpej mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL,
361 1.15 thorpej MII_OFFSET_ANY, 0);
362 1.1 pk
363 1.11 pk child = LIST_FIRST(&mii->mii_phys);
364 1.11 pk if (child == NULL) {
365 1.1 pk /* No PHY attached */
366 1.11 pk ifmedia_add(&sc->sc_media,
367 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance),
368 1.11 pk 0, NULL);
369 1.11 pk ifmedia_set(&sc->sc_media,
370 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance));
371 1.1 pk } else {
372 1.1 pk /*
373 1.11 pk * Note: we support just one PHY on the external
374 1.11 pk * MII connector.
375 1.11 pk */
376 1.11 pk #ifdef DIAGNOSTIC
377 1.11 pk if (LIST_NEXT(child, mii_list) != NULL) {
378 1.11 pk printf("%s: spurious MII device %s attached\n",
379 1.11 pk sc->sc_dev.dv_xname,
380 1.11 pk child->mii_dev.dv_xname);
381 1.11 pk }
382 1.11 pk #endif
383 1.11 pk if (child->mii_phy != BE_PHY_EXTERNAL ||
384 1.11 pk child->mii_inst > 0) {
385 1.11 pk printf("%s: cannot accomodate MII device %s"
386 1.11 pk " at phy %d, instance %d\n",
387 1.11 pk sc->sc_dev.dv_xname,
388 1.11 pk child->mii_dev.dv_xname,
389 1.11 pk child->mii_phy, child->mii_inst);
390 1.11 pk } else {
391 1.11 pk sc->sc_phys[instance] = child->mii_phy;
392 1.11 pk }
393 1.11 pk
394 1.11 pk /*
395 1.1 pk * XXX - we can really do the following ONLY if the
396 1.1 pk * phy indeed has the auto negotiation capability!!
397 1.1 pk */
398 1.11 pk ifmedia_set(&sc->sc_media,
399 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance));
400 1.11 pk
401 1.11 pk /* Mark our current media setting */
402 1.11 pk be_pal_gate(sc, BE_PHY_EXTERNAL);
403 1.11 pk instance++;
404 1.1 pk }
405 1.11 pk
406 1.11 pk }
407 1.11 pk
408 1.11 pk if ((v & MGMT_PAL_INT_MDIO) != 0) {
409 1.1 pk /*
410 1.1 pk * The be internal phy looks vaguely like MII hardware,
411 1.1 pk * but not enough to be able to use the MII device
412 1.1 pk * layer. Hence, we have to take care of media selection
413 1.1 pk * ourselves.
414 1.1 pk */
415 1.1 pk
416 1.12 pk sc->sc_mii_inst = instance;
417 1.11 pk sc->sc_phys[instance] = BE_PHY_INTERNAL;
418 1.11 pk
419 1.1 pk /* Use `ifm_data' to store BMCR bits */
420 1.1 pk ifmedia_add(&sc->sc_media,
421 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance),
422 1.1 pk 0, NULL);
423 1.1 pk ifmedia_add(&sc->sc_media,
424 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance),
425 1.1 pk BMCR_S100, NULL);
426 1.1 pk ifmedia_add(&sc->sc_media,
427 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance),
428 1.1 pk 0, NULL);
429 1.11 pk
430 1.13 pk printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n",
431 1.13 pk self->dv_xname);
432 1.13 pk
433 1.12 pk be_mii_reset(sc, BE_PHY_INTERNAL);
434 1.11 pk /* Only set default medium here if there's no external PHY */
435 1.11 pk if (instance == 0) {
436 1.11 pk be_pal_gate(sc, BE_PHY_INTERNAL);
437 1.11 pk ifmedia_set(&sc->sc_media,
438 1.11 pk IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance));
439 1.12 pk } else
440 1.12 pk be_mii_writereg((void *)sc,
441 1.12 pk BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO);
442 1.1 pk }
443 1.1 pk
444 1.1 pk bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
445 1.1 pk ifp->if_softc = sc;
446 1.1 pk ifp->if_start = bestart;
447 1.1 pk ifp->if_ioctl = beioctl;
448 1.1 pk ifp->if_watchdog = bewatchdog;
449 1.1 pk ifp->if_flags =
450 1.1 pk IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
451 1.1 pk
452 1.1 pk /* Attach the interface. */
453 1.1 pk if_attach(ifp);
454 1.1 pk ether_ifattach(ifp, sc->sc_enaddr);
455 1.1 pk
456 1.1 pk #if NBPFILTER > 0
457 1.11 pk bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
458 1.1 pk #endif
459 1.1 pk }
460 1.1 pk
461 1.1 pk
462 1.1 pk /*
463 1.1 pk * Routine to copy from mbuf chain to transmit buffer in
464 1.1 pk * network buffer memory.
465 1.1 pk */
466 1.1 pk static __inline__ int
467 1.1 pk be_put(sc, idx, m)
468 1.1 pk struct be_softc *sc;
469 1.1 pk int idx;
470 1.1 pk struct mbuf *m;
471 1.1 pk {
472 1.1 pk struct mbuf *n;
473 1.1 pk int len, tlen = 0, boff = 0;
474 1.2 pk caddr_t bp;
475 1.2 pk
476 1.2 pk bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ;
477 1.1 pk
478 1.1 pk for (; m; m = n) {
479 1.1 pk len = m->m_len;
480 1.1 pk if (len == 0) {
481 1.1 pk MFREE(m, n);
482 1.1 pk continue;
483 1.1 pk }
484 1.1 pk bcopy(mtod(m, caddr_t), bp+boff, len);
485 1.1 pk boff += len;
486 1.1 pk tlen += len;
487 1.1 pk MFREE(m, n);
488 1.1 pk }
489 1.1 pk return (tlen);
490 1.1 pk }
491 1.1 pk
492 1.1 pk /*
493 1.1 pk * Pull data off an interface.
494 1.1 pk * Len is the length of data, with local net header stripped.
495 1.1 pk * We copy the data into mbufs. When full cluster sized units are present,
496 1.1 pk * we copy into clusters.
497 1.1 pk */
498 1.1 pk static __inline__ struct mbuf *
499 1.1 pk be_get(sc, idx, totlen)
500 1.1 pk struct be_softc *sc;
501 1.1 pk int idx, totlen;
502 1.1 pk {
503 1.1 pk struct ifnet *ifp = &sc->sc_ethercom.ec_if;
504 1.1 pk struct mbuf *m;
505 1.1 pk struct mbuf *top, **mp;
506 1.1 pk int len, pad, boff = 0;
507 1.2 pk caddr_t bp;
508 1.2 pk
509 1.2 pk bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ;
510 1.1 pk
511 1.1 pk MGETHDR(m, M_DONTWAIT, MT_DATA);
512 1.1 pk if (m == NULL)
513 1.1 pk return (NULL);
514 1.1 pk m->m_pkthdr.rcvif = ifp;
515 1.1 pk m->m_pkthdr.len = totlen;
516 1.1 pk
517 1.1 pk pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
518 1.1 pk m->m_data += pad;
519 1.1 pk len = MHLEN - pad;
520 1.1 pk top = NULL;
521 1.1 pk mp = ⊤
522 1.1 pk
523 1.1 pk while (totlen > 0) {
524 1.1 pk if (top) {
525 1.1 pk MGET(m, M_DONTWAIT, MT_DATA);
526 1.1 pk if (m == NULL) {
527 1.1 pk m_freem(top);
528 1.1 pk return (NULL);
529 1.1 pk }
530 1.1 pk len = MLEN;
531 1.1 pk }
532 1.1 pk if (top && totlen >= MINCLSIZE) {
533 1.1 pk MCLGET(m, M_DONTWAIT);
534 1.1 pk if (m->m_flags & M_EXT)
535 1.1 pk len = MCLBYTES;
536 1.1 pk }
537 1.1 pk m->m_len = len = min(totlen, len);
538 1.1 pk bcopy(bp + boff, mtod(m, caddr_t), len);
539 1.1 pk boff += len;
540 1.1 pk totlen -= len;
541 1.1 pk *mp = m;
542 1.1 pk mp = &m->m_next;
543 1.1 pk }
544 1.1 pk
545 1.1 pk return (top);
546 1.1 pk }
547 1.1 pk
548 1.1 pk /*
549 1.1 pk * Pass a packet to the higher levels.
550 1.1 pk */
551 1.1 pk static __inline__ void
552 1.1 pk be_read(sc, idx, len)
553 1.1 pk struct be_softc *sc;
554 1.1 pk int idx, len;
555 1.1 pk {
556 1.1 pk struct ifnet *ifp = &sc->sc_ethercom.ec_if;
557 1.1 pk struct mbuf *m;
558 1.1 pk
559 1.1 pk if (len <= sizeof(struct ether_header) ||
560 1.1 pk len > ETHERMTU + sizeof(struct ether_header)) {
561 1.1 pk
562 1.1 pk printf("%s: invalid packet size %d; dropping\n",
563 1.1 pk ifp->if_xname, len);
564 1.1 pk
565 1.1 pk ifp->if_ierrors++;
566 1.1 pk return;
567 1.1 pk }
568 1.1 pk
569 1.1 pk /*
570 1.1 pk * Pull packet off interface.
571 1.1 pk */
572 1.1 pk m = be_get(sc, idx, len);
573 1.1 pk if (m == NULL) {
574 1.1 pk ifp->if_ierrors++;
575 1.1 pk return;
576 1.1 pk }
577 1.1 pk ifp->if_ipackets++;
578 1.1 pk
579 1.1 pk #if NBPFILTER > 0
580 1.1 pk /*
581 1.1 pk * Check if there's a BPF listener on this interface.
582 1.1 pk * If so, hand off the raw packet to BPF.
583 1.1 pk */
584 1.1 pk if (ifp->if_bpf)
585 1.1 pk bpf_mtap(ifp->if_bpf, m);
586 1.1 pk #endif
587 1.6 thorpej /* Pass the packet up. */
588 1.6 thorpej (*ifp->if_input)(ifp, m);
589 1.1 pk }
590 1.1 pk
591 1.1 pk /*
592 1.1 pk * Start output on interface.
593 1.1 pk * We make two assumptions here:
594 1.1 pk * 1) that the current priority is set to splnet _before_ this code
595 1.1 pk * is called *and* is returned to the appropriate priority after
596 1.1 pk * return
597 1.1 pk * 2) that the IFF_OACTIVE flag is checked before this code is called
598 1.1 pk * (i.e. that the output part of the interface is idle)
599 1.1 pk */
600 1.1 pk void
601 1.1 pk bestart(ifp)
602 1.1 pk struct ifnet *ifp;
603 1.1 pk {
604 1.1 pk struct be_softc *sc = (struct be_softc *)ifp->if_softc;
605 1.2 pk struct qec_xd *txd = sc->sc_rb.rb_txd;
606 1.1 pk struct mbuf *m;
607 1.1 pk unsigned int bix, len;
608 1.2 pk unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
609 1.1 pk
610 1.1 pk if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
611 1.1 pk return;
612 1.1 pk
613 1.2 pk bix = sc->sc_rb.rb_tdhead;
614 1.1 pk
615 1.1 pk for (;;) {
616 1.1 pk IF_DEQUEUE(&ifp->if_snd, m);
617 1.1 pk if (m == 0)
618 1.1 pk break;
619 1.1 pk
620 1.1 pk #if NBPFILTER > 0
621 1.1 pk /*
622 1.1 pk * If BPF is listening on this interface, let it see the
623 1.1 pk * packet before we commit it to the wire.
624 1.1 pk */
625 1.1 pk if (ifp->if_bpf)
626 1.1 pk bpf_mtap(ifp->if_bpf, m);
627 1.1 pk #endif
628 1.1 pk
629 1.1 pk /*
630 1.1 pk * Copy the mbuf chain into the transmit buffer.
631 1.1 pk */
632 1.1 pk len = be_put(sc, bix, m);
633 1.1 pk
634 1.1 pk /*
635 1.1 pk * Initialize transmit registers and start transmission
636 1.1 pk */
637 1.1 pk txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
638 1.1 pk (len & QEC_XD_LENGTH);
639 1.1 pk bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL,
640 1.1 pk BE_CR_CTRL_TWAKEUP);
641 1.1 pk
642 1.1 pk if (++bix == QEC_XD_RING_MAXSIZE)
643 1.1 pk bix = 0;
644 1.1 pk
645 1.2 pk if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
646 1.1 pk ifp->if_flags |= IFF_OACTIVE;
647 1.1 pk break;
648 1.1 pk }
649 1.1 pk }
650 1.1 pk
651 1.2 pk sc->sc_rb.rb_tdhead = bix;
652 1.1 pk }
653 1.1 pk
654 1.1 pk void
655 1.1 pk bestop(sc)
656 1.1 pk struct be_softc *sc;
657 1.1 pk {
658 1.1 pk int n;
659 1.1 pk bus_space_tag_t t = sc->sc_bustag;
660 1.1 pk bus_space_handle_t br = sc->sc_br;
661 1.1 pk
662 1.17 thorpej callout_stop(&sc->sc_tick_ch);
663 1.8 thorpej
664 1.12 pk /* Down the MII. */
665 1.12 pk mii_down(&sc->sc_mii);
666 1.12 pk (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN);
667 1.1 pk
668 1.1 pk /* Stop the transmitter */
669 1.1 pk bus_space_write_4(t, br, BE_BRI_TXCFG, 0);
670 1.1 pk for (n = 32; n > 0; n--) {
671 1.1 pk if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0)
672 1.1 pk break;
673 1.1 pk DELAY(20);
674 1.1 pk }
675 1.1 pk
676 1.1 pk /* Stop the receiver */
677 1.1 pk bus_space_write_4(t, br, BE_BRI_RXCFG, 0);
678 1.1 pk for (n = 32; n > 0; n--) {
679 1.1 pk if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0)
680 1.1 pk break;
681 1.1 pk DELAY(20);
682 1.1 pk }
683 1.1 pk }
684 1.1 pk
685 1.1 pk /*
686 1.1 pk * Reset interface.
687 1.1 pk */
688 1.1 pk void
689 1.1 pk bereset(sc)
690 1.1 pk struct be_softc *sc;
691 1.1 pk {
692 1.1 pk int s;
693 1.1 pk
694 1.1 pk s = splnet();
695 1.1 pk bestop(sc);
696 1.13 pk if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0)
697 1.13 pk beinit(sc);
698 1.1 pk splx(s);
699 1.1 pk }
700 1.1 pk
701 1.1 pk void
702 1.1 pk bewatchdog(ifp)
703 1.1 pk struct ifnet *ifp;
704 1.1 pk {
705 1.1 pk struct be_softc *sc = ifp->if_softc;
706 1.1 pk
707 1.1 pk log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
708 1.1 pk ++sc->sc_ethercom.ec_if.if_oerrors;
709 1.1 pk
710 1.1 pk bereset(sc);
711 1.1 pk }
712 1.1 pk
713 1.1 pk int
714 1.1 pk beintr(v)
715 1.1 pk void *v;
716 1.1 pk {
717 1.1 pk struct be_softc *sc = (struct be_softc *)v;
718 1.1 pk bus_space_tag_t t = sc->sc_bustag;
719 1.1 pk u_int32_t whyq, whyb, whyc;
720 1.1 pk int r = 0;
721 1.1 pk
722 1.1 pk /* Read QEC status, channel status and BE status */
723 1.1 pk whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
724 1.1 pk whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT);
725 1.1 pk whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT);
726 1.1 pk
727 1.1 pk if (whyq & QEC_STAT_BM)
728 1.1 pk r |= beeint(sc, whyb);
729 1.1 pk
730 1.1 pk if (whyq & QEC_STAT_ER)
731 1.1 pk r |= beqint(sc, whyc);
732 1.1 pk
733 1.1 pk if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ)
734 1.1 pk r |= betint(sc);
735 1.1 pk
736 1.1 pk if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ)
737 1.1 pk r |= berint(sc);
738 1.1 pk
739 1.1 pk return (r);
740 1.1 pk }
741 1.1 pk
742 1.1 pk /*
743 1.1 pk * QEC Interrupt.
744 1.1 pk */
745 1.1 pk int
746 1.1 pk beqint(sc, why)
747 1.1 pk struct be_softc *sc;
748 1.1 pk u_int32_t why;
749 1.1 pk {
750 1.1 pk int r = 0, rst = 0;
751 1.1 pk
752 1.1 pk if (why & BE_CR_STAT_TXIRQ)
753 1.1 pk r |= 1;
754 1.1 pk if (why & BE_CR_STAT_RXIRQ)
755 1.1 pk r |= 1;
756 1.1 pk
757 1.1 pk if (why & BE_CR_STAT_BERROR) {
758 1.1 pk r |= 1;
759 1.1 pk rst = 1;
760 1.1 pk printf("%s: bigmac error\n", sc->sc_dev.dv_xname);
761 1.1 pk }
762 1.1 pk
763 1.1 pk if (why & BE_CR_STAT_TXDERR) {
764 1.1 pk r |= 1;
765 1.1 pk rst = 1;
766 1.1 pk printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname);
767 1.1 pk }
768 1.1 pk
769 1.1 pk if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) {
770 1.1 pk r |= 1;
771 1.1 pk rst = 1;
772 1.1 pk printf("%s: tx dma error ( ", sc->sc_dev.dv_xname);
773 1.1 pk if (why & BE_CR_STAT_TXLERR)
774 1.1 pk printf("Late ");
775 1.1 pk if (why & BE_CR_STAT_TXPERR)
776 1.1 pk printf("Parity ");
777 1.1 pk if (why & BE_CR_STAT_TXSERR)
778 1.1 pk printf("Generic ");
779 1.1 pk printf(")\n");
780 1.1 pk }
781 1.1 pk
782 1.1 pk if (why & BE_CR_STAT_RXDROP) {
783 1.1 pk r |= 1;
784 1.1 pk rst = 1;
785 1.1 pk printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname);
786 1.1 pk }
787 1.1 pk
788 1.1 pk if (why & BE_CR_STAT_RXSMALL) {
789 1.1 pk r |= 1;
790 1.1 pk rst = 1;
791 1.1 pk printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname);
792 1.1 pk }
793 1.1 pk
794 1.1 pk if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) {
795 1.1 pk r |= 1;
796 1.1 pk rst = 1;
797 1.1 pk printf("%s: rx dma error ( ", sc->sc_dev.dv_xname);
798 1.1 pk if (why & BE_CR_STAT_RXLERR)
799 1.1 pk printf("Late ");
800 1.1 pk if (why & BE_CR_STAT_RXPERR)
801 1.1 pk printf("Parity ");
802 1.1 pk if (why & BE_CR_STAT_RXSERR)
803 1.1 pk printf("Generic ");
804 1.1 pk printf(")\n");
805 1.1 pk }
806 1.1 pk
807 1.1 pk if (!r) {
808 1.1 pk rst = 1;
809 1.1 pk printf("%s: unexpected error interrupt %08x\n",
810 1.1 pk sc->sc_dev.dv_xname, why);
811 1.1 pk }
812 1.1 pk
813 1.1 pk if (rst) {
814 1.1 pk printf("%s: resetting\n", sc->sc_dev.dv_xname);
815 1.1 pk bereset(sc);
816 1.1 pk }
817 1.1 pk
818 1.1 pk return (r);
819 1.1 pk }
820 1.1 pk
821 1.1 pk /*
822 1.1 pk * Error interrupt.
823 1.1 pk */
824 1.1 pk int
825 1.1 pk beeint(sc, why)
826 1.1 pk struct be_softc *sc;
827 1.1 pk u_int32_t why;
828 1.1 pk {
829 1.1 pk int r = 0, rst = 0;
830 1.1 pk
831 1.1 pk if (why & BE_BR_STAT_RFIFOVF) {
832 1.1 pk r |= 1;
833 1.1 pk rst = 1;
834 1.1 pk printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname);
835 1.1 pk }
836 1.1 pk if (why & BE_BR_STAT_TFIFO_UND) {
837 1.1 pk r |= 1;
838 1.1 pk rst = 1;
839 1.1 pk printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname);
840 1.1 pk }
841 1.1 pk if (why & BE_BR_STAT_MAXPKTERR) {
842 1.1 pk r |= 1;
843 1.1 pk rst = 1;
844 1.1 pk printf("%s: max packet size error\n", sc->sc_dev.dv_xname);
845 1.1 pk }
846 1.1 pk
847 1.1 pk if (!r) {
848 1.1 pk rst = 1;
849 1.1 pk printf("%s: unexpected error interrupt %08x\n",
850 1.1 pk sc->sc_dev.dv_xname, why);
851 1.1 pk }
852 1.1 pk
853 1.1 pk if (rst) {
854 1.1 pk printf("%s: resetting\n", sc->sc_dev.dv_xname);
855 1.1 pk bereset(sc);
856 1.1 pk }
857 1.1 pk
858 1.1 pk return (r);
859 1.1 pk }
860 1.1 pk
861 1.1 pk /*
862 1.1 pk * Transmit interrupt.
863 1.1 pk */
864 1.1 pk int
865 1.1 pk betint(sc)
866 1.1 pk struct be_softc *sc;
867 1.1 pk {
868 1.1 pk struct ifnet *ifp = &sc->sc_ethercom.ec_if;
869 1.1 pk bus_space_tag_t t = sc->sc_bustag;
870 1.1 pk bus_space_handle_t br = sc->sc_br;
871 1.1 pk unsigned int bix, txflags;
872 1.1 pk
873 1.1 pk /*
874 1.1 pk * Unload collision counters
875 1.1 pk */
876 1.1 pk ifp->if_collisions +=
877 1.1 pk bus_space_read_4(t, br, BE_BRI_NCCNT) +
878 1.1 pk bus_space_read_4(t, br, BE_BRI_FCCNT) +
879 1.1 pk bus_space_read_4(t, br, BE_BRI_EXCNT) +
880 1.1 pk bus_space_read_4(t, br, BE_BRI_LTCNT);
881 1.1 pk
882 1.1 pk /*
883 1.1 pk * the clear the hardware counters
884 1.1 pk */
885 1.1 pk bus_space_write_4(t, br, BE_BRI_NCCNT, 0);
886 1.1 pk bus_space_write_4(t, br, BE_BRI_FCCNT, 0);
887 1.1 pk bus_space_write_4(t, br, BE_BRI_EXCNT, 0);
888 1.1 pk bus_space_write_4(t, br, BE_BRI_LTCNT, 0);
889 1.1 pk
890 1.2 pk bix = sc->sc_rb.rb_tdtail;
891 1.1 pk
892 1.1 pk for (;;) {
893 1.2 pk if (sc->sc_rb.rb_td_nbusy <= 0)
894 1.1 pk break;
895 1.1 pk
896 1.2 pk txflags = sc->sc_rb.rb_txd[bix].xd_flags;
897 1.1 pk
898 1.1 pk if (txflags & QEC_XD_OWN)
899 1.1 pk break;
900 1.1 pk
901 1.1 pk ifp->if_flags &= ~IFF_OACTIVE;
902 1.1 pk ifp->if_opackets++;
903 1.1 pk
904 1.1 pk if (++bix == QEC_XD_RING_MAXSIZE)
905 1.1 pk bix = 0;
906 1.1 pk
907 1.2 pk --sc->sc_rb.rb_td_nbusy;
908 1.1 pk }
909 1.1 pk
910 1.2 pk sc->sc_rb.rb_tdtail = bix;
911 1.1 pk
912 1.1 pk bestart(ifp);
913 1.1 pk
914 1.2 pk if (sc->sc_rb.rb_td_nbusy == 0)
915 1.1 pk ifp->if_timer = 0;
916 1.1 pk
917 1.1 pk return (1);
918 1.1 pk }
919 1.1 pk
920 1.1 pk /*
921 1.1 pk * Receive interrupt.
922 1.1 pk */
923 1.1 pk int
924 1.1 pk berint(sc)
925 1.1 pk struct be_softc *sc;
926 1.1 pk {
927 1.2 pk struct qec_xd *xd = sc->sc_rb.rb_rxd;
928 1.1 pk unsigned int bix, len;
929 1.2 pk unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
930 1.1 pk
931 1.2 pk bix = sc->sc_rb.rb_rdtail;
932 1.1 pk
933 1.1 pk /*
934 1.1 pk * Process all buffers with valid data.
935 1.1 pk */
936 1.1 pk for (;;) {
937 1.1 pk len = xd[bix].xd_flags;
938 1.1 pk if (len & QEC_XD_OWN)
939 1.1 pk break;
940 1.1 pk
941 1.1 pk len &= QEC_XD_LENGTH;
942 1.1 pk be_read(sc, bix, len);
943 1.1 pk
944 1.1 pk /* ... */
945 1.1 pk xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
946 1.1 pk QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH);
947 1.1 pk
948 1.1 pk if (++bix == QEC_XD_RING_MAXSIZE)
949 1.1 pk bix = 0;
950 1.1 pk }
951 1.1 pk
952 1.2 pk sc->sc_rb.rb_rdtail = bix;
953 1.1 pk
954 1.1 pk return (1);
955 1.1 pk }
956 1.1 pk
957 1.1 pk int
958 1.1 pk beioctl(ifp, cmd, data)
959 1.1 pk struct ifnet *ifp;
960 1.1 pk u_long cmd;
961 1.1 pk caddr_t data;
962 1.1 pk {
963 1.1 pk struct be_softc *sc = ifp->if_softc;
964 1.1 pk struct ifaddr *ifa = (struct ifaddr *)data;
965 1.1 pk struct ifreq *ifr = (struct ifreq *)data;
966 1.1 pk int s, error = 0;
967 1.1 pk
968 1.1 pk s = splnet();
969 1.1 pk
970 1.1 pk switch (cmd) {
971 1.1 pk case SIOCSIFADDR:
972 1.1 pk ifp->if_flags |= IFF_UP;
973 1.1 pk switch (ifa->ifa_addr->sa_family) {
974 1.1 pk #ifdef INET
975 1.1 pk case AF_INET:
976 1.1 pk beinit(sc);
977 1.1 pk arp_ifinit(ifp, ifa);
978 1.1 pk break;
979 1.1 pk #endif /* INET */
980 1.1 pk #ifdef NS
981 1.1 pk case AF_NS:
982 1.1 pk {
983 1.1 pk struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
984 1.1 pk
985 1.1 pk if (ns_nullhost(*ina))
986 1.3 pk ina->x_host =
987 1.3 pk *(union ns_host *)LLADDR(ifp->if_sadl);
988 1.1 pk else
989 1.3 pk bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
990 1.3 pk sizeof(sc->sc_enaddr));
991 1.1 pk /* Set new address. */
992 1.1 pk beinit(sc);
993 1.1 pk break;
994 1.1 pk }
995 1.1 pk #endif /* NS */
996 1.1 pk default:
997 1.1 pk beinit(sc);
998 1.1 pk break;
999 1.1 pk }
1000 1.1 pk break;
1001 1.1 pk
1002 1.1 pk case SIOCSIFFLAGS:
1003 1.1 pk if ((ifp->if_flags & IFF_UP) == 0 &&
1004 1.1 pk (ifp->if_flags & IFF_RUNNING) != 0) {
1005 1.1 pk /*
1006 1.1 pk * If interface is marked down and it is running, then
1007 1.1 pk * stop it.
1008 1.1 pk */
1009 1.1 pk bestop(sc);
1010 1.1 pk ifp->if_flags &= ~IFF_RUNNING;
1011 1.1 pk } else if ((ifp->if_flags & IFF_UP) != 0 &&
1012 1.1 pk (ifp->if_flags & IFF_RUNNING) == 0) {
1013 1.1 pk /*
1014 1.1 pk * If interface is marked up and it is stopped, then
1015 1.1 pk * start it.
1016 1.1 pk */
1017 1.1 pk beinit(sc);
1018 1.1 pk } else {
1019 1.1 pk /*
1020 1.1 pk * Reset the interface to pick up changes in any other
1021 1.1 pk * flags that affect hardware registers.
1022 1.1 pk */
1023 1.1 pk bestop(sc);
1024 1.1 pk beinit(sc);
1025 1.1 pk }
1026 1.1 pk #ifdef BEDEBUG
1027 1.1 pk if (ifp->if_flags & IFF_DEBUG)
1028 1.2 pk sc->sc_debug = 1;
1029 1.1 pk else
1030 1.1 pk sc->sc_debug = 0;
1031 1.1 pk #endif
1032 1.1 pk break;
1033 1.1 pk
1034 1.1 pk case SIOCADDMULTI:
1035 1.1 pk case SIOCDELMULTI:
1036 1.1 pk error = (cmd == SIOCADDMULTI) ?
1037 1.1 pk ether_addmulti(ifr, &sc->sc_ethercom):
1038 1.1 pk ether_delmulti(ifr, &sc->sc_ethercom);
1039 1.1 pk
1040 1.1 pk if (error == ENETRESET) {
1041 1.1 pk /*
1042 1.1 pk * Multicast list has changed; set the hardware filter
1043 1.1 pk * accordingly.
1044 1.1 pk */
1045 1.1 pk be_mcreset(sc);
1046 1.1 pk error = 0;
1047 1.1 pk }
1048 1.1 pk break;
1049 1.1 pk case SIOCGIFMEDIA:
1050 1.1 pk case SIOCSIFMEDIA:
1051 1.1 pk error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
1052 1.1 pk break;
1053 1.1 pk default:
1054 1.1 pk error = EINVAL;
1055 1.1 pk break;
1056 1.1 pk }
1057 1.1 pk splx(s);
1058 1.1 pk return (error);
1059 1.1 pk }
1060 1.1 pk
1061 1.1 pk
1062 1.1 pk void
1063 1.1 pk beinit(sc)
1064 1.1 pk struct be_softc *sc;
1065 1.1 pk {
1066 1.2 pk struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1067 1.1 pk bus_space_tag_t t = sc->sc_bustag;
1068 1.1 pk bus_space_handle_t br = sc->sc_br;
1069 1.1 pk bus_space_handle_t cr = sc->sc_cr;
1070 1.1 pk struct qec_softc *qec = sc->sc_qec;
1071 1.16 pk u_int32_t v;
1072 1.1 pk u_int32_t qecaddr;
1073 1.1 pk u_int8_t *ea;
1074 1.1 pk int s;
1075 1.1 pk
1076 1.1 pk s = splimp();
1077 1.1 pk
1078 1.2 pk qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
1079 1.1 pk
1080 1.1 pk bestop(sc);
1081 1.1 pk
1082 1.1 pk ea = sc->sc_enaddr;
1083 1.1 pk bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
1084 1.1 pk bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
1085 1.1 pk bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
1086 1.1 pk
1087 1.16 pk /* Clear hash table */
1088 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
1089 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
1090 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
1091 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
1092 1.1 pk
1093 1.16 pk /* Re-initialize RX configuration */
1094 1.16 pk v = BE_BR_RXCFG_FIFO;
1095 1.16 pk bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1096 1.16 pk
1097 1.5 pk be_mcreset(sc);
1098 1.1 pk
1099 1.1 pk bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
1100 1.1 pk
1101 1.1 pk bus_space_write_4(t, br, BE_BRI_XIFCFG,
1102 1.1 pk BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
1103 1.1 pk
1104 1.1 pk bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
1105 1.1 pk
1106 1.1 pk /*
1107 1.1 pk * Turn off counter expiration interrupts as well as
1108 1.1 pk * 'gotframe' and 'sentframe'
1109 1.1 pk */
1110 1.1 pk bus_space_write_4(t, br, BE_BRI_IMASK,
1111 1.1 pk BE_BR_IMASK_GOTFRAME |
1112 1.1 pk BE_BR_IMASK_RCNTEXP |
1113 1.1 pk BE_BR_IMASK_ACNTEXP |
1114 1.1 pk BE_BR_IMASK_CCNTEXP |
1115 1.1 pk BE_BR_IMASK_LCNTEXP |
1116 1.1 pk BE_BR_IMASK_CVCNTEXP |
1117 1.1 pk BE_BR_IMASK_SENTFRAME |
1118 1.1 pk BE_BR_IMASK_NCNTEXP |
1119 1.1 pk BE_BR_IMASK_ECNTEXP |
1120 1.1 pk BE_BR_IMASK_LCCNTEXP |
1121 1.1 pk BE_BR_IMASK_FCNTEXP |
1122 1.1 pk BE_BR_IMASK_DTIMEXP);
1123 1.1 pk
1124 1.1 pk /* Channel registers: */
1125 1.2 pk bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
1126 1.2 pk bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
1127 1.1 pk
1128 1.1 pk qecaddr = sc->sc_channel * qec->sc_msize;
1129 1.1 pk bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
1130 1.1 pk bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
1131 1.1 pk bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
1132 1.1 pk bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
1133 1.1 pk
1134 1.1 pk bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
1135 1.1 pk bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
1136 1.1 pk bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
1137 1.1 pk bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
1138 1.1 pk bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
1139 1.1 pk
1140 1.1 pk /* Enable transmitter */
1141 1.1 pk bus_space_write_4(t, br, BE_BRI_TXCFG,
1142 1.1 pk BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
1143 1.1 pk
1144 1.1 pk /* Enable receiver */
1145 1.16 pk v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1146 1.16 pk v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE;
1147 1.16 pk bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1148 1.1 pk
1149 1.1 pk ifp->if_flags |= IFF_RUNNING;
1150 1.1 pk ifp->if_flags &= ~IFF_OACTIVE;
1151 1.1 pk
1152 1.13 pk be_ifmedia_upd(ifp);
1153 1.17 thorpej callout_reset(&sc->sc_tick_ch, hz, be_tick, sc);
1154 1.1 pk splx(s);
1155 1.1 pk }
1156 1.1 pk
1157 1.1 pk void
1158 1.1 pk be_mcreset(sc)
1159 1.1 pk struct be_softc *sc;
1160 1.1 pk {
1161 1.2 pk struct ethercom *ec = &sc->sc_ethercom;
1162 1.1 pk struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1163 1.1 pk bus_space_tag_t t = sc->sc_bustag;
1164 1.1 pk bus_space_handle_t br = sc->sc_br;
1165 1.1 pk u_int32_t crc;
1166 1.1 pk u_int16_t hash[4];
1167 1.1 pk u_int8_t octet;
1168 1.5 pk u_int32_t v;
1169 1.1 pk int i, j;
1170 1.1 pk struct ether_multi *enm;
1171 1.1 pk struct ether_multistep step;
1172 1.1 pk
1173 1.5 pk if (ifp->if_flags & IFF_PROMISC) {
1174 1.5 pk v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1175 1.5 pk v |= BE_BR_RXCFG_PMISC;
1176 1.5 pk bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1177 1.5 pk return;
1178 1.5 pk }
1179 1.5 pk
1180 1.1 pk if (ifp->if_flags & IFF_ALLMULTI) {
1181 1.16 pk hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1182 1.16 pk goto chipit;
1183 1.1 pk }
1184 1.1 pk
1185 1.1 pk hash[3] = hash[2] = hash[1] = hash[0] = 0;
1186 1.1 pk
1187 1.2 pk ETHER_FIRST_MULTI(step, ec, enm);
1188 1.1 pk while (enm != NULL) {
1189 1.1 pk if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1190 1.1 pk /*
1191 1.1 pk * We must listen to a range of multicast
1192 1.1 pk * addresses. For now, just accept all
1193 1.1 pk * multicasts, rather than trying to set only
1194 1.1 pk * those filter bits needed to match the range.
1195 1.1 pk * (At this time, the only use of address
1196 1.1 pk * ranges is for IP multicast routing, for
1197 1.1 pk * which the range is big enough to require
1198 1.1 pk * all bits set.)
1199 1.1 pk */
1200 1.16 pk hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1201 1.1 pk ifp->if_flags |= IFF_ALLMULTI;
1202 1.16 pk goto chipit;
1203 1.1 pk }
1204 1.1 pk
1205 1.1 pk crc = 0xffffffff;
1206 1.1 pk
1207 1.1 pk for (i = 0; i < ETHER_ADDR_LEN; i++) {
1208 1.1 pk octet = enm->enm_addrlo[i];
1209 1.1 pk
1210 1.1 pk for (j = 0; j < 8; j++) {
1211 1.1 pk if ((crc & 1) ^ (octet & 1)) {
1212 1.1 pk crc >>= 1;
1213 1.1 pk crc ^= MC_POLY_LE;
1214 1.1 pk }
1215 1.1 pk else
1216 1.1 pk crc >>= 1;
1217 1.1 pk octet >>= 1;
1218 1.1 pk }
1219 1.1 pk }
1220 1.1 pk
1221 1.1 pk crc >>= 26;
1222 1.1 pk hash[crc >> 4] |= 1 << (crc & 0xf);
1223 1.1 pk ETHER_NEXT_MULTI(step, enm);
1224 1.1 pk }
1225 1.1 pk
1226 1.16 pk ifp->if_flags &= ~IFF_ALLMULTI;
1227 1.16 pk
1228 1.16 pk chipit:
1229 1.16 pk /* Enable the hash filter */
1230 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]);
1231 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]);
1232 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]);
1233 1.1 pk bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]);
1234 1.16 pk
1235 1.16 pk v = bus_space_read_4(t, br, BE_BRI_RXCFG);
1236 1.16 pk v &= ~BE_BR_RXCFG_PMISC;
1237 1.16 pk v |= BE_BR_RXCFG_HENABLE;
1238 1.16 pk bus_space_write_4(t, br, BE_BRI_RXCFG, v);
1239 1.1 pk }
1240 1.1 pk
1241 1.1 pk /*
1242 1.1 pk * Set the tcvr to an idle state
1243 1.1 pk */
1244 1.1 pk void
1245 1.1 pk be_mii_sync(sc)
1246 1.1 pk struct be_softc *sc;
1247 1.1 pk {
1248 1.1 pk bus_space_tag_t t = sc->sc_bustag;
1249 1.1 pk bus_space_handle_t tr = sc->sc_tr;
1250 1.10 pk int n = 32;
1251 1.1 pk
1252 1.1 pk while (n--) {
1253 1.1 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1254 1.1 pk MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
1255 1.1 pk MGMT_PAL_OENAB);
1256 1.1 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1257 1.1 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1258 1.1 pk MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
1259 1.1 pk MGMT_PAL_OENAB | MGMT_PAL_DCLOCK);
1260 1.1 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1261 1.1 pk }
1262 1.1 pk }
1263 1.1 pk
1264 1.11 pk void
1265 1.11 pk be_pal_gate(sc, phy)
1266 1.11 pk struct be_softc *sc;
1267 1.11 pk int phy;
1268 1.11 pk {
1269 1.11 pk bus_space_tag_t t = sc->sc_bustag;
1270 1.11 pk bus_space_handle_t tr = sc->sc_tr;
1271 1.11 pk u_int32_t v;
1272 1.11 pk
1273 1.11 pk be_mii_sync(sc);
1274 1.11 pk
1275 1.11 pk v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE);
1276 1.11 pk if (phy == BE_PHY_INTERNAL)
1277 1.11 pk v &= ~TCVR_PAL_SERIAL;
1278 1.11 pk
1279 1.11 pk bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v);
1280 1.11 pk (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
1281 1.11 pk }
1282 1.11 pk
1283 1.10 pk static int
1284 1.1 pk be_tcvr_read_bit(sc, phy)
1285 1.1 pk struct be_softc *sc;
1286 1.1 pk int phy;
1287 1.1 pk {
1288 1.1 pk bus_space_tag_t t = sc->sc_bustag;
1289 1.1 pk bus_space_handle_t tr = sc->sc_tr;
1290 1.1 pk int ret;
1291 1.1 pk
1292 1.1 pk if (phy == BE_PHY_INTERNAL) {
1293 1.1 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO);
1294 1.1 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1295 1.1 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1296 1.1 pk MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK);
1297 1.1 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1298 1.1 pk ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
1299 1.10 pk MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT;
1300 1.1 pk } else {
1301 1.1 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO);
1302 1.1 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1303 1.1 pk ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
1304 1.10 pk MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT;
1305 1.1 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
1306 1.1 pk MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK);
1307 1.1 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1308 1.1 pk }
1309 1.1 pk
1310 1.1 pk return (ret);
1311 1.1 pk }
1312 1.1 pk
1313 1.10 pk static void
1314 1.1 pk be_tcvr_write_bit(sc, phy, bit)
1315 1.1 pk struct be_softc *sc;
1316 1.1 pk int phy;
1317 1.1 pk int bit;
1318 1.1 pk {
1319 1.1 pk bus_space_tag_t t = sc->sc_bustag;
1320 1.1 pk bus_space_handle_t tr = sc->sc_tr;
1321 1.10 pk u_int32_t v;
1322 1.1 pk
1323 1.1 pk if (phy == BE_PHY_INTERNAL) {
1324 1.10 pk v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) |
1325 1.10 pk MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO;
1326 1.1 pk } else {
1327 1.10 pk v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT)
1328 1.10 pk | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO;
1329 1.1 pk }
1330 1.12 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v);
1331 1.12 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1332 1.12 pk bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK);
1333 1.12 pk (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
1334 1.1 pk }
1335 1.1 pk
1336 1.10 pk static void
1337 1.1 pk be_mii_sendbits(sc, phy, data, nbits)
1338 1.1 pk struct be_softc *sc;
1339 1.1 pk int phy;
1340 1.1 pk u_int32_t data;
1341 1.1 pk int nbits;
1342 1.1 pk {
1343 1.1 pk int i;
1344 1.1 pk
1345 1.1 pk for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
1346 1.1 pk be_tcvr_write_bit(sc, phy, (data & i) != 0);
1347 1.1 pk }
1348 1.1 pk }
1349 1.1 pk
1350 1.4 pk static int
1351 1.4 pk be_mii_readreg(self, phy, reg)
1352 1.1 pk struct device *self;
1353 1.1 pk int phy, reg;
1354 1.1 pk {
1355 1.1 pk struct be_softc *sc = (struct be_softc *)self;
1356 1.1 pk int val = 0, i;
1357 1.1 pk
1358 1.1 pk /*
1359 1.1 pk * Read the PHY register by manually driving the MII control lines.
1360 1.1 pk */
1361 1.1 pk be_mii_sync(sc);
1362 1.1 pk be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
1363 1.1 pk be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);
1364 1.1 pk be_mii_sendbits(sc, phy, phy, 5);
1365 1.1 pk be_mii_sendbits(sc, phy, reg, 5);
1366 1.1 pk
1367 1.1 pk (void) be_tcvr_read_bit(sc, phy);
1368 1.1 pk (void) be_tcvr_read_bit(sc, phy);
1369 1.1 pk
1370 1.1 pk for (i = 15; i >= 0; i--)
1371 1.1 pk val |= (be_tcvr_read_bit(sc, phy) << i);
1372 1.1 pk
1373 1.1 pk (void) be_tcvr_read_bit(sc, phy);
1374 1.1 pk (void) be_tcvr_read_bit(sc, phy);
1375 1.1 pk (void) be_tcvr_read_bit(sc, phy);
1376 1.1 pk
1377 1.1 pk return (val);
1378 1.1 pk }
1379 1.1 pk
1380 1.1 pk void
1381 1.1 pk be_mii_writereg(self, phy, reg, val)
1382 1.1 pk struct device *self;
1383 1.1 pk int phy, reg, val;
1384 1.1 pk {
1385 1.1 pk struct be_softc *sc = (struct be_softc *)self;
1386 1.1 pk int i;
1387 1.1 pk
1388 1.1 pk /*
1389 1.1 pk * Write the PHY register by manually driving the MII control lines.
1390 1.1 pk */
1391 1.1 pk be_mii_sync(sc);
1392 1.1 pk be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
1393 1.1 pk be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);
1394 1.1 pk be_mii_sendbits(sc, phy, phy, 5);
1395 1.1 pk be_mii_sendbits(sc, phy, reg, 5);
1396 1.1 pk
1397 1.1 pk be_tcvr_write_bit(sc, phy, 1);
1398 1.1 pk be_tcvr_write_bit(sc, phy, 0);
1399 1.1 pk
1400 1.1 pk for (i = 15; i >= 0; i--)
1401 1.1 pk be_tcvr_write_bit(sc, phy, (val >> i) & 1);
1402 1.1 pk }
1403 1.1 pk
1404 1.1 pk int
1405 1.1 pk be_mii_reset(sc, phy)
1406 1.1 pk struct be_softc *sc;
1407 1.1 pk int phy;
1408 1.1 pk {
1409 1.1 pk int n;
1410 1.1 pk
1411 1.1 pk be_mii_writereg((struct device *)sc, phy, MII_BMCR,
1412 1.1 pk BMCR_LOOP | BMCR_PDOWN | BMCR_ISO);
1413 1.1 pk be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);
1414 1.1 pk
1415 1.1 pk for (n = 16; n >= 0; n--) {
1416 1.1 pk int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
1417 1.1 pk if ((bmcr & BMCR_RESET) == 0)
1418 1.1 pk break;
1419 1.1 pk DELAY(20);
1420 1.1 pk }
1421 1.1 pk if (n == 0) {
1422 1.1 pk printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname);
1423 1.1 pk return (EIO);
1424 1.1 pk }
1425 1.13 pk
1426 1.1 pk return (0);
1427 1.1 pk }
1428 1.1 pk
1429 1.1 pk void
1430 1.12 pk be_tick(arg)
1431 1.12 pk void *arg;
1432 1.12 pk {
1433 1.12 pk struct be_softc *sc = arg;
1434 1.12 pk int s = splnet();
1435 1.12 pk
1436 1.12 pk mii_tick(&sc->sc_mii);
1437 1.12 pk (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK);
1438 1.12 pk
1439 1.12 pk splx(s);
1440 1.17 thorpej callout_reset(&sc->sc_tick_ch, hz, be_tick, sc);
1441 1.12 pk }
1442 1.12 pk
1443 1.12 pk void
1444 1.10 pk be_mii_statchg(self)
1445 1.1 pk struct device *self;
1446 1.1 pk {
1447 1.1 pk struct be_softc *sc = (struct be_softc *)self;
1448 1.10 pk bus_space_tag_t t = sc->sc_bustag;
1449 1.10 pk bus_space_handle_t br = sc->sc_br;
1450 1.11 pk u_int instance;
1451 1.10 pk u_int32_t v;
1452 1.10 pk
1453 1.11 pk instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1454 1.11 pk #ifdef DIAGNOSTIC
1455 1.11 pk if (instance > 1)
1456 1.11 pk panic("be_mii_statchg: instance %d out of range", instance);
1457 1.11 pk #endif
1458 1.1 pk
1459 1.10 pk /* Update duplex mode in TX configuration */
1460 1.10 pk v = bus_space_read_4(t, br, BE_BRI_TXCFG);
1461 1.10 pk if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
1462 1.10 pk v |= BE_BR_TXCFG_FULLDPLX;
1463 1.10 pk else
1464 1.10 pk v &= ~BE_BR_TXCFG_FULLDPLX;
1465 1.10 pk bus_space_write_4(t, br, BE_BRI_TXCFG, v);
1466 1.11 pk
1467 1.11 pk /* Change to appropriate gate in transceiver PAL */
1468 1.11 pk be_pal_gate(sc, sc->sc_phys[instance]);
1469 1.1 pk }
1470 1.1 pk
1471 1.12 pk /*
1472 1.12 pk * Get current media settings.
1473 1.12 pk */
1474 1.1 pk void
1475 1.12 pk be_ifmedia_sts(ifp, ifmr)
1476 1.12 pk struct ifnet *ifp;
1477 1.12 pk struct ifmediareq *ifmr;
1478 1.12 pk {
1479 1.12 pk struct be_softc *sc = ifp->if_softc;
1480 1.12 pk
1481 1.12 pk mii_pollstat(&sc->sc_mii);
1482 1.12 pk (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT);
1483 1.12 pk
1484 1.12 pk ifmr->ifm_status = sc->sc_mii.mii_media_status;
1485 1.12 pk ifmr->ifm_active = sc->sc_mii.mii_media_active;
1486 1.12 pk return;
1487 1.12 pk }
1488 1.12 pk
1489 1.12 pk /*
1490 1.12 pk * Set media options.
1491 1.12 pk */
1492 1.12 pk int
1493 1.12 pk be_ifmedia_upd(ifp)
1494 1.12 pk struct ifnet *ifp;
1495 1.1 pk {
1496 1.12 pk struct be_softc *sc = ifp->if_softc;
1497 1.12 pk int error;
1498 1.1 pk
1499 1.12 pk if ((error = mii_mediachg(&sc->sc_mii)) != 0)
1500 1.12 pk return (error);
1501 1.1 pk
1502 1.12 pk return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG));
1503 1.1 pk }
1504 1.1 pk
1505 1.12 pk /*
1506 1.12 pk * Service routine for our pseudo-MII internal transceiver.
1507 1.12 pk */
1508 1.12 pk int
1509 1.12 pk be_intphy_service(sc, mii, cmd)
1510 1.1 pk struct be_softc *sc;
1511 1.12 pk struct mii_data *mii;
1512 1.12 pk int cmd;
1513 1.1 pk {
1514 1.12 pk struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
1515 1.1 pk int bmcr, bmsr;
1516 1.13 pk int error;
1517 1.1 pk
1518 1.12 pk switch (cmd) {
1519 1.12 pk case MII_POLLSTAT:
1520 1.12 pk /*
1521 1.12 pk * If we're not polling our PHY instance, just return.
1522 1.12 pk */
1523 1.12 pk if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
1524 1.12 pk return (0);
1525 1.12 pk
1526 1.12 pk break;
1527 1.12 pk
1528 1.12 pk case MII_MEDIACHG:
1529 1.12 pk
1530 1.12 pk /*
1531 1.12 pk * If the media indicates a different PHY instance,
1532 1.12 pk * isolate ourselves.
1533 1.12 pk */
1534 1.12 pk if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) {
1535 1.13 pk bmcr = be_mii_readreg((void *)sc,
1536 1.13 pk BE_PHY_INTERNAL, MII_BMCR);
1537 1.12 pk be_mii_writereg((void *)sc,
1538 1.12 pk BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
1539 1.13 pk sc->sc_mii_flags &= ~MIIF_HAVELINK;
1540 1.13 pk sc->sc_intphy_curspeed = 0;
1541 1.12 pk return (0);
1542 1.12 pk }
1543 1.12 pk
1544 1.12 pk
1545 1.13 pk if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0)
1546 1.13 pk return (error);
1547 1.13 pk
1548 1.13 pk bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
1549 1.13 pk
1550 1.13 pk /*
1551 1.13 pk * Select the new mode and take out of isolation
1552 1.13 pk */
1553 1.12 pk if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
1554 1.12 pk bmcr |= BMCR_S100;
1555 1.12 pk else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T)
1556 1.12 pk bmcr &= ~BMCR_S100;
1557 1.13 pk else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
1558 1.13 pk if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) {
1559 1.13 pk bmcr &= ~BMCR_S100;
1560 1.13 pk bmcr |= sc->sc_intphy_curspeed;
1561 1.13 pk } else {
1562 1.13 pk /* Keep isolated until link is up */
1563 1.13 pk bmcr |= BMCR_ISO;
1564 1.13 pk sc->sc_mii_flags |= MIIF_DOINGAUTO;
1565 1.13 pk }
1566 1.13 pk }
1567 1.12 pk
1568 1.12 pk if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0)
1569 1.12 pk bmcr |= BMCR_FDX;
1570 1.12 pk else
1571 1.12 pk bmcr &= ~BMCR_FDX;
1572 1.12 pk
1573 1.12 pk be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
1574 1.12 pk break;
1575 1.12 pk
1576 1.12 pk case MII_TICK:
1577 1.12 pk /*
1578 1.12 pk * If we're not currently selected, just return.
1579 1.12 pk */
1580 1.12 pk if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
1581 1.12 pk return (0);
1582 1.12 pk
1583 1.12 pk /* Only used for automatic media selection */
1584 1.12 pk if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
1585 1.12 pk return (0);
1586 1.12 pk
1587 1.12 pk /* Is the interface even up? */
1588 1.12 pk if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
1589 1.12 pk return (0);
1590 1.12 pk
1591 1.12 pk /*
1592 1.12 pk * Check link status; if we don't have a link, try another
1593 1.12 pk * speed. We can't detect duplex mode, so half-duplex is
1594 1.12 pk * what we have to settle for.
1595 1.12 pk */
1596 1.1 pk
1597 1.12 pk /* Read twice in case the register is latched */
1598 1.12 pk bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) |
1599 1.12 pk be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR);
1600 1.12 pk
1601 1.12 pk if ((bmsr & BMSR_LINK) != 0) {
1602 1.12 pk /* We have a carrier */
1603 1.13 pk bmcr = be_mii_readreg((void *)sc,
1604 1.13 pk BE_PHY_INTERNAL, MII_BMCR);
1605 1.13 pk
1606 1.13 pk if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) {
1607 1.13 pk bmcr = be_mii_readreg((void *)sc,
1608 1.13 pk BE_PHY_INTERNAL, MII_BMCR);
1609 1.13 pk
1610 1.13 pk sc->sc_mii_flags |= MIIF_HAVELINK;
1611 1.13 pk sc->sc_intphy_curspeed = (bmcr & BMCR_S100);
1612 1.13 pk sc->sc_mii_flags &= ~MIIF_DOINGAUTO;
1613 1.13 pk
1614 1.13 pk bmcr &= ~BMCR_ISO;
1615 1.13 pk be_mii_writereg((void *)sc,
1616 1.13 pk BE_PHY_INTERNAL, MII_BMCR, bmcr);
1617 1.13 pk
1618 1.13 pk printf("%s: link up at %s Mbps\n",
1619 1.13 pk sc->sc_dev.dv_xname,
1620 1.13 pk (bmcr & BMCR_S100) ? "100" : "10");
1621 1.13 pk }
1622 1.12 pk return (0);
1623 1.12 pk }
1624 1.1 pk
1625 1.13 pk if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) {
1626 1.13 pk sc->sc_mii_flags |= MIIF_DOINGAUTO;
1627 1.13 pk sc->sc_mii_flags &= ~MIIF_HAVELINK;
1628 1.13 pk sc->sc_intphy_curspeed = 0;
1629 1.13 pk printf("%s: link down\n", sc->sc_dev.dv_xname);
1630 1.13 pk }
1631 1.13 pk
1632 1.12 pk /* Only retry autonegotiation every 5 seconds. */
1633 1.13 pk if (++sc->sc_mii_ticks < 5)
1634 1.12 pk return(0);
1635 1.12 pk
1636 1.12 pk sc->sc_mii_ticks = 0;
1637 1.12 pk bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
1638 1.12 pk /* Just flip the fast speed bit */
1639 1.12 pk bmcr ^= BMCR_S100;
1640 1.12 pk be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
1641 1.1 pk
1642 1.12 pk break;
1643 1.1 pk
1644 1.12 pk case MII_DOWN:
1645 1.13 pk /* Isolate this phy */
1646 1.13 pk bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
1647 1.13 pk be_mii_writereg((void *)sc,
1648 1.13 pk BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
1649 1.12 pk return (0);
1650 1.1 pk }
1651 1.1 pk
1652 1.12 pk /* Update the media status. */
1653 1.12 pk be_intphy_status(sc);
1654 1.10 pk
1655 1.12 pk /* Callback if something changed. */
1656 1.12 pk if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
1657 1.12 pk (*mii->mii_statchg)((struct device *)sc);
1658 1.12 pk sc->sc_mii_active = mii->mii_media_active;
1659 1.12 pk }
1660 1.12 pk return (0);
1661 1.1 pk }
1662 1.1 pk
1663 1.1 pk /*
1664 1.12 pk * Determine status of internal transceiver
1665 1.1 pk */
1666 1.1 pk void
1667 1.12 pk be_intphy_status(sc)
1668 1.12 pk struct be_softc *sc;
1669 1.1 pk {
1670 1.12 pk struct mii_data *mii = &sc->sc_mii;
1671 1.10 pk int media_active, media_status;
1672 1.1 pk int bmcr, bmsr;
1673 1.1 pk
1674 1.10 pk media_status = IFM_AVALID;
1675 1.10 pk media_active = 0;
1676 1.10 pk
1677 1.1 pk /*
1678 1.1 pk * Internal transceiver; do the work here.
1679 1.1 pk */
1680 1.4 pk bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR);
1681 1.1 pk
1682 1.1 pk switch (bmcr & (BMCR_S100 | BMCR_FDX)) {
1683 1.1 pk case (BMCR_S100 | BMCR_FDX):
1684 1.10 pk media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1685 1.1 pk break;
1686 1.1 pk case BMCR_S100:
1687 1.10 pk media_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1688 1.1 pk break;
1689 1.1 pk case BMCR_FDX:
1690 1.10 pk media_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1691 1.1 pk break;
1692 1.1 pk case 0:
1693 1.10 pk media_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1694 1.1 pk break;
1695 1.1 pk }
1696 1.1 pk
1697 1.1 pk /* Read twice in case the register is latched */
1698 1.4 pk bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)|
1699 1.4 pk be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR);
1700 1.1 pk if (bmsr & BMSR_LINK)
1701 1.11 pk media_status |= IFM_ACTIVE;
1702 1.10 pk
1703 1.12 pk mii->mii_media_status = media_status;
1704 1.12 pk mii->mii_media_active = media_active;
1705 1.1 pk }
1706