be.c revision 1.1
1 /* $NetBSD: be.c,v 1.1 1999/01/16 12:43:09 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/kernel.h> 77 #include <sys/errno.h> 78 #include <sys/ioctl.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/syslog.h> 82 #include <sys/device.h> 83 #include <sys/malloc.h> 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_types.h> 91 #include <net/netisr.h> 92 #include <net/if_media.h> 93 #include <net/if_ether.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_inarp.h> 98 #include <netinet/in_systm.h> 99 #include <netinet/in_var.h> 100 #include <netinet/ip.h> 101 #endif 102 103 #if NBPFILTER > 0 104 #include <net/bpf.h> 105 #include <net/bpfdesc.h> 106 #endif 107 108 #include <machine/autoconf.h> 109 #include <machine/cpu.h> 110 111 #include <dev/sbus/sbusvar.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 116 #include <dev/sbus/qecreg.h> 117 #include <dev/sbus/qecvar.h> 118 #include <dev/sbus/bereg.h> 119 120 struct be_softc { 121 struct device sc_dev; 122 struct sbusdev sc_sd; /* sbus device */ 123 bus_space_tag_t sc_bustag; /* bus & dma tags */ 124 bus_dma_tag_t sc_dmatag; 125 struct ethercom sc_ethercom; 126 /*struct ifmedia sc_ifmedia; -* interface media */ 127 struct mii_data sc_mii; /* MII media control */ 128 #define sc_media sc_mii.mii_media/* shorthand */ 129 130 struct qec_softc *sc_qec; /* QEC parent */ 131 132 bus_space_handle_t sc_qr; /* QEC registers */ 133 bus_space_handle_t sc_br; /* BE registers */ 134 bus_space_handle_t sc_cr; /* channel registers */ 135 bus_space_handle_t sc_tr; /* transceiver registers */ 136 137 u_int sc_rev; 138 139 int sc_channel; /* channel number */ 140 int sc_promisc; 141 int sc_burst; 142 int sc_conf; 143 #define BE_CONF_MII 1 144 int sc_nticks; /* negotiation ticks */ 145 146 /* Ring Descriptors */ 147 caddr_t sc_membase; 148 bus_addr_t sc_dmabase; 149 struct qec_xd *sc_txd; /* Transmit descriptors */ 150 bus_addr_t sc_txddma; /* DMA address of same */ 151 struct qec_xd *sc_rxd; /* Receive descriptors */ 152 bus_addr_t sc_rxddma; /* DMA address of same */ 153 caddr_t sc_txbuf; /* Transmit buffers */ 154 caddr_t sc_rxbuf; /* Receive buffers */ 155 int sc_ntbuf; /* # of transmit buffers */ 156 int sc_nrbuf; /* # of receive buffers */ 157 158 /* Ring Descriptor state */ 159 int sc_tdhead, sc_tdtail; 160 int sc_rdtail; 161 int sc_td_nbusy; 162 163 /* MAC address */ 164 u_int8_t sc_enaddr[6]; 165 }; 166 167 int bematch __P((struct device *, struct cfdata *, void *)); 168 void beattach __P((struct device *, struct device *, void *)); 169 170 void beinit __P((struct be_softc *)); 171 void bememinit __P((struct be_softc *)); 172 void bestart __P((struct ifnet *)); 173 void bestop __P((struct be_softc *)); 174 void bewatchdog __P((struct ifnet *)); 175 int beioctl __P((struct ifnet *, u_long, caddr_t)); 176 void bereset __P((struct be_softc *)); 177 178 int beintr __P((void *)); 179 int berint __P((struct be_softc *)); 180 int betint __P((struct be_softc *)); 181 int beqint __P((struct be_softc *, u_int32_t)); 182 int beeint __P((struct be_softc *, u_int32_t)); 183 184 static void be_read __P((struct be_softc *, int, int)); 185 static int be_put __P((struct be_softc *, int, struct mbuf *)); 186 static struct mbuf *be_get __P((struct be_softc *, int, int)); 187 188 void be_tcvr_init __P((struct be_softc *)); 189 190 /* ifmedia callbacks */ 191 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 192 int be_ifmedia_upd __P((struct ifnet *)); 193 void be_mcreset __P((struct be_softc *)); 194 195 /* MII methods & callbacks */ 196 static int be_mii_readreg __P((struct device *, int, int)); 197 static void be_mii_writereg __P((struct device *, int, int, int)); 198 static void be_statchg __P((struct device *)); 199 200 /* MII helpers */ 201 static int be_mii_readreg1 __P((struct device *, int, int)); 202 static void be_mii_sync __P((struct be_softc *)); 203 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 204 static int be_mii_reset __P((struct be_softc *, int)); 205 static int be_tcvr_read_bit __P((struct be_softc *, int)); 206 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 207 208 void be_tick __P((void *)); 209 void be_internal_phy_auto __P((struct be_softc *)); 210 211 212 struct cfattach be_ca = { 213 sizeof(struct be_softc), bematch, beattach 214 }; 215 216 int 217 bematch(parent, cf, aux) 218 struct device *parent; 219 struct cfdata *cf; 220 void *aux; 221 { 222 struct sbus_attach_args *sa = aux; 223 224 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 225 } 226 227 void 228 beattach(parent, self, aux) 229 struct device *parent, *self; 230 void *aux; 231 { 232 struct sbus_attach_args *sa = aux; 233 struct qec_softc *qec = (struct qec_softc *)parent; 234 struct be_softc *sc = (struct be_softc *)self; 235 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 236 struct mii_data *mii = &sc->sc_mii; 237 int node = sa->sa_node; 238 bus_dma_segment_t seg; 239 bus_size_t size; 240 int rseg, error; 241 extern void myetheraddr __P((u_char *)); 242 243 if (sa->sa_nreg < 3) { 244 printf("%s: only %d register sets\n", 245 self->dv_xname, sa->sa_nreg); 246 return; 247 } 248 249 if (bus_space_map2(sa->sa_bustag, 250 (bus_type_t)sa->sa_reg[0].sbr_slot, 251 (bus_addr_t)sa->sa_reg[0].sbr_offset, 252 (bus_size_t)sa->sa_reg[0].sbr_size, 253 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 254 printf("beattach: cannot map registers\n"); 255 return; 256 } 257 258 if (bus_space_map2(sa->sa_bustag, 259 (bus_type_t)sa->sa_reg[1].sbr_slot, 260 (bus_addr_t)sa->sa_reg[1].sbr_offset, 261 (bus_size_t)sa->sa_reg[1].sbr_size, 262 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 263 printf("beattach: cannot map registers\n"); 264 return; 265 } 266 267 if (bus_space_map2(sa->sa_bustag, 268 (bus_type_t)sa->sa_reg[2].sbr_slot, 269 (bus_addr_t)sa->sa_reg[2].sbr_offset, 270 (bus_size_t)sa->sa_reg[2].sbr_size, 271 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 272 printf("beattach: cannot map registers\n"); 273 return; 274 } 275 276 sc->sc_qec = qec; 277 sc->sc_qr = qec->sc_regs; 278 279 sc->sc_rev = getpropint(node, "board-version", -1); 280 printf(" rev %x", sc->sc_rev); 281 282 bestop(sc); 283 284 sc->sc_channel = getpropint(node, "channel#", -1); 285 if (sc->sc_channel == -1) 286 sc->sc_channel = 0; 287 288 sc->sc_burst = getpropint(node, "burst-sizes", -1); 289 if (sc->sc_burst == -1) 290 sc->sc_burst = qec->sc_burst; 291 292 /* Clamp at parent's burst sizes */ 293 sc->sc_burst &= qec->sc_burst; 294 295 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 0, beintr, sc); 296 297 myetheraddr(sc->sc_enaddr); 298 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 299 300 /* 301 * Allocate descriptor ring and buffers. 302 */ 303 sc->sc_ntbuf = QEC_XD_RING_MAXSIZE; /* for now, allocate as many bufs */ 304 sc->sc_nrbuf = QEC_XD_RING_MAXSIZE; /* as there are ring descriptors */ 305 306 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 307 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 308 sc->sc_ntbuf * BE_PKT_BUF_SZ + 309 sc->sc_nrbuf * BE_PKT_BUF_SZ; 310 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 311 NBPG, 0, 312 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 313 printf("%s: DMA buffer alloc error %d\n", 314 self->dv_xname, error); 315 return; 316 } 317 sc->sc_dmabase = seg.ds_addr; 318 319 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 320 &sc->sc_membase, 321 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 322 printf("%s: DMA buffer map error %d\n", 323 self->dv_xname, error); 324 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 325 return; 326 } 327 328 /* 329 * Initialize transceiver and determine which PHY connection to use. 330 */ 331 be_tcvr_init(sc); 332 333 /* 334 * Initialize our media structures and MII info. 335 */ 336 mii->mii_ifp = ifp; 337 mii->mii_readreg = be_mii_readreg; 338 mii->mii_writereg = be_mii_writereg; 339 mii->mii_statchg = be_statchg; 340 341 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 342 343 if ((sc->sc_conf & BE_CONF_MII) != 0) { 344 #if 1 345 mii_phy_probe(&sc->sc_dev, mii, 0xffffffff); 346 #else 347 /* TEST */ 348 extern int mii_print __P((void *, const char *)); 349 struct mii_attach_args ma; 350 struct mii_softc *child; 351 352 bzero(&ma, sizeof(ma)); 353 ma.mii_phyno = BE_PHY_INTERNAL; 354 ma.mii_data = mii; 355 ma.mii_capmask = 0xffffffff; 356 if ((child = (struct mii_softc *) 357 config_found(&sc->sc_dev, &ma, mii_print)) != NULL) { 358 /* 359 * Link it up in the parent's MII data. 360 */ 361 LIST_INSERT_HEAD(&mii->mii_phys, child, mii_list); 362 mii->mii_instance++; 363 } 364 #endif 365 366 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 367 /* No PHY attached */ 368 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_NONE, 0, NULL); 369 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_NONE); 370 } else { 371 /* 372 * XXX - we can really do the following ONLY if the 373 * phy indeed has the auto negotiation capability!! 374 */ 375 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 376 } 377 } else { 378 /* 379 * The be internal phy looks vaguely like MII hardware, 380 * but not enough to be able to use the MII device 381 * layer. Hence, we have to take care of media selection 382 * ourselves. 383 */ 384 385 /* Use `ifm_data' to store BMCR bits */ 386 ifmedia_add(&sc->sc_media, 387 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 388 0, NULL); 389 ifmedia_add(&sc->sc_media, 390 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,IFM_FDX,0), 391 BMCR_FDX, NULL); 392 ifmedia_add(&sc->sc_media, 393 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,0), 394 BMCR_S100, NULL); 395 ifmedia_add(&sc->sc_media, 396 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,IFM_FDX,0), 397 BMCR_S100|BMCR_FDX, NULL); 398 ifmedia_add(&sc->sc_media, 399 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 400 0, NULL); 401 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 402 } 403 404 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 405 ifp->if_softc = sc; 406 ifp->if_start = bestart; 407 ifp->if_ioctl = beioctl; 408 ifp->if_watchdog = bewatchdog; 409 ifp->if_flags = 410 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 411 412 /* Attach the interface. */ 413 if_attach(ifp); 414 ether_ifattach(ifp, sc->sc_enaddr); 415 416 #if NBPFILTER > 0 417 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, 418 sizeof(struct ether_header)); 419 #endif 420 } 421 422 423 /* 424 * Routine to copy from mbuf chain to transmit buffer in 425 * network buffer memory. 426 */ 427 static __inline__ int 428 be_put(sc, idx, m) 429 struct be_softc *sc; 430 int idx; 431 struct mbuf *m; 432 { 433 struct mbuf *n; 434 int len, tlen = 0, boff = 0; 435 caddr_t bp = sc->sc_txbuf + (idx % sc->sc_ntbuf) * BE_PKT_BUF_SZ; 436 437 for (; m; m = n) { 438 len = m->m_len; 439 if (len == 0) { 440 MFREE(m, n); 441 continue; 442 } 443 bcopy(mtod(m, caddr_t), bp+boff, len); 444 boff += len; 445 tlen += len; 446 MFREE(m, n); 447 } 448 return (tlen); 449 } 450 451 /* 452 * Pull data off an interface. 453 * Len is the length of data, with local net header stripped. 454 * We copy the data into mbufs. When full cluster sized units are present, 455 * we copy into clusters. 456 */ 457 static __inline__ struct mbuf * 458 be_get(sc, idx, totlen) 459 struct be_softc *sc; 460 int idx, totlen; 461 { 462 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 463 struct mbuf *m; 464 struct mbuf *top, **mp; 465 int len, pad, boff = 0; 466 caddr_t bp = sc->sc_rxbuf + (idx % sc->sc_nrbuf) * BE_PKT_BUF_SZ; 467 468 MGETHDR(m, M_DONTWAIT, MT_DATA); 469 if (m == NULL) 470 return (NULL); 471 m->m_pkthdr.rcvif = ifp; 472 m->m_pkthdr.len = totlen; 473 474 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 475 m->m_data += pad; 476 len = MHLEN - pad; 477 top = NULL; 478 mp = ⊤ 479 480 while (totlen > 0) { 481 if (top) { 482 MGET(m, M_DONTWAIT, MT_DATA); 483 if (m == NULL) { 484 m_freem(top); 485 return (NULL); 486 } 487 len = MLEN; 488 } 489 if (top && totlen >= MINCLSIZE) { 490 MCLGET(m, M_DONTWAIT); 491 if (m->m_flags & M_EXT) 492 len = MCLBYTES; 493 } 494 m->m_len = len = min(totlen, len); 495 bcopy(bp + boff, mtod(m, caddr_t), len); 496 boff += len; 497 totlen -= len; 498 *mp = m; 499 mp = &m->m_next; 500 } 501 502 return (top); 503 } 504 505 /* 506 * Pass a packet to the higher levels. 507 */ 508 static __inline__ void 509 be_read(sc, idx, len) 510 struct be_softc *sc; 511 int idx, len; 512 { 513 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 514 struct ether_header *eh; 515 struct mbuf *m; 516 517 if (len <= sizeof(struct ether_header) || 518 len > ETHERMTU + sizeof(struct ether_header)) { 519 520 printf("%s: invalid packet size %d; dropping\n", 521 ifp->if_xname, len); 522 523 ifp->if_ierrors++; 524 return; 525 } 526 527 /* 528 * Pull packet off interface. 529 */ 530 m = be_get(sc, idx, len); 531 if (m == NULL) { 532 ifp->if_ierrors++; 533 return; 534 } 535 ifp->if_ipackets++; 536 537 /* We assume that the header fits entirely in one mbuf. */ 538 eh = mtod(m, struct ether_header *); 539 540 #if NBPFILTER > 0 541 /* 542 * Check if there's a BPF listener on this interface. 543 * If so, hand off the raw packet to BPF. 544 */ 545 if (ifp->if_bpf) 546 bpf_mtap(ifp->if_bpf, m); 547 #endif 548 /* Pass the packet up, with the ether header sort-of removed. */ 549 m_adj(m, sizeof(struct ether_header)); 550 ether_input(ifp, eh, m); 551 } 552 553 /* 554 * Start output on interface. 555 * We make two assumptions here: 556 * 1) that the current priority is set to splnet _before_ this code 557 * is called *and* is returned to the appropriate priority after 558 * return 559 * 2) that the IFF_OACTIVE flag is checked before this code is called 560 * (i.e. that the output part of the interface is idle) 561 */ 562 void 563 bestart(ifp) 564 struct ifnet *ifp; 565 { 566 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 567 struct qec_xd *txd = sc->sc_txd; 568 struct mbuf *m; 569 unsigned int bix, len; 570 unsigned int ntbuf = sc->sc_ntbuf; 571 572 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 573 return; 574 575 bix = sc->sc_tdhead; 576 577 for (;;) { 578 IF_DEQUEUE(&ifp->if_snd, m); 579 if (m == 0) 580 break; 581 582 #if NBPFILTER > 0 583 /* 584 * If BPF is listening on this interface, let it see the 585 * packet before we commit it to the wire. 586 */ 587 if (ifp->if_bpf) 588 bpf_mtap(ifp->if_bpf, m); 589 #endif 590 591 /* 592 * Copy the mbuf chain into the transmit buffer. 593 */ 594 len = be_put(sc, bix, m); 595 596 /* 597 * Initialize transmit registers and start transmission 598 */ 599 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 600 (len & QEC_XD_LENGTH); 601 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 602 BE_CR_CTRL_TWAKEUP); 603 604 if (++bix == QEC_XD_RING_MAXSIZE) 605 bix = 0; 606 607 if (++sc->sc_td_nbusy == ntbuf) { 608 ifp->if_flags |= IFF_OACTIVE; 609 break; 610 } 611 } 612 613 sc->sc_tdhead = bix; 614 } 615 616 void 617 bestop(sc) 618 struct be_softc *sc; 619 { 620 int n; 621 bus_space_tag_t t = sc->sc_bustag; 622 bus_space_handle_t br = sc->sc_br; 623 624 untimeout(be_tick, sc); 625 626 /* Stop the transmitter */ 627 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 628 for (n = 32; n > 0; n--) { 629 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 630 break; 631 DELAY(20); 632 } 633 634 /* Stop the receiver */ 635 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 636 for (n = 32; n > 0; n--) { 637 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 638 break; 639 DELAY(20); 640 } 641 } 642 643 /* 644 * Reset interface. 645 */ 646 void 647 bereset(sc) 648 struct be_softc *sc; 649 { 650 int s; 651 652 s = splnet(); 653 bestop(sc); 654 beinit(sc); 655 splx(s); 656 } 657 658 void 659 bewatchdog(ifp) 660 struct ifnet *ifp; 661 { 662 struct be_softc *sc = ifp->if_softc; 663 664 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 665 ++sc->sc_ethercom.ec_if.if_oerrors; 666 667 bereset(sc); 668 } 669 670 int 671 beintr(v) 672 void *v; 673 { 674 struct be_softc *sc = (struct be_softc *)v; 675 bus_space_tag_t t = sc->sc_bustag; 676 u_int32_t whyq, whyb, whyc; 677 int r = 0; 678 679 /* Read QEC status, channel status and BE status */ 680 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 681 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 682 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 683 684 if (whyq & QEC_STAT_BM) 685 r |= beeint(sc, whyb); 686 687 if (whyq & QEC_STAT_ER) 688 r |= beqint(sc, whyc); 689 690 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 691 r |= betint(sc); 692 693 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 694 r |= berint(sc); 695 696 return (r); 697 } 698 699 /* 700 * QEC Interrupt. 701 */ 702 int 703 beqint(sc, why) 704 struct be_softc *sc; 705 u_int32_t why; 706 { 707 int r = 0, rst = 0; 708 709 if (why & BE_CR_STAT_TXIRQ) 710 r |= 1; 711 if (why & BE_CR_STAT_RXIRQ) 712 r |= 1; 713 714 if (why & BE_CR_STAT_BERROR) { 715 r |= 1; 716 rst = 1; 717 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 718 } 719 720 if (why & BE_CR_STAT_TXDERR) { 721 r |= 1; 722 rst = 1; 723 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 724 } 725 726 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 727 r |= 1; 728 rst = 1; 729 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 730 if (why & BE_CR_STAT_TXLERR) 731 printf("Late "); 732 if (why & BE_CR_STAT_TXPERR) 733 printf("Parity "); 734 if (why & BE_CR_STAT_TXSERR) 735 printf("Generic "); 736 printf(")\n"); 737 } 738 739 if (why & BE_CR_STAT_RXDROP) { 740 r |= 1; 741 rst = 1; 742 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 743 } 744 745 if (why & BE_CR_STAT_RXSMALL) { 746 r |= 1; 747 rst = 1; 748 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 749 } 750 751 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 752 r |= 1; 753 rst = 1; 754 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 755 if (why & BE_CR_STAT_RXLERR) 756 printf("Late "); 757 if (why & BE_CR_STAT_RXPERR) 758 printf("Parity "); 759 if (why & BE_CR_STAT_RXSERR) 760 printf("Generic "); 761 printf(")\n"); 762 } 763 764 if (!r) { 765 rst = 1; 766 printf("%s: unexpected error interrupt %08x\n", 767 sc->sc_dev.dv_xname, why); 768 } 769 770 if (rst) { 771 printf("%s: resetting\n", sc->sc_dev.dv_xname); 772 bereset(sc); 773 } 774 775 return (r); 776 } 777 778 /* 779 * Error interrupt. 780 */ 781 int 782 beeint(sc, why) 783 struct be_softc *sc; 784 u_int32_t why; 785 { 786 int r = 0, rst = 0; 787 788 if (why & BE_BR_STAT_RFIFOVF) { 789 r |= 1; 790 rst = 1; 791 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 792 } 793 if (why & BE_BR_STAT_TFIFO_UND) { 794 r |= 1; 795 rst = 1; 796 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 797 } 798 if (why & BE_BR_STAT_MAXPKTERR) { 799 r |= 1; 800 rst = 1; 801 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 802 } 803 804 if (!r) { 805 rst = 1; 806 printf("%s: unexpected error interrupt %08x\n", 807 sc->sc_dev.dv_xname, why); 808 } 809 810 if (rst) { 811 printf("%s: resetting\n", sc->sc_dev.dv_xname); 812 bereset(sc); 813 } 814 815 return (r); 816 } 817 818 /* 819 * Transmit interrupt. 820 */ 821 int 822 betint(sc) 823 struct be_softc *sc; 824 { 825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 826 bus_space_tag_t t = sc->sc_bustag; 827 bus_space_handle_t br = sc->sc_br; 828 unsigned int bix, txflags; 829 830 /* 831 * Unload collision counters 832 */ 833 ifp->if_collisions += 834 bus_space_read_4(t, br, BE_BRI_NCCNT) + 835 bus_space_read_4(t, br, BE_BRI_FCCNT) + 836 bus_space_read_4(t, br, BE_BRI_EXCNT) + 837 bus_space_read_4(t, br, BE_BRI_LTCNT); 838 839 /* 840 * the clear the hardware counters 841 */ 842 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 843 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 844 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 845 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 846 847 bix = sc->sc_tdtail; 848 849 for (;;) { 850 if (sc->sc_td_nbusy <= 0) 851 break; 852 853 txflags = sc->sc_txd[bix].xd_flags; 854 855 if (txflags & QEC_XD_OWN) 856 break; 857 858 ifp->if_flags &= ~IFF_OACTIVE; 859 ifp->if_opackets++; 860 861 if (++bix == QEC_XD_RING_MAXSIZE) 862 bix = 0; 863 864 --sc->sc_td_nbusy; 865 } 866 867 sc->sc_tdtail = bix; 868 869 bestart(ifp); 870 871 if (sc->sc_td_nbusy == 0) 872 ifp->if_timer = 0; 873 874 return (1); 875 } 876 877 /* 878 * Receive interrupt. 879 */ 880 int 881 berint(sc) 882 struct be_softc *sc; 883 { 884 struct qec_xd *xd = sc->sc_rxd; 885 unsigned int bix, len; 886 unsigned int nrbuf = sc->sc_nrbuf; 887 888 bix = sc->sc_rdtail; 889 890 /* 891 * Process all buffers with valid data. 892 */ 893 for (;;) { 894 len = xd[bix].xd_flags; 895 if (len & QEC_XD_OWN) 896 break; 897 898 len &= QEC_XD_LENGTH; 899 be_read(sc, bix, len); 900 901 /* ... */ 902 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 903 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 904 905 if (++bix == QEC_XD_RING_MAXSIZE) 906 bix = 0; 907 } 908 909 sc->sc_rdtail = bix; 910 911 return (1); 912 } 913 914 int 915 beioctl(ifp, cmd, data) 916 struct ifnet *ifp; 917 u_long cmd; 918 caddr_t data; 919 { 920 struct be_softc *sc = ifp->if_softc; 921 struct ifaddr *ifa = (struct ifaddr *)data; 922 struct ifreq *ifr = (struct ifreq *)data; 923 int s, error = 0; 924 925 s = splnet(); 926 927 switch (cmd) { 928 case SIOCSIFADDR: 929 ifp->if_flags |= IFF_UP; 930 switch (ifa->ifa_addr->sa_family) { 931 #ifdef INET 932 case AF_INET: 933 beinit(sc); 934 arp_ifinit(ifp, ifa); 935 break; 936 #endif /* INET */ 937 #ifdef NS 938 /* XXX - This code is probably wrong. */ 939 case AF_NS: 940 { 941 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 942 943 if (ns_nullhost(*ina)) 944 ina->x_host = *(union ns_host *) 945 (sc->sc_ethercom.ac_enaddr); 946 else 947 bcopy(ina->x_host.c_host, 948 sc->sc_enaddr, sizeof(sc->sc_enaddr)); 949 /* Set new address. */ 950 beinit(sc); 951 break; 952 } 953 #endif /* NS */ 954 default: 955 beinit(sc); 956 break; 957 } 958 break; 959 960 case SIOCSIFFLAGS: 961 sc->sc_promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 962 if ((ifp->if_flags & IFF_UP) == 0 && 963 (ifp->if_flags & IFF_RUNNING) != 0) { 964 /* 965 * If interface is marked down and it is running, then 966 * stop it. 967 */ 968 bestop(sc); 969 ifp->if_flags &= ~IFF_RUNNING; 970 } else if ((ifp->if_flags & IFF_UP) != 0 && 971 (ifp->if_flags & IFF_RUNNING) == 0) { 972 /* 973 * If interface is marked up and it is stopped, then 974 * start it. 975 */ 976 beinit(sc); 977 } else { 978 /* 979 * Reset the interface to pick up changes in any other 980 * flags that affect hardware registers. 981 */ 982 bestop(sc); 983 beinit(sc); 984 } 985 #ifdef BEDEBUG 986 if (ifp->if_flags & IFF_DEBUG) 987 sc->sc_debug = BE_XXX; 988 else 989 sc->sc_debug = 0; 990 #endif 991 break; 992 993 case SIOCADDMULTI: 994 case SIOCDELMULTI: 995 error = (cmd == SIOCADDMULTI) ? 996 ether_addmulti(ifr, &sc->sc_ethercom): 997 ether_delmulti(ifr, &sc->sc_ethercom); 998 999 if (error == ENETRESET) { 1000 /* 1001 * Multicast list has changed; set the hardware filter 1002 * accordingly. 1003 */ 1004 be_mcreset(sc); 1005 error = 0; 1006 } 1007 break; 1008 case SIOCGIFMEDIA: 1009 case SIOCSIFMEDIA: 1010 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1011 break; 1012 default: 1013 error = EINVAL; 1014 break; 1015 } 1016 splx(s); 1017 return (error); 1018 } 1019 1020 void 1021 bememinit(sc) 1022 struct be_softc *sc; 1023 { 1024 bus_addr_t txbufdma, rxbufdma; 1025 bus_addr_t dma; 1026 caddr_t p; 1027 unsigned int ntbuf, nrbuf, i; 1028 1029 p = sc->sc_membase; 1030 dma = sc->sc_dmabase; 1031 1032 ntbuf = sc->sc_ntbuf; 1033 nrbuf = sc->sc_nrbuf; 1034 1035 /* 1036 * Allocate transmit descriptors 1037 */ 1038 sc->sc_txd = (struct qec_xd *)p; 1039 sc->sc_txddma = dma; 1040 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 1041 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 1042 1043 /* 1044 * Allocate receive descriptors 1045 */ 1046 sc->sc_rxd = (struct qec_xd *)p; 1047 sc->sc_rxddma = dma; 1048 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 1049 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 1050 1051 1052 /* 1053 * Allocate transmit buffers 1054 */ 1055 sc->sc_txbuf = p; 1056 txbufdma = dma; 1057 p += ntbuf * BE_PKT_BUF_SZ; 1058 dma += ntbuf * BE_PKT_BUF_SZ; 1059 1060 /* 1061 * Allocate receive buffers 1062 */ 1063 sc->sc_rxbuf = p; 1064 rxbufdma = dma; 1065 p += nrbuf * BE_PKT_BUF_SZ; 1066 dma += nrbuf * BE_PKT_BUF_SZ; 1067 1068 /* 1069 * Initialize transmit buffer descriptors 1070 */ 1071 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 1072 sc->sc_txd[i].xd_addr = (u_int32_t) 1073 (txbufdma + (i % ntbuf) * BE_PKT_BUF_SZ); 1074 sc->sc_txd[i].xd_flags = 0; 1075 } 1076 1077 /* 1078 * Initialize receive buffer descriptors 1079 */ 1080 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 1081 sc->sc_rxd[i].xd_addr = (u_int32_t) 1082 (rxbufdma + (i % nrbuf) * BE_PKT_BUF_SZ); 1083 sc->sc_rxd[i].xd_flags = (i < nrbuf) 1084 ? QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH) 1085 : 0; 1086 } 1087 1088 sc->sc_tdhead = sc->sc_tdtail = 0; 1089 sc->sc_td_nbusy = 0; 1090 sc->sc_rdtail = 0; 1091 } 1092 1093 void 1094 beinit(sc) 1095 struct be_softc *sc; 1096 { 1097 bus_space_tag_t t = sc->sc_bustag; 1098 bus_space_handle_t br = sc->sc_br; 1099 bus_space_handle_t cr = sc->sc_cr; 1100 struct qec_softc *qec = sc->sc_qec; 1101 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1102 u_int32_t qecaddr; 1103 u_int8_t *ea; 1104 int s; 1105 1106 s = splimp(); 1107 1108 sc->sc_nticks = 0; 1109 1110 bememinit(sc); 1111 be_tcvr_init(sc); 1112 1113 be_ifmedia_upd(ifp); 1114 1115 bestop(sc); 1116 1117 ea = sc->sc_enaddr; 1118 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1119 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1120 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1121 1122 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1123 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1124 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1125 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1126 1127 DELAY(20); 1128 1129 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1130 1131 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1132 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1133 1134 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1135 1136 /* 1137 * Turn off counter expiration interrupts as well as 1138 * 'gotframe' and 'sentframe' 1139 */ 1140 bus_space_write_4(t, br, BE_BRI_IMASK, 1141 BE_BR_IMASK_GOTFRAME | 1142 BE_BR_IMASK_RCNTEXP | 1143 BE_BR_IMASK_ACNTEXP | 1144 BE_BR_IMASK_CCNTEXP | 1145 BE_BR_IMASK_LCNTEXP | 1146 BE_BR_IMASK_CVCNTEXP | 1147 BE_BR_IMASK_SENTFRAME | 1148 BE_BR_IMASK_NCNTEXP | 1149 BE_BR_IMASK_ECNTEXP | 1150 BE_BR_IMASK_LCCNTEXP | 1151 BE_BR_IMASK_FCNTEXP | 1152 BE_BR_IMASK_DTIMEXP); 1153 1154 /* Channel registers: */ 1155 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rxddma); 1156 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_txddma); 1157 1158 qecaddr = sc->sc_channel * qec->sc_msize; 1159 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1160 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1161 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1162 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1163 1164 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1165 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1166 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1167 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1168 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1169 1170 /* Enable transmitter */ 1171 bus_space_write_4(t, br, BE_BRI_TXCFG, 1172 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1173 1174 /* Enable receiver */ 1175 bus_space_write_4(t, br, BE_BRI_RXCFG, 1176 BE_BR_RXCFG_HENABLE | BE_BR_RXCFG_FIFO | 1177 BE_BR_RXCFG_ENABLE); 1178 1179 ifp->if_flags |= IFF_RUNNING; 1180 ifp->if_flags &= ~IFF_OACTIVE; 1181 1182 timeout(be_tick, sc, hz); 1183 splx(s); 1184 } 1185 1186 void 1187 be_mcreset(sc) 1188 struct be_softc *sc; 1189 { 1190 struct ethercom *ac = &sc->sc_ethercom; 1191 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1192 bus_space_tag_t t = sc->sc_bustag; 1193 bus_space_handle_t br = sc->sc_br; 1194 u_int32_t crc; 1195 u_int16_t hash[4]; 1196 u_int8_t octet; 1197 int i, j; 1198 struct ether_multi *enm; 1199 struct ether_multistep step; 1200 1201 if (ifp->if_flags & IFF_ALLMULTI) { 1202 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0xffff); 1203 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0xffff); 1204 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0xffff); 1205 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0xffff); 1206 return; 1207 } 1208 1209 if (ifp->if_flags & IFF_PROMISC) { 1210 u_int32_t v; 1211 1212 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1213 v |= BE_BR_RXCFG_PMISC; 1214 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1215 return; 1216 } 1217 1218 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1219 1220 ETHER_FIRST_MULTI(step, ac, enm); 1221 while (enm != NULL) { 1222 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1223 /* 1224 * We must listen to a range of multicast 1225 * addresses. For now, just accept all 1226 * multicasts, rather than trying to set only 1227 * those filter bits needed to match the range. 1228 * (At this time, the only use of address 1229 * ranges is for IP multicast routing, for 1230 * which the range is big enough to require 1231 * all bits set.) 1232 */ 1233 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0xffff); 1234 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0xffff); 1235 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0xffff); 1236 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0xffff); 1237 ifp->if_flags |= IFF_ALLMULTI; 1238 return; 1239 } 1240 1241 crc = 0xffffffff; 1242 1243 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1244 octet = enm->enm_addrlo[i]; 1245 1246 for (j = 0; j < 8; j++) { 1247 if ((crc & 1) ^ (octet & 1)) { 1248 crc >>= 1; 1249 crc ^= MC_POLY_LE; 1250 } 1251 else 1252 crc >>= 1; 1253 octet >>= 1; 1254 } 1255 } 1256 1257 crc >>= 26; 1258 hash[crc >> 4] |= 1 << (crc & 0xf); 1259 ETHER_NEXT_MULTI(step, enm); 1260 } 1261 1262 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1263 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1264 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1265 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1266 ifp->if_flags &= ~IFF_ALLMULTI; 1267 } 1268 1269 /* 1270 * Set the tcvr to an idle state 1271 */ 1272 void 1273 be_mii_sync(sc) 1274 struct be_softc *sc; 1275 { 1276 bus_space_tag_t t = sc->sc_bustag; 1277 bus_space_handle_t tr = sc->sc_tr; 1278 int n = 20; 1279 1280 while (n--) { 1281 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1282 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1283 MGMT_PAL_OENAB); 1284 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1285 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1286 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1287 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1288 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1289 } 1290 } 1291 1292 /* 1293 * Initialize the transceiver and figure out whether we're using the 1294 * external or internal one. 1295 */ 1296 void 1297 be_tcvr_init(sc) 1298 struct be_softc *sc; 1299 { 1300 bus_space_tag_t t = sc->sc_bustag; 1301 bus_space_handle_t tr = sc->sc_tr; 1302 u_int32_t v; 1303 1304 be_mii_sync(sc); 1305 1306 if (sc->sc_rev != 1) { 1307 printf("%s: rev %d PAL not supported.\n", 1308 sc->sc_dev.dv_xname, 1309 sc->sc_rev); 1310 return; 1311 } 1312 1313 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1314 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1315 MGMT_PAL_DCLOCK); 1316 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1317 1318 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1319 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO); 1320 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1321 DELAY(200); 1322 1323 v = bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1324 #ifdef DEBUG 1325 if (bedebug) { 1326 char bits[64]; 1327 printf("be_tcvr_init: MGMTPAL=%s\n", 1328 bitmask_snprintf(v, MGMT_PAL_BITS, bits, sizeof(bits))); 1329 } 1330 #endif 1331 if (v & MGMT_PAL_EXT_MDIO) { 1332 sc->sc_conf |= BE_CONF_MII; 1333 /*sc->sc_tcvr_type = BE_TCVR_EXTERNAL;*/ 1334 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, 1335 ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | 1336 TCVR_PAL_LTENABLE)); 1337 1338 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1339 } 1340 else if (v & MGMT_PAL_INT_MDIO) { 1341 /*sc->sc_tcvr_type = BE_TCVR_INTERNAL;*/ 1342 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, 1343 ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | 1344 TCVR_PAL_LTENABLE | TCVR_PAL_SERIAL)); 1345 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1346 } 1347 else { 1348 printf("%s: no internal or external transceiver found.\n", 1349 sc->sc_dev.dv_xname); 1350 } 1351 } 1352 1353 1354 static __inline__ int 1355 be_tcvr_read_bit(sc, phy) 1356 struct be_softc *sc; 1357 int phy; 1358 { 1359 bus_space_tag_t t = sc->sc_bustag; 1360 bus_space_handle_t tr = sc->sc_tr; 1361 int ret; 1362 1363 if (phy == BE_PHY_INTERNAL) { 1364 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1365 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1366 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1367 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1368 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1369 DELAY(20); 1370 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1371 MGMT_PAL_INT_MDIO) >> 3; 1372 } else { 1373 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1374 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1375 DELAY(20); 1376 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1377 MGMT_PAL_EXT_MDIO) >> 2; 1378 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1379 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1380 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1381 } 1382 1383 return (ret); 1384 } 1385 1386 static __inline__ void 1387 be_tcvr_write_bit(sc, phy, bit) 1388 struct be_softc *sc; 1389 int phy; 1390 int bit; 1391 { 1392 bus_space_tag_t t = sc->sc_bustag; 1393 bus_space_handle_t tr = sc->sc_tr; 1394 1395 if (phy == BE_PHY_INTERNAL) { 1396 bit = ((bit & 1) << 3) | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1397 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit); 1398 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1399 1400 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit | MGMT_PAL_DCLOCK); 1401 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1402 } else { 1403 bit = ((bit & 1) << 2) | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1404 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit); 1405 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1406 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, bit | MGMT_PAL_DCLOCK); 1407 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1408 } 1409 } 1410 1411 static __inline__ void 1412 be_mii_sendbits(sc, phy, data, nbits) 1413 struct be_softc *sc; 1414 int phy; 1415 u_int32_t data; 1416 int nbits; 1417 { 1418 int i; 1419 1420 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1421 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1422 } 1423 } 1424 1425 static __inline__ int 1426 be_mii_readreg1(self, phy, reg) 1427 struct device *self; 1428 int phy, reg; 1429 { 1430 struct be_softc *sc = (struct be_softc *)self; 1431 int val = 0, i; 1432 1433 /* 1434 * Read the PHY register by manually driving the MII control lines. 1435 */ 1436 1437 be_mii_sync(sc); 1438 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1439 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1440 be_mii_sendbits(sc, phy, phy, 5); 1441 be_mii_sendbits(sc, phy, reg, 5); 1442 1443 (void) be_tcvr_read_bit(sc, phy); 1444 (void) be_tcvr_read_bit(sc, phy); 1445 1446 for (i = 15; i >= 0; i--) 1447 val |= (be_tcvr_read_bit(sc, phy) << i); 1448 1449 (void) be_tcvr_read_bit(sc, phy); 1450 (void) be_tcvr_read_bit(sc, phy); 1451 (void) be_tcvr_read_bit(sc, phy); 1452 1453 #if 0 1454 if (phy == BE_PHY_INTERNAL) { 1455 /* 1456 * Feign capabilities for imaginary MII. 1457 */ 1458 if (reg == MII_BMSR) 1459 val |= BMSR_100TXFDX | BMSR_100TXHDX | 1460 BMSR_10TFDX | BMSR_10THDX | BMSR_ANEG; 1461 1462 if (reg == MII_BMCR) 1463 ; 1464 } 1465 #endif 1466 return (val); 1467 } 1468 1469 int 1470 be_mii_readreg(self, phy, reg) 1471 struct device *self; 1472 int phy, reg; 1473 { 1474 if (phy == BE_PHY_INTERNAL) 1475 return (be_mii_readreg1(self, BE_PHY_INTERNAL, reg)); 1476 else if (phy == BE_PHY_EXTERNAL) 1477 return (be_mii_readreg1(self, BE_PHY_EXTERNAL, reg)); 1478 else 1479 return (0); 1480 } 1481 1482 void 1483 be_mii_writereg(self, phy, reg, val) 1484 struct device *self; 1485 int phy, reg, val; 1486 { 1487 struct be_softc *sc = (struct be_softc *)self; 1488 int i; 1489 1490 /* 1491 * Write the PHY register by manually driving the MII control lines. 1492 */ 1493 be_mii_sync(sc); 1494 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1495 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1496 be_mii_sendbits(sc, phy, phy, 5); 1497 be_mii_sendbits(sc, phy, reg, 5); 1498 1499 be_tcvr_write_bit(sc, phy, 1); 1500 be_tcvr_write_bit(sc, phy, 0); 1501 1502 for (i = 15; i >= 0; i--) 1503 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1504 } 1505 1506 int 1507 be_mii_reset(sc, phy) 1508 struct be_softc *sc; 1509 int phy; 1510 { 1511 int n; 1512 1513 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1514 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1515 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1516 1517 for (n = 16; n >= 0; n--) { 1518 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1519 if ((bmcr & BMCR_RESET) == 0) 1520 break; 1521 DELAY(20); 1522 } 1523 if (n == 0) { 1524 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1525 return (EIO); 1526 } 1527 return (0); 1528 } 1529 1530 void 1531 be_statchg(self) 1532 struct device *self; 1533 { 1534 struct be_softc *sc = (struct be_softc *)self; 1535 1536 printf("be_statchg: media_active=%x\n", sc->sc_mii.mii_media_active); 1537 } 1538 1539 void 1540 be_tick(arg) 1541 void *arg; 1542 { 1543 struct be_softc *sc = arg; 1544 int s = splnet(); 1545 1546 if ((sc->sc_conf & BE_CONF_MII) != 0) 1547 mii_tick(&sc->sc_mii); 1548 else 1549 be_internal_phy_auto(sc); 1550 1551 splx(s); 1552 timeout(be_tick, sc, hz); 1553 } 1554 1555 void 1556 be_internal_phy_auto(sc) 1557 struct be_softc *sc; 1558 { 1559 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1560 int bmcr, bmsr; 1561 1562 /* 1563 * Check link status; if we don't have a link, try another 1564 * speed. We can't detect duplex mode, so half-duplex is 1565 * what we have to settle for. 1566 */ 1567 1568 /* Only used for automatic media selection */ 1569 if (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media) != IFM_AUTO) 1570 return; 1571 1572 /* Don't bother if interface isn't up */ 1573 if ((ifp->if_flags & IFF_UP) == 0) 1574 return; 1575 1576 /* Read twice in case the register is latched */ 1577 bmsr = be_mii_readreg1((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1578 be_mii_readreg1((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1579 1580 if ((bmsr & BMSR_LINK) != 0) { 1581 /* We have a carrier */ 1582 return; 1583 } 1584 1585 bmcr = be_mii_readreg1((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1586 /* Just flip the fast speed bit */ 1587 bmcr ^= BMCR_S100; 1588 be_mii_writereg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1589 } 1590 1591 /* 1592 * Get current media settings. 1593 */ 1594 void 1595 be_ifmedia_sts(ifp, ifmr) 1596 struct ifnet *ifp; 1597 struct ifmediareq *ifmr; 1598 { 1599 struct be_softc *sc = ifp->if_softc; 1600 int bmcr, bmsr; 1601 1602 if ((sc->sc_conf & BE_CONF_MII) != 0) { 1603 mii_pollstat(&sc->sc_mii); 1604 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1605 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1606 return; 1607 } 1608 1609 /* 1610 * Internal transceiver; do the work here. 1611 */ 1612 bmcr = be_mii_readreg1((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1613 1614 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1615 case (BMCR_S100 | BMCR_FDX): 1616 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1617 break; 1618 case BMCR_S100: 1619 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1620 break; 1621 case BMCR_FDX: 1622 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1623 break; 1624 case 0: 1625 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1626 break; 1627 } 1628 1629 /* Read twice in case the register is latched */ 1630 bmsr = be_mii_readreg1((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1631 be_mii_readreg1((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1632 if (bmsr & BMSR_LINK) 1633 ifmr->ifm_status |= IFM_AVALID | IFM_ACTIVE; 1634 else { 1635 ifmr->ifm_status |= IFM_AVALID; 1636 ifmr->ifm_status &= ~IFM_ACTIVE; 1637 } 1638 } 1639 1640 /* 1641 * Set media options. 1642 */ 1643 int 1644 be_ifmedia_upd(ifp) 1645 struct ifnet *ifp; 1646 { 1647 struct be_softc *sc = ifp->if_softc; 1648 struct ifmedia *ifm = &sc->sc_media; 1649 int newmedia = ifm->ifm_media; 1650 int n, error, phy, bmcr; 1651 char *speed, *mode; 1652 u_int32_t v; 1653 bus_space_tag_t t = sc->sc_bustag; 1654 bus_space_handle_t br = sc->sc_br; 1655 1656 if (IFM_TYPE(newmedia) != IFM_ETHER) 1657 return (EINVAL); 1658 1659 if ((sc->sc_conf & BE_CONF_MII) != 0) { 1660 int error; 1661 1662 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1663 return (error); 1664 1665 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1666 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1667 v |= BE_BR_TXCFG_FULLDPLX; 1668 else 1669 v &= ~BE_BR_TXCFG_FULLDPLX; 1670 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1671 1672 return (0); 1673 } 1674 1675 /* 1676 * The rest of this routine is devoted to the 1677 * not-quite-a-phy internal transceiver case. 1678 */ 1679 phy = BE_PHY_INTERNAL; 1680 1681 /* Why must we reset the device? */ 1682 if ((error = be_mii_reset(sc, phy)) != 0) 1683 return (error); 1684 1685 bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1686 1687 if (IFM_SUBTYPE(newmedia) == IFM_100_TX) { 1688 bmcr |= BMCR_S100; 1689 speed = "100baseTX"; 1690 } else if (IFM_SUBTYPE(newmedia) == IFM_10_T) { 1691 bmcr &= ~BMCR_S100; 1692 speed = "10baseT"; 1693 } else { 1694 speed = "auto sense"; 1695 } 1696 1697 printf("%s: selecting %s", sc->sc_dev.dv_xname, speed); 1698 1699 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1700 if ((IFM_OPTIONS(newmedia) & IFM_FDX) != 0) { 1701 bmcr |= BMCR_FDX; 1702 v |= BE_BR_TXCFG_FULLDPLX; 1703 mode = "full"; 1704 } else { 1705 bmcr &= ~BMCR_FDX; 1706 v &= ~BE_BR_TXCFG_FULLDPLX; 1707 mode = "half"; 1708 } 1709 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1710 printf(" %s-duplex\n", mode); 1711 1712 /* Select the new mode and take out of isolation */ 1713 be_mii_writereg((struct device *)sc, phy, MII_BMCR, bmcr & ~BMCR_ISO); 1714 1715 for (n = 32; n >= 0; n--) { 1716 bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1717 if ((bmcr & BMCR_ISO) == 0) 1718 break; 1719 DELAY(20); 1720 } 1721 if (n == 0) { 1722 printf("%s: bmcr unisolate failed\n", sc->sc_dev.dv_xname); 1723 return (EIO); 1724 } 1725 1726 return (0); 1727 } 1728
Indexes created Tue Sep 30 11:09:46 GMT 2025