be.c revision 1.13
1 /* $NetBSD: be.c,v 1.13 1999/12/23 16:39:56 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/kernel.h> 77 #include <sys/errno.h> 78 #include <sys/ioctl.h> 79 #include <sys/mbuf.h> 80 #include <sys/socket.h> 81 #include <sys/syslog.h> 82 #include <sys/device.h> 83 #include <sys/malloc.h> 84 #if NRND > 0 85 #include <sys/rnd.h> 86 #endif 87 88 #include <net/if.h> 89 #include <net/if_dl.h> 90 #include <net/if_types.h> 91 #include <net/netisr.h> 92 #include <net/if_media.h> 93 #include <net/if_ether.h> 94 95 #ifdef INET 96 #include <netinet/in.h> 97 #include <netinet/if_inarp.h> 98 #include <netinet/in_systm.h> 99 #include <netinet/in_var.h> 100 #include <netinet/ip.h> 101 #endif 102 103 #ifdef NS 104 #include <netns/ns.h> 105 #include <netns/ns_if.h> 106 #endif 107 108 #if NBPFILTER > 0 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 #endif 112 113 #include <machine/autoconf.h> 114 #include <machine/cpu.h> 115 116 #include <dev/sbus/sbusvar.h> 117 118 #include <dev/mii/mii.h> 119 #include <dev/mii/miivar.h> 120 121 #include <dev/sbus/qecreg.h> 122 #include <dev/sbus/qecvar.h> 123 #include <dev/sbus/bereg.h> 124 125 struct be_softc { 126 struct device sc_dev; 127 struct sbusdev sc_sd; /* sbus device */ 128 bus_space_tag_t sc_bustag; /* bus & dma tags */ 129 bus_dma_tag_t sc_dmatag; 130 struct ethercom sc_ethercom; 131 /*struct ifmedia sc_ifmedia; -* interface media */ 132 struct mii_data sc_mii; /* MII media control */ 133 #define sc_media sc_mii.mii_media/* shorthand */ 134 int sc_phys[2]; /* MII instance -> phy */ 135 136 /* 137 * Some `mii_softc' items we need to emulate MII operation 138 * for our internal transceiver. 139 */ 140 int sc_mii_inst; /* instance of internal phy */ 141 int sc_mii_active; /* currently active medium */ 142 int sc_mii_ticks; /* tick counter */ 143 int sc_mii_flags; /* phy status flags */ 144 #define MIIF_HAVELINK 0x04000000 145 int sc_intphy_curspeed; /* Established link speed */ 146 147 struct qec_softc *sc_qec; /* QEC parent */ 148 149 bus_space_handle_t sc_qr; /* QEC registers */ 150 bus_space_handle_t sc_br; /* BE registers */ 151 bus_space_handle_t sc_cr; /* channel registers */ 152 bus_space_handle_t sc_tr; /* transceiver registers */ 153 154 u_int sc_rev; 155 156 int sc_channel; /* channel number */ 157 int sc_burst; 158 159 struct qec_ring sc_rb; /* Packet Ring Buffer */ 160 161 /* MAC address */ 162 u_int8_t sc_enaddr[6]; 163 }; 164 165 int bematch __P((struct device *, struct cfdata *, void *)); 166 void beattach __P((struct device *, struct device *, void *)); 167 168 void beinit __P((struct be_softc *)); 169 void bestart __P((struct ifnet *)); 170 void bestop __P((struct be_softc *)); 171 void bewatchdog __P((struct ifnet *)); 172 int beioctl __P((struct ifnet *, u_long, caddr_t)); 173 void bereset __P((struct be_softc *)); 174 175 int beintr __P((void *)); 176 int berint __P((struct be_softc *)); 177 int betint __P((struct be_softc *)); 178 int beqint __P((struct be_softc *, u_int32_t)); 179 int beeint __P((struct be_softc *, u_int32_t)); 180 181 static void be_read __P((struct be_softc *, int, int)); 182 static int be_put __P((struct be_softc *, int, struct mbuf *)); 183 static struct mbuf *be_get __P((struct be_softc *, int, int)); 184 185 void be_pal_gate __P((struct be_softc *, int)); 186 187 /* ifmedia callbacks */ 188 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 189 int be_ifmedia_upd __P((struct ifnet *)); 190 191 void be_mcreset __P((struct be_softc *)); 192 193 /* MII methods & callbacks */ 194 static int be_mii_readreg __P((struct device *, int, int)); 195 static void be_mii_writereg __P((struct device *, int, int, int)); 196 static void be_mii_statchg __P((struct device *)); 197 198 /* MII helpers */ 199 static void be_mii_sync __P((struct be_softc *)); 200 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 201 static int be_mii_reset __P((struct be_softc *, int)); 202 static int be_tcvr_read_bit __P((struct be_softc *, int)); 203 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 204 205 void be_tick __P((void *)); 206 void be_intphy_auto __P((struct be_softc *)); 207 void be_intphy_status __P((struct be_softc *)); 208 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 209 210 211 struct cfattach be_ca = { 212 sizeof(struct be_softc), bematch, beattach 213 }; 214 215 int 216 bematch(parent, cf, aux) 217 struct device *parent; 218 struct cfdata *cf; 219 void *aux; 220 { 221 struct sbus_attach_args *sa = aux; 222 223 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 224 } 225 226 void 227 beattach(parent, self, aux) 228 struct device *parent, *self; 229 void *aux; 230 { 231 struct sbus_attach_args *sa = aux; 232 struct qec_softc *qec = (struct qec_softc *)parent; 233 struct be_softc *sc = (struct be_softc *)self; 234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 235 struct mii_data *mii = &sc->sc_mii; 236 struct mii_softc *child; 237 int instance; 238 int node = sa->sa_node; 239 bus_dma_segment_t seg; 240 bus_size_t size; 241 int rseg, error; 242 u_int32_t v; 243 extern void myetheraddr __P((u_char *)); 244 245 if (sa->sa_nreg < 3) { 246 printf("%s: only %d register sets\n", 247 self->dv_xname, sa->sa_nreg); 248 return; 249 } 250 251 if (bus_space_map2(sa->sa_bustag, 252 (bus_type_t)sa->sa_reg[0].sbr_slot, 253 (bus_addr_t)sa->sa_reg[0].sbr_offset, 254 (bus_size_t)sa->sa_reg[0].sbr_size, 255 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 256 printf("beattach: cannot map registers\n"); 257 return; 258 } 259 260 if (bus_space_map2(sa->sa_bustag, 261 (bus_type_t)sa->sa_reg[1].sbr_slot, 262 (bus_addr_t)sa->sa_reg[1].sbr_offset, 263 (bus_size_t)sa->sa_reg[1].sbr_size, 264 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 265 printf("beattach: cannot map registers\n"); 266 return; 267 } 268 269 if (bus_space_map2(sa->sa_bustag, 270 (bus_type_t)sa->sa_reg[2].sbr_slot, 271 (bus_addr_t)sa->sa_reg[2].sbr_offset, 272 (bus_size_t)sa->sa_reg[2].sbr_size, 273 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 274 printf("beattach: cannot map registers\n"); 275 return; 276 } 277 278 sc->sc_qec = qec; 279 sc->sc_qr = qec->sc_regs; 280 281 sc->sc_rev = getpropint(node, "board-version", -1); 282 printf(" rev %x", sc->sc_rev); 283 284 bestop(sc); 285 286 sc->sc_channel = getpropint(node, "channel#", -1); 287 if (sc->sc_channel == -1) 288 sc->sc_channel = 0; 289 290 sc->sc_burst = getpropint(node, "burst-sizes", -1); 291 if (sc->sc_burst == -1) 292 sc->sc_burst = qec->sc_burst; 293 294 /* Clamp at parent's burst sizes */ 295 sc->sc_burst &= qec->sc_burst; 296 297 /* Establish interrupt handler */ 298 if (sa->sa_nintr) 299 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 300 0, beintr, sc); 301 302 myetheraddr(sc->sc_enaddr); 303 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 304 305 /* 306 * Allocate descriptor ring and buffers. 307 */ 308 309 /* for now, allocate as many bufs as there are ring descriptors */ 310 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 311 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 312 313 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 314 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 315 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 316 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 317 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 318 NBPG, 0, 319 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 320 printf("%s: DMA buffer alloc error %d\n", 321 self->dv_xname, error); 322 return; 323 } 324 sc->sc_rb.rb_dmabase = seg.ds_addr; 325 326 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 327 &sc->sc_rb.rb_membase, 328 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 329 printf("%s: DMA buffer map error %d\n", 330 self->dv_xname, error); 331 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 332 return; 333 } 334 335 /* 336 * Initialize our media structures and MII info. 337 */ 338 mii->mii_ifp = ifp; 339 mii->mii_readreg = be_mii_readreg; 340 mii->mii_writereg = be_mii_writereg; 341 mii->mii_statchg = be_mii_statchg; 342 343 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 344 345 /* 346 * Initialize transceiver and determine which PHY connection to use. 347 */ 348 be_mii_sync(sc); 349 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 350 351 instance = 0; 352 353 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 354 355 mii_phy_probe(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 356 MII_OFFSET_ANY); 357 358 child = LIST_FIRST(&mii->mii_phys); 359 if (child == NULL) { 360 /* No PHY attached */ 361 ifmedia_add(&sc->sc_media, 362 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 363 0, NULL); 364 ifmedia_set(&sc->sc_media, 365 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 366 } else { 367 /* 368 * Note: we support just one PHY on the external 369 * MII connector. 370 */ 371 #ifdef DIAGNOSTIC 372 if (LIST_NEXT(child, mii_list) != NULL) { 373 printf("%s: spurious MII device %s attached\n", 374 sc->sc_dev.dv_xname, 375 child->mii_dev.dv_xname); 376 } 377 #endif 378 if (child->mii_phy != BE_PHY_EXTERNAL || 379 child->mii_inst > 0) { 380 printf("%s: cannot accomodate MII device %s" 381 " at phy %d, instance %d\n", 382 sc->sc_dev.dv_xname, 383 child->mii_dev.dv_xname, 384 child->mii_phy, child->mii_inst); 385 } else { 386 sc->sc_phys[instance] = child->mii_phy; 387 } 388 389 /* 390 * XXX - we can really do the following ONLY if the 391 * phy indeed has the auto negotiation capability!! 392 */ 393 ifmedia_set(&sc->sc_media, 394 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 395 396 /* Mark our current media setting */ 397 be_pal_gate(sc, BE_PHY_EXTERNAL); 398 instance++; 399 } 400 401 } 402 403 if ((v & MGMT_PAL_INT_MDIO) != 0) { 404 /* 405 * The be internal phy looks vaguely like MII hardware, 406 * but not enough to be able to use the MII device 407 * layer. Hence, we have to take care of media selection 408 * ourselves. 409 */ 410 411 sc->sc_mii_inst = instance; 412 sc->sc_phys[instance] = BE_PHY_INTERNAL; 413 414 /* Use `ifm_data' to store BMCR bits */ 415 ifmedia_add(&sc->sc_media, 416 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 417 0, NULL); 418 ifmedia_add(&sc->sc_media, 419 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 420 BMCR_S100, NULL); 421 ifmedia_add(&sc->sc_media, 422 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 423 0, NULL); 424 425 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 426 self->dv_xname); 427 428 be_mii_reset(sc, BE_PHY_INTERNAL); 429 /* Only set default medium here if there's no external PHY */ 430 if (instance == 0) { 431 be_pal_gate(sc, BE_PHY_INTERNAL); 432 ifmedia_set(&sc->sc_media, 433 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 434 } else 435 be_mii_writereg((void *)sc, 436 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 437 } 438 439 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 440 ifp->if_softc = sc; 441 ifp->if_start = bestart; 442 ifp->if_ioctl = beioctl; 443 ifp->if_watchdog = bewatchdog; 444 ifp->if_flags = 445 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 446 447 /* Attach the interface. */ 448 if_attach(ifp); 449 ether_ifattach(ifp, sc->sc_enaddr); 450 451 #if NBPFILTER > 0 452 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 453 #endif 454 } 455 456 457 /* 458 * Routine to copy from mbuf chain to transmit buffer in 459 * network buffer memory. 460 */ 461 static __inline__ int 462 be_put(sc, idx, m) 463 struct be_softc *sc; 464 int idx; 465 struct mbuf *m; 466 { 467 struct mbuf *n; 468 int len, tlen = 0, boff = 0; 469 caddr_t bp; 470 471 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 472 473 for (; m; m = n) { 474 len = m->m_len; 475 if (len == 0) { 476 MFREE(m, n); 477 continue; 478 } 479 bcopy(mtod(m, caddr_t), bp+boff, len); 480 boff += len; 481 tlen += len; 482 MFREE(m, n); 483 } 484 return (tlen); 485 } 486 487 /* 488 * Pull data off an interface. 489 * Len is the length of data, with local net header stripped. 490 * We copy the data into mbufs. When full cluster sized units are present, 491 * we copy into clusters. 492 */ 493 static __inline__ struct mbuf * 494 be_get(sc, idx, totlen) 495 struct be_softc *sc; 496 int idx, totlen; 497 { 498 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 499 struct mbuf *m; 500 struct mbuf *top, **mp; 501 int len, pad, boff = 0; 502 caddr_t bp; 503 504 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 505 506 MGETHDR(m, M_DONTWAIT, MT_DATA); 507 if (m == NULL) 508 return (NULL); 509 m->m_pkthdr.rcvif = ifp; 510 m->m_pkthdr.len = totlen; 511 512 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 513 m->m_data += pad; 514 len = MHLEN - pad; 515 top = NULL; 516 mp = ⊤ 517 518 while (totlen > 0) { 519 if (top) { 520 MGET(m, M_DONTWAIT, MT_DATA); 521 if (m == NULL) { 522 m_freem(top); 523 return (NULL); 524 } 525 len = MLEN; 526 } 527 if (top && totlen >= MINCLSIZE) { 528 MCLGET(m, M_DONTWAIT); 529 if (m->m_flags & M_EXT) 530 len = MCLBYTES; 531 } 532 m->m_len = len = min(totlen, len); 533 bcopy(bp + boff, mtod(m, caddr_t), len); 534 boff += len; 535 totlen -= len; 536 *mp = m; 537 mp = &m->m_next; 538 } 539 540 return (top); 541 } 542 543 /* 544 * Pass a packet to the higher levels. 545 */ 546 static __inline__ void 547 be_read(sc, idx, len) 548 struct be_softc *sc; 549 int idx, len; 550 { 551 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 552 struct mbuf *m; 553 554 if (len <= sizeof(struct ether_header) || 555 len > ETHERMTU + sizeof(struct ether_header)) { 556 557 printf("%s: invalid packet size %d; dropping\n", 558 ifp->if_xname, len); 559 560 ifp->if_ierrors++; 561 return; 562 } 563 564 /* 565 * Pull packet off interface. 566 */ 567 m = be_get(sc, idx, len); 568 if (m == NULL) { 569 ifp->if_ierrors++; 570 return; 571 } 572 ifp->if_ipackets++; 573 574 #if NBPFILTER > 0 575 /* 576 * Check if there's a BPF listener on this interface. 577 * If so, hand off the raw packet to BPF. 578 */ 579 if (ifp->if_bpf) 580 bpf_mtap(ifp->if_bpf, m); 581 #endif 582 /* Pass the packet up. */ 583 (*ifp->if_input)(ifp, m); 584 } 585 586 /* 587 * Start output on interface. 588 * We make two assumptions here: 589 * 1) that the current priority is set to splnet _before_ this code 590 * is called *and* is returned to the appropriate priority after 591 * return 592 * 2) that the IFF_OACTIVE flag is checked before this code is called 593 * (i.e. that the output part of the interface is idle) 594 */ 595 void 596 bestart(ifp) 597 struct ifnet *ifp; 598 { 599 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 600 struct qec_xd *txd = sc->sc_rb.rb_txd; 601 struct mbuf *m; 602 unsigned int bix, len; 603 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 604 605 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 606 return; 607 608 bix = sc->sc_rb.rb_tdhead; 609 610 for (;;) { 611 IF_DEQUEUE(&ifp->if_snd, m); 612 if (m == 0) 613 break; 614 615 #if NBPFILTER > 0 616 /* 617 * If BPF is listening on this interface, let it see the 618 * packet before we commit it to the wire. 619 */ 620 if (ifp->if_bpf) 621 bpf_mtap(ifp->if_bpf, m); 622 #endif 623 624 /* 625 * Copy the mbuf chain into the transmit buffer. 626 */ 627 len = be_put(sc, bix, m); 628 629 /* 630 * Initialize transmit registers and start transmission 631 */ 632 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 633 (len & QEC_XD_LENGTH); 634 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 635 BE_CR_CTRL_TWAKEUP); 636 637 if (++bix == QEC_XD_RING_MAXSIZE) 638 bix = 0; 639 640 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 641 ifp->if_flags |= IFF_OACTIVE; 642 break; 643 } 644 } 645 646 sc->sc_rb.rb_tdhead = bix; 647 } 648 649 void 650 bestop(sc) 651 struct be_softc *sc; 652 { 653 int n; 654 bus_space_tag_t t = sc->sc_bustag; 655 bus_space_handle_t br = sc->sc_br; 656 657 untimeout(be_tick, sc); 658 659 /* Down the MII. */ 660 mii_down(&sc->sc_mii); 661 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 662 663 /* Stop the transmitter */ 664 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 665 for (n = 32; n > 0; n--) { 666 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 667 break; 668 DELAY(20); 669 } 670 671 /* Stop the receiver */ 672 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 673 for (n = 32; n > 0; n--) { 674 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 675 break; 676 DELAY(20); 677 } 678 } 679 680 /* 681 * Reset interface. 682 */ 683 void 684 bereset(sc) 685 struct be_softc *sc; 686 { 687 int s; 688 689 s = splnet(); 690 bestop(sc); 691 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 692 beinit(sc); 693 splx(s); 694 } 695 696 void 697 bewatchdog(ifp) 698 struct ifnet *ifp; 699 { 700 struct be_softc *sc = ifp->if_softc; 701 702 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 703 ++sc->sc_ethercom.ec_if.if_oerrors; 704 705 bereset(sc); 706 } 707 708 int 709 beintr(v) 710 void *v; 711 { 712 struct be_softc *sc = (struct be_softc *)v; 713 bus_space_tag_t t = sc->sc_bustag; 714 u_int32_t whyq, whyb, whyc; 715 int r = 0; 716 717 /* Read QEC status, channel status and BE status */ 718 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 719 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 720 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 721 722 if (whyq & QEC_STAT_BM) 723 r |= beeint(sc, whyb); 724 725 if (whyq & QEC_STAT_ER) 726 r |= beqint(sc, whyc); 727 728 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 729 r |= betint(sc); 730 731 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 732 r |= berint(sc); 733 734 return (r); 735 } 736 737 /* 738 * QEC Interrupt. 739 */ 740 int 741 beqint(sc, why) 742 struct be_softc *sc; 743 u_int32_t why; 744 { 745 int r = 0, rst = 0; 746 747 if (why & BE_CR_STAT_TXIRQ) 748 r |= 1; 749 if (why & BE_CR_STAT_RXIRQ) 750 r |= 1; 751 752 if (why & BE_CR_STAT_BERROR) { 753 r |= 1; 754 rst = 1; 755 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 756 } 757 758 if (why & BE_CR_STAT_TXDERR) { 759 r |= 1; 760 rst = 1; 761 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 762 } 763 764 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 765 r |= 1; 766 rst = 1; 767 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 768 if (why & BE_CR_STAT_TXLERR) 769 printf("Late "); 770 if (why & BE_CR_STAT_TXPERR) 771 printf("Parity "); 772 if (why & BE_CR_STAT_TXSERR) 773 printf("Generic "); 774 printf(")\n"); 775 } 776 777 if (why & BE_CR_STAT_RXDROP) { 778 r |= 1; 779 rst = 1; 780 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 781 } 782 783 if (why & BE_CR_STAT_RXSMALL) { 784 r |= 1; 785 rst = 1; 786 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 787 } 788 789 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 790 r |= 1; 791 rst = 1; 792 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 793 if (why & BE_CR_STAT_RXLERR) 794 printf("Late "); 795 if (why & BE_CR_STAT_RXPERR) 796 printf("Parity "); 797 if (why & BE_CR_STAT_RXSERR) 798 printf("Generic "); 799 printf(")\n"); 800 } 801 802 if (!r) { 803 rst = 1; 804 printf("%s: unexpected error interrupt %08x\n", 805 sc->sc_dev.dv_xname, why); 806 } 807 808 if (rst) { 809 printf("%s: resetting\n", sc->sc_dev.dv_xname); 810 bereset(sc); 811 } 812 813 return (r); 814 } 815 816 /* 817 * Error interrupt. 818 */ 819 int 820 beeint(sc, why) 821 struct be_softc *sc; 822 u_int32_t why; 823 { 824 int r = 0, rst = 0; 825 826 if (why & BE_BR_STAT_RFIFOVF) { 827 r |= 1; 828 rst = 1; 829 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 830 } 831 if (why & BE_BR_STAT_TFIFO_UND) { 832 r |= 1; 833 rst = 1; 834 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 835 } 836 if (why & BE_BR_STAT_MAXPKTERR) { 837 r |= 1; 838 rst = 1; 839 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 840 } 841 842 if (!r) { 843 rst = 1; 844 printf("%s: unexpected error interrupt %08x\n", 845 sc->sc_dev.dv_xname, why); 846 } 847 848 if (rst) { 849 printf("%s: resetting\n", sc->sc_dev.dv_xname); 850 bereset(sc); 851 } 852 853 return (r); 854 } 855 856 /* 857 * Transmit interrupt. 858 */ 859 int 860 betint(sc) 861 struct be_softc *sc; 862 { 863 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 864 bus_space_tag_t t = sc->sc_bustag; 865 bus_space_handle_t br = sc->sc_br; 866 unsigned int bix, txflags; 867 868 /* 869 * Unload collision counters 870 */ 871 ifp->if_collisions += 872 bus_space_read_4(t, br, BE_BRI_NCCNT) + 873 bus_space_read_4(t, br, BE_BRI_FCCNT) + 874 bus_space_read_4(t, br, BE_BRI_EXCNT) + 875 bus_space_read_4(t, br, BE_BRI_LTCNT); 876 877 /* 878 * the clear the hardware counters 879 */ 880 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 881 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 882 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 883 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 884 885 bix = sc->sc_rb.rb_tdtail; 886 887 for (;;) { 888 if (sc->sc_rb.rb_td_nbusy <= 0) 889 break; 890 891 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 892 893 if (txflags & QEC_XD_OWN) 894 break; 895 896 ifp->if_flags &= ~IFF_OACTIVE; 897 ifp->if_opackets++; 898 899 if (++bix == QEC_XD_RING_MAXSIZE) 900 bix = 0; 901 902 --sc->sc_rb.rb_td_nbusy; 903 } 904 905 sc->sc_rb.rb_tdtail = bix; 906 907 bestart(ifp); 908 909 if (sc->sc_rb.rb_td_nbusy == 0) 910 ifp->if_timer = 0; 911 912 return (1); 913 } 914 915 /* 916 * Receive interrupt. 917 */ 918 int 919 berint(sc) 920 struct be_softc *sc; 921 { 922 struct qec_xd *xd = sc->sc_rb.rb_rxd; 923 unsigned int bix, len; 924 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 925 926 bix = sc->sc_rb.rb_rdtail; 927 928 /* 929 * Process all buffers with valid data. 930 */ 931 for (;;) { 932 len = xd[bix].xd_flags; 933 if (len & QEC_XD_OWN) 934 break; 935 936 len &= QEC_XD_LENGTH; 937 be_read(sc, bix, len); 938 939 /* ... */ 940 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 941 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 942 943 if (++bix == QEC_XD_RING_MAXSIZE) 944 bix = 0; 945 } 946 947 sc->sc_rb.rb_rdtail = bix; 948 949 return (1); 950 } 951 952 int 953 beioctl(ifp, cmd, data) 954 struct ifnet *ifp; 955 u_long cmd; 956 caddr_t data; 957 { 958 struct be_softc *sc = ifp->if_softc; 959 struct ifaddr *ifa = (struct ifaddr *)data; 960 struct ifreq *ifr = (struct ifreq *)data; 961 int s, error = 0; 962 963 s = splnet(); 964 965 switch (cmd) { 966 case SIOCSIFADDR: 967 ifp->if_flags |= IFF_UP; 968 switch (ifa->ifa_addr->sa_family) { 969 #ifdef INET 970 case AF_INET: 971 beinit(sc); 972 arp_ifinit(ifp, ifa); 973 break; 974 #endif /* INET */ 975 #ifdef NS 976 case AF_NS: 977 { 978 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 979 980 if (ns_nullhost(*ina)) 981 ina->x_host = 982 *(union ns_host *)LLADDR(ifp->if_sadl); 983 else 984 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 985 sizeof(sc->sc_enaddr)); 986 /* Set new address. */ 987 beinit(sc); 988 break; 989 } 990 #endif /* NS */ 991 default: 992 beinit(sc); 993 break; 994 } 995 break; 996 997 case SIOCSIFFLAGS: 998 if ((ifp->if_flags & IFF_UP) == 0 && 999 (ifp->if_flags & IFF_RUNNING) != 0) { 1000 /* 1001 * If interface is marked down and it is running, then 1002 * stop it. 1003 */ 1004 bestop(sc); 1005 ifp->if_flags &= ~IFF_RUNNING; 1006 } else if ((ifp->if_flags & IFF_UP) != 0 && 1007 (ifp->if_flags & IFF_RUNNING) == 0) { 1008 /* 1009 * If interface is marked up and it is stopped, then 1010 * start it. 1011 */ 1012 beinit(sc); 1013 } else { 1014 /* 1015 * Reset the interface to pick up changes in any other 1016 * flags that affect hardware registers. 1017 */ 1018 bestop(sc); 1019 beinit(sc); 1020 } 1021 #ifdef BEDEBUG 1022 if (ifp->if_flags & IFF_DEBUG) 1023 sc->sc_debug = 1; 1024 else 1025 sc->sc_debug = 0; 1026 #endif 1027 break; 1028 1029 case SIOCADDMULTI: 1030 case SIOCDELMULTI: 1031 error = (cmd == SIOCADDMULTI) ? 1032 ether_addmulti(ifr, &sc->sc_ethercom): 1033 ether_delmulti(ifr, &sc->sc_ethercom); 1034 1035 if (error == ENETRESET) { 1036 /* 1037 * Multicast list has changed; set the hardware filter 1038 * accordingly. 1039 */ 1040 be_mcreset(sc); 1041 error = 0; 1042 } 1043 break; 1044 case SIOCGIFMEDIA: 1045 case SIOCSIFMEDIA: 1046 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1047 break; 1048 default: 1049 error = EINVAL; 1050 break; 1051 } 1052 splx(s); 1053 return (error); 1054 } 1055 1056 1057 void 1058 beinit(sc) 1059 struct be_softc *sc; 1060 { 1061 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1062 bus_space_tag_t t = sc->sc_bustag; 1063 bus_space_handle_t br = sc->sc_br; 1064 bus_space_handle_t cr = sc->sc_cr; 1065 struct qec_softc *qec = sc->sc_qec; 1066 u_int32_t qecaddr; 1067 u_int8_t *ea; 1068 int s; 1069 1070 s = splimp(); 1071 1072 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1073 1074 bestop(sc); 1075 1076 ea = sc->sc_enaddr; 1077 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1078 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1079 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1080 1081 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1082 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1083 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1084 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1085 1086 be_mcreset(sc); 1087 1088 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1089 1090 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1091 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1092 1093 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1094 1095 /* 1096 * Turn off counter expiration interrupts as well as 1097 * 'gotframe' and 'sentframe' 1098 */ 1099 bus_space_write_4(t, br, BE_BRI_IMASK, 1100 BE_BR_IMASK_GOTFRAME | 1101 BE_BR_IMASK_RCNTEXP | 1102 BE_BR_IMASK_ACNTEXP | 1103 BE_BR_IMASK_CCNTEXP | 1104 BE_BR_IMASK_LCNTEXP | 1105 BE_BR_IMASK_CVCNTEXP | 1106 BE_BR_IMASK_SENTFRAME | 1107 BE_BR_IMASK_NCNTEXP | 1108 BE_BR_IMASK_ECNTEXP | 1109 BE_BR_IMASK_LCCNTEXP | 1110 BE_BR_IMASK_FCNTEXP | 1111 BE_BR_IMASK_DTIMEXP); 1112 1113 /* Channel registers: */ 1114 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1115 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1116 1117 qecaddr = sc->sc_channel * qec->sc_msize; 1118 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1119 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1120 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1121 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1122 1123 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1124 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1125 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1126 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1127 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1128 1129 /* Enable transmitter */ 1130 bus_space_write_4(t, br, BE_BRI_TXCFG, 1131 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1132 1133 /* Enable receiver */ 1134 bus_space_write_4(t, br, BE_BRI_RXCFG, 1135 BE_BR_RXCFG_HENABLE | BE_BR_RXCFG_FIFO | 1136 BE_BR_RXCFG_ENABLE); 1137 1138 ifp->if_flags |= IFF_RUNNING; 1139 ifp->if_flags &= ~IFF_OACTIVE; 1140 1141 be_ifmedia_upd(ifp); 1142 timeout(be_tick, sc, hz); 1143 splx(s); 1144 } 1145 1146 void 1147 be_mcreset(sc) 1148 struct be_softc *sc; 1149 { 1150 struct ethercom *ec = &sc->sc_ethercom; 1151 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1152 bus_space_tag_t t = sc->sc_bustag; 1153 bus_space_handle_t br = sc->sc_br; 1154 u_int32_t crc; 1155 u_int16_t hash[4]; 1156 u_int8_t octet; 1157 u_int32_t v; 1158 int i, j; 1159 struct ether_multi *enm; 1160 struct ether_multistep step; 1161 1162 if (ifp->if_flags & IFF_PROMISC) { 1163 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1164 v |= BE_BR_RXCFG_PMISC; 1165 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1166 return; 1167 } 1168 1169 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1170 v &= ~BE_BR_RXCFG_PMISC; 1171 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1172 1173 if (ifp->if_flags & IFF_ALLMULTI) { 1174 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0xffff); 1175 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0xffff); 1176 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0xffff); 1177 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0xffff); 1178 return; 1179 } 1180 1181 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1182 1183 ETHER_FIRST_MULTI(step, ec, enm); 1184 while (enm != NULL) { 1185 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1186 /* 1187 * We must listen to a range of multicast 1188 * addresses. For now, just accept all 1189 * multicasts, rather than trying to set only 1190 * those filter bits needed to match the range. 1191 * (At this time, the only use of address 1192 * ranges is for IP multicast routing, for 1193 * which the range is big enough to require 1194 * all bits set.) 1195 */ 1196 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0xffff); 1197 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0xffff); 1198 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0xffff); 1199 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0xffff); 1200 ifp->if_flags |= IFF_ALLMULTI; 1201 return; 1202 } 1203 1204 crc = 0xffffffff; 1205 1206 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1207 octet = enm->enm_addrlo[i]; 1208 1209 for (j = 0; j < 8; j++) { 1210 if ((crc & 1) ^ (octet & 1)) { 1211 crc >>= 1; 1212 crc ^= MC_POLY_LE; 1213 } 1214 else 1215 crc >>= 1; 1216 octet >>= 1; 1217 } 1218 } 1219 1220 crc >>= 26; 1221 hash[crc >> 4] |= 1 << (crc & 0xf); 1222 ETHER_NEXT_MULTI(step, enm); 1223 } 1224 1225 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1226 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1227 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1228 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1229 ifp->if_flags &= ~IFF_ALLMULTI; 1230 } 1231 1232 /* 1233 * Set the tcvr to an idle state 1234 */ 1235 void 1236 be_mii_sync(sc) 1237 struct be_softc *sc; 1238 { 1239 bus_space_tag_t t = sc->sc_bustag; 1240 bus_space_handle_t tr = sc->sc_tr; 1241 int n = 32; 1242 1243 while (n--) { 1244 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1245 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1246 MGMT_PAL_OENAB); 1247 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1248 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1249 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1250 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1251 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1252 } 1253 } 1254 1255 void 1256 be_pal_gate(sc, phy) 1257 struct be_softc *sc; 1258 int phy; 1259 { 1260 bus_space_tag_t t = sc->sc_bustag; 1261 bus_space_handle_t tr = sc->sc_tr; 1262 u_int32_t v; 1263 1264 be_mii_sync(sc); 1265 1266 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1267 if (phy == BE_PHY_INTERNAL) 1268 v &= ~TCVR_PAL_SERIAL; 1269 1270 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1271 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1272 } 1273 1274 static int 1275 be_tcvr_read_bit(sc, phy) 1276 struct be_softc *sc; 1277 int phy; 1278 { 1279 bus_space_tag_t t = sc->sc_bustag; 1280 bus_space_handle_t tr = sc->sc_tr; 1281 int ret; 1282 1283 if (phy == BE_PHY_INTERNAL) { 1284 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1285 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1286 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1287 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1288 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1289 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1290 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1291 } else { 1292 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1293 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1294 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1295 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1296 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1297 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1298 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1299 } 1300 1301 return (ret); 1302 } 1303 1304 static void 1305 be_tcvr_write_bit(sc, phy, bit) 1306 struct be_softc *sc; 1307 int phy; 1308 int bit; 1309 { 1310 bus_space_tag_t t = sc->sc_bustag; 1311 bus_space_handle_t tr = sc->sc_tr; 1312 u_int32_t v; 1313 1314 if (phy == BE_PHY_INTERNAL) { 1315 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1316 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1317 } else { 1318 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1319 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1320 } 1321 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1322 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1323 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1324 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1325 } 1326 1327 static void 1328 be_mii_sendbits(sc, phy, data, nbits) 1329 struct be_softc *sc; 1330 int phy; 1331 u_int32_t data; 1332 int nbits; 1333 { 1334 int i; 1335 1336 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1337 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1338 } 1339 } 1340 1341 static int 1342 be_mii_readreg(self, phy, reg) 1343 struct device *self; 1344 int phy, reg; 1345 { 1346 struct be_softc *sc = (struct be_softc *)self; 1347 int val = 0, i; 1348 1349 /* 1350 * Read the PHY register by manually driving the MII control lines. 1351 */ 1352 be_mii_sync(sc); 1353 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1354 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1355 be_mii_sendbits(sc, phy, phy, 5); 1356 be_mii_sendbits(sc, phy, reg, 5); 1357 1358 (void) be_tcvr_read_bit(sc, phy); 1359 (void) be_tcvr_read_bit(sc, phy); 1360 1361 for (i = 15; i >= 0; i--) 1362 val |= (be_tcvr_read_bit(sc, phy) << i); 1363 1364 (void) be_tcvr_read_bit(sc, phy); 1365 (void) be_tcvr_read_bit(sc, phy); 1366 (void) be_tcvr_read_bit(sc, phy); 1367 1368 return (val); 1369 } 1370 1371 void 1372 be_mii_writereg(self, phy, reg, val) 1373 struct device *self; 1374 int phy, reg, val; 1375 { 1376 struct be_softc *sc = (struct be_softc *)self; 1377 int i; 1378 1379 /* 1380 * Write the PHY register by manually driving the MII control lines. 1381 */ 1382 be_mii_sync(sc); 1383 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1384 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1385 be_mii_sendbits(sc, phy, phy, 5); 1386 be_mii_sendbits(sc, phy, reg, 5); 1387 1388 be_tcvr_write_bit(sc, phy, 1); 1389 be_tcvr_write_bit(sc, phy, 0); 1390 1391 for (i = 15; i >= 0; i--) 1392 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1393 } 1394 1395 int 1396 be_mii_reset(sc, phy) 1397 struct be_softc *sc; 1398 int phy; 1399 { 1400 int n; 1401 1402 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1403 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1404 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1405 1406 for (n = 16; n >= 0; n--) { 1407 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1408 if ((bmcr & BMCR_RESET) == 0) 1409 break; 1410 DELAY(20); 1411 } 1412 if (n == 0) { 1413 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1414 return (EIO); 1415 } 1416 1417 return (0); 1418 } 1419 1420 void 1421 be_tick(arg) 1422 void *arg; 1423 { 1424 struct be_softc *sc = arg; 1425 int s = splnet(); 1426 1427 mii_tick(&sc->sc_mii); 1428 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1429 1430 splx(s); 1431 timeout(be_tick, sc, hz); 1432 } 1433 1434 void 1435 be_mii_statchg(self) 1436 struct device *self; 1437 { 1438 struct be_softc *sc = (struct be_softc *)self; 1439 bus_space_tag_t t = sc->sc_bustag; 1440 bus_space_handle_t br = sc->sc_br; 1441 u_int instance; 1442 u_int32_t v; 1443 1444 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1445 #ifdef DIAGNOSTIC 1446 if (instance > 1) 1447 panic("be_mii_statchg: instance %d out of range", instance); 1448 #endif 1449 1450 /* Update duplex mode in TX configuration */ 1451 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1452 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1453 v |= BE_BR_TXCFG_FULLDPLX; 1454 else 1455 v &= ~BE_BR_TXCFG_FULLDPLX; 1456 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1457 1458 /* Change to appropriate gate in transceiver PAL */ 1459 be_pal_gate(sc, sc->sc_phys[instance]); 1460 } 1461 1462 /* 1463 * Get current media settings. 1464 */ 1465 void 1466 be_ifmedia_sts(ifp, ifmr) 1467 struct ifnet *ifp; 1468 struct ifmediareq *ifmr; 1469 { 1470 struct be_softc *sc = ifp->if_softc; 1471 1472 mii_pollstat(&sc->sc_mii); 1473 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1474 1475 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1476 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1477 return; 1478 } 1479 1480 /* 1481 * Set media options. 1482 */ 1483 int 1484 be_ifmedia_upd(ifp) 1485 struct ifnet *ifp; 1486 { 1487 struct be_softc *sc = ifp->if_softc; 1488 int error; 1489 1490 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1491 return (error); 1492 1493 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1494 } 1495 1496 /* 1497 * Service routine for our pseudo-MII internal transceiver. 1498 */ 1499 int 1500 be_intphy_service(sc, mii, cmd) 1501 struct be_softc *sc; 1502 struct mii_data *mii; 1503 int cmd; 1504 { 1505 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1506 int bmcr, bmsr; 1507 int error; 1508 1509 switch (cmd) { 1510 case MII_POLLSTAT: 1511 /* 1512 * If we're not polling our PHY instance, just return. 1513 */ 1514 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1515 return (0); 1516 1517 break; 1518 1519 case MII_MEDIACHG: 1520 1521 /* 1522 * If the media indicates a different PHY instance, 1523 * isolate ourselves. 1524 */ 1525 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1526 bmcr = be_mii_readreg((void *)sc, 1527 BE_PHY_INTERNAL, MII_BMCR); 1528 be_mii_writereg((void *)sc, 1529 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1530 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1531 sc->sc_intphy_curspeed = 0; 1532 return (0); 1533 } 1534 1535 1536 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1537 return (error); 1538 1539 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1540 1541 /* 1542 * Select the new mode and take out of isolation 1543 */ 1544 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1545 bmcr |= BMCR_S100; 1546 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1547 bmcr &= ~BMCR_S100; 1548 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1549 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1550 bmcr &= ~BMCR_S100; 1551 bmcr |= sc->sc_intphy_curspeed; 1552 } else { 1553 /* Keep isolated until link is up */ 1554 bmcr |= BMCR_ISO; 1555 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1556 } 1557 } 1558 1559 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1560 bmcr |= BMCR_FDX; 1561 else 1562 bmcr &= ~BMCR_FDX; 1563 1564 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1565 break; 1566 1567 case MII_TICK: 1568 /* 1569 * If we're not currently selected, just return. 1570 */ 1571 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1572 return (0); 1573 1574 /* Only used for automatic media selection */ 1575 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1576 return (0); 1577 1578 /* Is the interface even up? */ 1579 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1580 return (0); 1581 1582 /* 1583 * Check link status; if we don't have a link, try another 1584 * speed. We can't detect duplex mode, so half-duplex is 1585 * what we have to settle for. 1586 */ 1587 1588 /* Read twice in case the register is latched */ 1589 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1590 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1591 1592 if ((bmsr & BMSR_LINK) != 0) { 1593 /* We have a carrier */ 1594 bmcr = be_mii_readreg((void *)sc, 1595 BE_PHY_INTERNAL, MII_BMCR); 1596 1597 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1598 bmcr = be_mii_readreg((void *)sc, 1599 BE_PHY_INTERNAL, MII_BMCR); 1600 1601 sc->sc_mii_flags |= MIIF_HAVELINK; 1602 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1603 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1604 1605 bmcr &= ~BMCR_ISO; 1606 be_mii_writereg((void *)sc, 1607 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1608 1609 printf("%s: link up at %s Mbps\n", 1610 sc->sc_dev.dv_xname, 1611 (bmcr & BMCR_S100) ? "100" : "10"); 1612 } 1613 return (0); 1614 } 1615 1616 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1617 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1618 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1619 sc->sc_intphy_curspeed = 0; 1620 printf("%s: link down\n", sc->sc_dev.dv_xname); 1621 } 1622 1623 /* Only retry autonegotiation every 5 seconds. */ 1624 if (++sc->sc_mii_ticks < 5) 1625 return(0); 1626 1627 sc->sc_mii_ticks = 0; 1628 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1629 /* Just flip the fast speed bit */ 1630 bmcr ^= BMCR_S100; 1631 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1632 1633 break; 1634 1635 case MII_DOWN: 1636 /* Isolate this phy */ 1637 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1638 be_mii_writereg((void *)sc, 1639 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1640 return (0); 1641 } 1642 1643 /* Update the media status. */ 1644 be_intphy_status(sc); 1645 1646 /* Callback if something changed. */ 1647 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1648 (*mii->mii_statchg)((struct device *)sc); 1649 sc->sc_mii_active = mii->mii_media_active; 1650 } 1651 return (0); 1652 } 1653 1654 /* 1655 * Determine status of internal transceiver 1656 */ 1657 void 1658 be_intphy_status(sc) 1659 struct be_softc *sc; 1660 { 1661 struct mii_data *mii = &sc->sc_mii; 1662 int media_active, media_status; 1663 int bmcr, bmsr; 1664 1665 media_status = IFM_AVALID; 1666 media_active = 0; 1667 1668 /* 1669 * Internal transceiver; do the work here. 1670 */ 1671 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1672 1673 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1674 case (BMCR_S100 | BMCR_FDX): 1675 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1676 break; 1677 case BMCR_S100: 1678 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1679 break; 1680 case BMCR_FDX: 1681 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1682 break; 1683 case 0: 1684 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1685 break; 1686 } 1687 1688 /* Read twice in case the register is latched */ 1689 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1690 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1691 if (bmsr & BMSR_LINK) 1692 media_status |= IFM_ACTIVE; 1693 1694 mii->mii_media_status = media_status; 1695 mii->mii_media_active = media_active; 1696 } 1697
Indexes created Tue Sep 30 07:10:03 GMT 2025