be.c revision 1.17
1 /* $NetBSD: be.c,v 1.17 2000/03/23 07:01:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 #ifdef NS 105 #include <netns/ns.h> 106 #include <netns/ns_if.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 #endif 113 114 #include <machine/autoconf.h> 115 #include <machine/cpu.h> 116 117 #include <dev/sbus/sbusvar.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/sbus/qecreg.h> 123 #include <dev/sbus/qecvar.h> 124 #include <dev/sbus/bereg.h> 125 126 struct be_softc { 127 struct device sc_dev; 128 struct sbusdev sc_sd; /* sbus device */ 129 bus_space_tag_t sc_bustag; /* bus & dma tags */ 130 bus_dma_tag_t sc_dmatag; 131 struct ethercom sc_ethercom; 132 /*struct ifmedia sc_ifmedia; -* interface media */ 133 struct mii_data sc_mii; /* MII media control */ 134 #define sc_media sc_mii.mii_media/* shorthand */ 135 int sc_phys[2]; /* MII instance -> phy */ 136 137 struct callout sc_tick_ch; 138 139 /* 140 * Some `mii_softc' items we need to emulate MII operation 141 * for our internal transceiver. 142 */ 143 int sc_mii_inst; /* instance of internal phy */ 144 int sc_mii_active; /* currently active medium */ 145 int sc_mii_ticks; /* tick counter */ 146 int sc_mii_flags; /* phy status flags */ 147 #define MIIF_HAVELINK 0x04000000 148 int sc_intphy_curspeed; /* Established link speed */ 149 150 struct qec_softc *sc_qec; /* QEC parent */ 151 152 bus_space_handle_t sc_qr; /* QEC registers */ 153 bus_space_handle_t sc_br; /* BE registers */ 154 bus_space_handle_t sc_cr; /* channel registers */ 155 bus_space_handle_t sc_tr; /* transceiver registers */ 156 157 u_int sc_rev; 158 159 int sc_channel; /* channel number */ 160 int sc_burst; 161 162 struct qec_ring sc_rb; /* Packet Ring Buffer */ 163 164 /* MAC address */ 165 u_int8_t sc_enaddr[6]; 166 }; 167 168 int bematch __P((struct device *, struct cfdata *, void *)); 169 void beattach __P((struct device *, struct device *, void *)); 170 171 void beinit __P((struct be_softc *)); 172 void bestart __P((struct ifnet *)); 173 void bestop __P((struct be_softc *)); 174 void bewatchdog __P((struct ifnet *)); 175 int beioctl __P((struct ifnet *, u_long, caddr_t)); 176 void bereset __P((struct be_softc *)); 177 178 int beintr __P((void *)); 179 int berint __P((struct be_softc *)); 180 int betint __P((struct be_softc *)); 181 int beqint __P((struct be_softc *, u_int32_t)); 182 int beeint __P((struct be_softc *, u_int32_t)); 183 184 static void be_read __P((struct be_softc *, int, int)); 185 static int be_put __P((struct be_softc *, int, struct mbuf *)); 186 static struct mbuf *be_get __P((struct be_softc *, int, int)); 187 188 void be_pal_gate __P((struct be_softc *, int)); 189 190 /* ifmedia callbacks */ 191 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 192 int be_ifmedia_upd __P((struct ifnet *)); 193 194 void be_mcreset __P((struct be_softc *)); 195 196 /* MII methods & callbacks */ 197 static int be_mii_readreg __P((struct device *, int, int)); 198 static void be_mii_writereg __P((struct device *, int, int, int)); 199 static void be_mii_statchg __P((struct device *)); 200 201 /* MII helpers */ 202 static void be_mii_sync __P((struct be_softc *)); 203 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 204 static int be_mii_reset __P((struct be_softc *, int)); 205 static int be_tcvr_read_bit __P((struct be_softc *, int)); 206 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 207 208 void be_tick __P((void *)); 209 void be_intphy_auto __P((struct be_softc *)); 210 void be_intphy_status __P((struct be_softc *)); 211 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 212 213 214 struct cfattach be_ca = { 215 sizeof(struct be_softc), bematch, beattach 216 }; 217 218 int 219 bematch(parent, cf, aux) 220 struct device *parent; 221 struct cfdata *cf; 222 void *aux; 223 { 224 struct sbus_attach_args *sa = aux; 225 226 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 227 } 228 229 void 230 beattach(parent, self, aux) 231 struct device *parent, *self; 232 void *aux; 233 { 234 struct sbus_attach_args *sa = aux; 235 struct qec_softc *qec = (struct qec_softc *)parent; 236 struct be_softc *sc = (struct be_softc *)self; 237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 238 struct mii_data *mii = &sc->sc_mii; 239 struct mii_softc *child; 240 int instance; 241 int node = sa->sa_node; 242 bus_dma_segment_t seg; 243 bus_size_t size; 244 int rseg, error; 245 u_int32_t v; 246 extern void myetheraddr __P((u_char *)); 247 248 if (sa->sa_nreg < 3) { 249 printf("%s: only %d register sets\n", 250 self->dv_xname, sa->sa_nreg); 251 return; 252 } 253 254 if (bus_space_map2(sa->sa_bustag, 255 (bus_type_t)sa->sa_reg[0].sbr_slot, 256 (bus_addr_t)sa->sa_reg[0].sbr_offset, 257 (bus_size_t)sa->sa_reg[0].sbr_size, 258 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 259 printf("beattach: cannot map registers\n"); 260 return; 261 } 262 263 if (bus_space_map2(sa->sa_bustag, 264 (bus_type_t)sa->sa_reg[1].sbr_slot, 265 (bus_addr_t)sa->sa_reg[1].sbr_offset, 266 (bus_size_t)sa->sa_reg[1].sbr_size, 267 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 268 printf("beattach: cannot map registers\n"); 269 return; 270 } 271 272 if (bus_space_map2(sa->sa_bustag, 273 (bus_type_t)sa->sa_reg[2].sbr_slot, 274 (bus_addr_t)sa->sa_reg[2].sbr_offset, 275 (bus_size_t)sa->sa_reg[2].sbr_size, 276 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 277 printf("beattach: cannot map registers\n"); 278 return; 279 } 280 281 sc->sc_qec = qec; 282 sc->sc_qr = qec->sc_regs; 283 284 sc->sc_rev = getpropint(node, "board-version", -1); 285 printf(" rev %x", sc->sc_rev); 286 287 bestop(sc); 288 289 sc->sc_channel = getpropint(node, "channel#", -1); 290 if (sc->sc_channel == -1) 291 sc->sc_channel = 0; 292 293 sc->sc_burst = getpropint(node, "burst-sizes", -1); 294 if (sc->sc_burst == -1) 295 sc->sc_burst = qec->sc_burst; 296 297 /* Clamp at parent's burst sizes */ 298 sc->sc_burst &= qec->sc_burst; 299 300 /* Establish interrupt handler */ 301 if (sa->sa_nintr) 302 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 303 0, beintr, sc); 304 305 myetheraddr(sc->sc_enaddr); 306 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 307 308 /* 309 * Allocate descriptor ring and buffers. 310 */ 311 312 /* for now, allocate as many bufs as there are ring descriptors */ 313 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 314 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 315 316 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 317 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 318 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 319 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 320 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 321 NBPG, 0, 322 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 323 printf("%s: DMA buffer alloc error %d\n", 324 self->dv_xname, error); 325 return; 326 } 327 sc->sc_rb.rb_dmabase = seg.ds_addr; 328 329 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 330 &sc->sc_rb.rb_membase, 331 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 332 printf("%s: DMA buffer map error %d\n", 333 self->dv_xname, error); 334 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 335 return; 336 } 337 338 /* 339 * Initialize our media structures and MII info. 340 */ 341 mii->mii_ifp = ifp; 342 mii->mii_readreg = be_mii_readreg; 343 mii->mii_writereg = be_mii_writereg; 344 mii->mii_statchg = be_mii_statchg; 345 346 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 347 348 callout_init(&sc->sc_tick_ch); 349 350 /* 351 * Initialize transceiver and determine which PHY connection to use. 352 */ 353 be_mii_sync(sc); 354 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 355 356 instance = 0; 357 358 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 359 360 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 361 MII_OFFSET_ANY, 0); 362 363 child = LIST_FIRST(&mii->mii_phys); 364 if (child == NULL) { 365 /* No PHY attached */ 366 ifmedia_add(&sc->sc_media, 367 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 368 0, NULL); 369 ifmedia_set(&sc->sc_media, 370 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 371 } else { 372 /* 373 * Note: we support just one PHY on the external 374 * MII connector. 375 */ 376 #ifdef DIAGNOSTIC 377 if (LIST_NEXT(child, mii_list) != NULL) { 378 printf("%s: spurious MII device %s attached\n", 379 sc->sc_dev.dv_xname, 380 child->mii_dev.dv_xname); 381 } 382 #endif 383 if (child->mii_phy != BE_PHY_EXTERNAL || 384 child->mii_inst > 0) { 385 printf("%s: cannot accomodate MII device %s" 386 " at phy %d, instance %d\n", 387 sc->sc_dev.dv_xname, 388 child->mii_dev.dv_xname, 389 child->mii_phy, child->mii_inst); 390 } else { 391 sc->sc_phys[instance] = child->mii_phy; 392 } 393 394 /* 395 * XXX - we can really do the following ONLY if the 396 * phy indeed has the auto negotiation capability!! 397 */ 398 ifmedia_set(&sc->sc_media, 399 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 400 401 /* Mark our current media setting */ 402 be_pal_gate(sc, BE_PHY_EXTERNAL); 403 instance++; 404 } 405 406 } 407 408 if ((v & MGMT_PAL_INT_MDIO) != 0) { 409 /* 410 * The be internal phy looks vaguely like MII hardware, 411 * but not enough to be able to use the MII device 412 * layer. Hence, we have to take care of media selection 413 * ourselves. 414 */ 415 416 sc->sc_mii_inst = instance; 417 sc->sc_phys[instance] = BE_PHY_INTERNAL; 418 419 /* Use `ifm_data' to store BMCR bits */ 420 ifmedia_add(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 422 0, NULL); 423 ifmedia_add(&sc->sc_media, 424 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 425 BMCR_S100, NULL); 426 ifmedia_add(&sc->sc_media, 427 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 428 0, NULL); 429 430 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 431 self->dv_xname); 432 433 be_mii_reset(sc, BE_PHY_INTERNAL); 434 /* Only set default medium here if there's no external PHY */ 435 if (instance == 0) { 436 be_pal_gate(sc, BE_PHY_INTERNAL); 437 ifmedia_set(&sc->sc_media, 438 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 439 } else 440 be_mii_writereg((void *)sc, 441 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 442 } 443 444 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 445 ifp->if_softc = sc; 446 ifp->if_start = bestart; 447 ifp->if_ioctl = beioctl; 448 ifp->if_watchdog = bewatchdog; 449 ifp->if_flags = 450 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 451 452 /* Attach the interface. */ 453 if_attach(ifp); 454 ether_ifattach(ifp, sc->sc_enaddr); 455 456 #if NBPFILTER > 0 457 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 458 #endif 459 } 460 461 462 /* 463 * Routine to copy from mbuf chain to transmit buffer in 464 * network buffer memory. 465 */ 466 static __inline__ int 467 be_put(sc, idx, m) 468 struct be_softc *sc; 469 int idx; 470 struct mbuf *m; 471 { 472 struct mbuf *n; 473 int len, tlen = 0, boff = 0; 474 caddr_t bp; 475 476 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 477 478 for (; m; m = n) { 479 len = m->m_len; 480 if (len == 0) { 481 MFREE(m, n); 482 continue; 483 } 484 bcopy(mtod(m, caddr_t), bp+boff, len); 485 boff += len; 486 tlen += len; 487 MFREE(m, n); 488 } 489 return (tlen); 490 } 491 492 /* 493 * Pull data off an interface. 494 * Len is the length of data, with local net header stripped. 495 * We copy the data into mbufs. When full cluster sized units are present, 496 * we copy into clusters. 497 */ 498 static __inline__ struct mbuf * 499 be_get(sc, idx, totlen) 500 struct be_softc *sc; 501 int idx, totlen; 502 { 503 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 504 struct mbuf *m; 505 struct mbuf *top, **mp; 506 int len, pad, boff = 0; 507 caddr_t bp; 508 509 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 510 511 MGETHDR(m, M_DONTWAIT, MT_DATA); 512 if (m == NULL) 513 return (NULL); 514 m->m_pkthdr.rcvif = ifp; 515 m->m_pkthdr.len = totlen; 516 517 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 518 m->m_data += pad; 519 len = MHLEN - pad; 520 top = NULL; 521 mp = ⊤ 522 523 while (totlen > 0) { 524 if (top) { 525 MGET(m, M_DONTWAIT, MT_DATA); 526 if (m == NULL) { 527 m_freem(top); 528 return (NULL); 529 } 530 len = MLEN; 531 } 532 if (top && totlen >= MINCLSIZE) { 533 MCLGET(m, M_DONTWAIT); 534 if (m->m_flags & M_EXT) 535 len = MCLBYTES; 536 } 537 m->m_len = len = min(totlen, len); 538 bcopy(bp + boff, mtod(m, caddr_t), len); 539 boff += len; 540 totlen -= len; 541 *mp = m; 542 mp = &m->m_next; 543 } 544 545 return (top); 546 } 547 548 /* 549 * Pass a packet to the higher levels. 550 */ 551 static __inline__ void 552 be_read(sc, idx, len) 553 struct be_softc *sc; 554 int idx, len; 555 { 556 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 557 struct mbuf *m; 558 559 if (len <= sizeof(struct ether_header) || 560 len > ETHERMTU + sizeof(struct ether_header)) { 561 562 printf("%s: invalid packet size %d; dropping\n", 563 ifp->if_xname, len); 564 565 ifp->if_ierrors++; 566 return; 567 } 568 569 /* 570 * Pull packet off interface. 571 */ 572 m = be_get(sc, idx, len); 573 if (m == NULL) { 574 ifp->if_ierrors++; 575 return; 576 } 577 ifp->if_ipackets++; 578 579 #if NBPFILTER > 0 580 /* 581 * Check if there's a BPF listener on this interface. 582 * If so, hand off the raw packet to BPF. 583 */ 584 if (ifp->if_bpf) 585 bpf_mtap(ifp->if_bpf, m); 586 #endif 587 /* Pass the packet up. */ 588 (*ifp->if_input)(ifp, m); 589 } 590 591 /* 592 * Start output on interface. 593 * We make two assumptions here: 594 * 1) that the current priority is set to splnet _before_ this code 595 * is called *and* is returned to the appropriate priority after 596 * return 597 * 2) that the IFF_OACTIVE flag is checked before this code is called 598 * (i.e. that the output part of the interface is idle) 599 */ 600 void 601 bestart(ifp) 602 struct ifnet *ifp; 603 { 604 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 605 struct qec_xd *txd = sc->sc_rb.rb_txd; 606 struct mbuf *m; 607 unsigned int bix, len; 608 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 609 610 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 611 return; 612 613 bix = sc->sc_rb.rb_tdhead; 614 615 for (;;) { 616 IF_DEQUEUE(&ifp->if_snd, m); 617 if (m == 0) 618 break; 619 620 #if NBPFILTER > 0 621 /* 622 * If BPF is listening on this interface, let it see the 623 * packet before we commit it to the wire. 624 */ 625 if (ifp->if_bpf) 626 bpf_mtap(ifp->if_bpf, m); 627 #endif 628 629 /* 630 * Copy the mbuf chain into the transmit buffer. 631 */ 632 len = be_put(sc, bix, m); 633 634 /* 635 * Initialize transmit registers and start transmission 636 */ 637 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 638 (len & QEC_XD_LENGTH); 639 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 640 BE_CR_CTRL_TWAKEUP); 641 642 if (++bix == QEC_XD_RING_MAXSIZE) 643 bix = 0; 644 645 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 646 ifp->if_flags |= IFF_OACTIVE; 647 break; 648 } 649 } 650 651 sc->sc_rb.rb_tdhead = bix; 652 } 653 654 void 655 bestop(sc) 656 struct be_softc *sc; 657 { 658 int n; 659 bus_space_tag_t t = sc->sc_bustag; 660 bus_space_handle_t br = sc->sc_br; 661 662 callout_stop(&sc->sc_tick_ch); 663 664 /* Down the MII. */ 665 mii_down(&sc->sc_mii); 666 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 667 668 /* Stop the transmitter */ 669 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 670 for (n = 32; n > 0; n--) { 671 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 672 break; 673 DELAY(20); 674 } 675 676 /* Stop the receiver */ 677 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 678 for (n = 32; n > 0; n--) { 679 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 680 break; 681 DELAY(20); 682 } 683 } 684 685 /* 686 * Reset interface. 687 */ 688 void 689 bereset(sc) 690 struct be_softc *sc; 691 { 692 int s; 693 694 s = splnet(); 695 bestop(sc); 696 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 697 beinit(sc); 698 splx(s); 699 } 700 701 void 702 bewatchdog(ifp) 703 struct ifnet *ifp; 704 { 705 struct be_softc *sc = ifp->if_softc; 706 707 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 708 ++sc->sc_ethercom.ec_if.if_oerrors; 709 710 bereset(sc); 711 } 712 713 int 714 beintr(v) 715 void *v; 716 { 717 struct be_softc *sc = (struct be_softc *)v; 718 bus_space_tag_t t = sc->sc_bustag; 719 u_int32_t whyq, whyb, whyc; 720 int r = 0; 721 722 /* Read QEC status, channel status and BE status */ 723 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 724 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 725 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 726 727 if (whyq & QEC_STAT_BM) 728 r |= beeint(sc, whyb); 729 730 if (whyq & QEC_STAT_ER) 731 r |= beqint(sc, whyc); 732 733 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 734 r |= betint(sc); 735 736 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 737 r |= berint(sc); 738 739 return (r); 740 } 741 742 /* 743 * QEC Interrupt. 744 */ 745 int 746 beqint(sc, why) 747 struct be_softc *sc; 748 u_int32_t why; 749 { 750 int r = 0, rst = 0; 751 752 if (why & BE_CR_STAT_TXIRQ) 753 r |= 1; 754 if (why & BE_CR_STAT_RXIRQ) 755 r |= 1; 756 757 if (why & BE_CR_STAT_BERROR) { 758 r |= 1; 759 rst = 1; 760 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 761 } 762 763 if (why & BE_CR_STAT_TXDERR) { 764 r |= 1; 765 rst = 1; 766 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 767 } 768 769 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 770 r |= 1; 771 rst = 1; 772 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 773 if (why & BE_CR_STAT_TXLERR) 774 printf("Late "); 775 if (why & BE_CR_STAT_TXPERR) 776 printf("Parity "); 777 if (why & BE_CR_STAT_TXSERR) 778 printf("Generic "); 779 printf(")\n"); 780 } 781 782 if (why & BE_CR_STAT_RXDROP) { 783 r |= 1; 784 rst = 1; 785 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 786 } 787 788 if (why & BE_CR_STAT_RXSMALL) { 789 r |= 1; 790 rst = 1; 791 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 792 } 793 794 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 795 r |= 1; 796 rst = 1; 797 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 798 if (why & BE_CR_STAT_RXLERR) 799 printf("Late "); 800 if (why & BE_CR_STAT_RXPERR) 801 printf("Parity "); 802 if (why & BE_CR_STAT_RXSERR) 803 printf("Generic "); 804 printf(")\n"); 805 } 806 807 if (!r) { 808 rst = 1; 809 printf("%s: unexpected error interrupt %08x\n", 810 sc->sc_dev.dv_xname, why); 811 } 812 813 if (rst) { 814 printf("%s: resetting\n", sc->sc_dev.dv_xname); 815 bereset(sc); 816 } 817 818 return (r); 819 } 820 821 /* 822 * Error interrupt. 823 */ 824 int 825 beeint(sc, why) 826 struct be_softc *sc; 827 u_int32_t why; 828 { 829 int r = 0, rst = 0; 830 831 if (why & BE_BR_STAT_RFIFOVF) { 832 r |= 1; 833 rst = 1; 834 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 835 } 836 if (why & BE_BR_STAT_TFIFO_UND) { 837 r |= 1; 838 rst = 1; 839 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 840 } 841 if (why & BE_BR_STAT_MAXPKTERR) { 842 r |= 1; 843 rst = 1; 844 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 845 } 846 847 if (!r) { 848 rst = 1; 849 printf("%s: unexpected error interrupt %08x\n", 850 sc->sc_dev.dv_xname, why); 851 } 852 853 if (rst) { 854 printf("%s: resetting\n", sc->sc_dev.dv_xname); 855 bereset(sc); 856 } 857 858 return (r); 859 } 860 861 /* 862 * Transmit interrupt. 863 */ 864 int 865 betint(sc) 866 struct be_softc *sc; 867 { 868 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 869 bus_space_tag_t t = sc->sc_bustag; 870 bus_space_handle_t br = sc->sc_br; 871 unsigned int bix, txflags; 872 873 /* 874 * Unload collision counters 875 */ 876 ifp->if_collisions += 877 bus_space_read_4(t, br, BE_BRI_NCCNT) + 878 bus_space_read_4(t, br, BE_BRI_FCCNT) + 879 bus_space_read_4(t, br, BE_BRI_EXCNT) + 880 bus_space_read_4(t, br, BE_BRI_LTCNT); 881 882 /* 883 * the clear the hardware counters 884 */ 885 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 886 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 887 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 888 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 889 890 bix = sc->sc_rb.rb_tdtail; 891 892 for (;;) { 893 if (sc->sc_rb.rb_td_nbusy <= 0) 894 break; 895 896 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 897 898 if (txflags & QEC_XD_OWN) 899 break; 900 901 ifp->if_flags &= ~IFF_OACTIVE; 902 ifp->if_opackets++; 903 904 if (++bix == QEC_XD_RING_MAXSIZE) 905 bix = 0; 906 907 --sc->sc_rb.rb_td_nbusy; 908 } 909 910 sc->sc_rb.rb_tdtail = bix; 911 912 bestart(ifp); 913 914 if (sc->sc_rb.rb_td_nbusy == 0) 915 ifp->if_timer = 0; 916 917 return (1); 918 } 919 920 /* 921 * Receive interrupt. 922 */ 923 int 924 berint(sc) 925 struct be_softc *sc; 926 { 927 struct qec_xd *xd = sc->sc_rb.rb_rxd; 928 unsigned int bix, len; 929 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 930 931 bix = sc->sc_rb.rb_rdtail; 932 933 /* 934 * Process all buffers with valid data. 935 */ 936 for (;;) { 937 len = xd[bix].xd_flags; 938 if (len & QEC_XD_OWN) 939 break; 940 941 len &= QEC_XD_LENGTH; 942 be_read(sc, bix, len); 943 944 /* ... */ 945 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 946 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 947 948 if (++bix == QEC_XD_RING_MAXSIZE) 949 bix = 0; 950 } 951 952 sc->sc_rb.rb_rdtail = bix; 953 954 return (1); 955 } 956 957 int 958 beioctl(ifp, cmd, data) 959 struct ifnet *ifp; 960 u_long cmd; 961 caddr_t data; 962 { 963 struct be_softc *sc = ifp->if_softc; 964 struct ifaddr *ifa = (struct ifaddr *)data; 965 struct ifreq *ifr = (struct ifreq *)data; 966 int s, error = 0; 967 968 s = splnet(); 969 970 switch (cmd) { 971 case SIOCSIFADDR: 972 ifp->if_flags |= IFF_UP; 973 switch (ifa->ifa_addr->sa_family) { 974 #ifdef INET 975 case AF_INET: 976 beinit(sc); 977 arp_ifinit(ifp, ifa); 978 break; 979 #endif /* INET */ 980 #ifdef NS 981 case AF_NS: 982 { 983 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 984 985 if (ns_nullhost(*ina)) 986 ina->x_host = 987 *(union ns_host *)LLADDR(ifp->if_sadl); 988 else 989 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 990 sizeof(sc->sc_enaddr)); 991 /* Set new address. */ 992 beinit(sc); 993 break; 994 } 995 #endif /* NS */ 996 default: 997 beinit(sc); 998 break; 999 } 1000 break; 1001 1002 case SIOCSIFFLAGS: 1003 if ((ifp->if_flags & IFF_UP) == 0 && 1004 (ifp->if_flags & IFF_RUNNING) != 0) { 1005 /* 1006 * If interface is marked down and it is running, then 1007 * stop it. 1008 */ 1009 bestop(sc); 1010 ifp->if_flags &= ~IFF_RUNNING; 1011 } else if ((ifp->if_flags & IFF_UP) != 0 && 1012 (ifp->if_flags & IFF_RUNNING) == 0) { 1013 /* 1014 * If interface is marked up and it is stopped, then 1015 * start it. 1016 */ 1017 beinit(sc); 1018 } else { 1019 /* 1020 * Reset the interface to pick up changes in any other 1021 * flags that affect hardware registers. 1022 */ 1023 bestop(sc); 1024 beinit(sc); 1025 } 1026 #ifdef BEDEBUG 1027 if (ifp->if_flags & IFF_DEBUG) 1028 sc->sc_debug = 1; 1029 else 1030 sc->sc_debug = 0; 1031 #endif 1032 break; 1033 1034 case SIOCADDMULTI: 1035 case SIOCDELMULTI: 1036 error = (cmd == SIOCADDMULTI) ? 1037 ether_addmulti(ifr, &sc->sc_ethercom): 1038 ether_delmulti(ifr, &sc->sc_ethercom); 1039 1040 if (error == ENETRESET) { 1041 /* 1042 * Multicast list has changed; set the hardware filter 1043 * accordingly. 1044 */ 1045 be_mcreset(sc); 1046 error = 0; 1047 } 1048 break; 1049 case SIOCGIFMEDIA: 1050 case SIOCSIFMEDIA: 1051 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1052 break; 1053 default: 1054 error = EINVAL; 1055 break; 1056 } 1057 splx(s); 1058 return (error); 1059 } 1060 1061 1062 void 1063 beinit(sc) 1064 struct be_softc *sc; 1065 { 1066 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1067 bus_space_tag_t t = sc->sc_bustag; 1068 bus_space_handle_t br = sc->sc_br; 1069 bus_space_handle_t cr = sc->sc_cr; 1070 struct qec_softc *qec = sc->sc_qec; 1071 u_int32_t v; 1072 u_int32_t qecaddr; 1073 u_int8_t *ea; 1074 int s; 1075 1076 s = splimp(); 1077 1078 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1079 1080 bestop(sc); 1081 1082 ea = sc->sc_enaddr; 1083 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1084 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1085 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1086 1087 /* Clear hash table */ 1088 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1089 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1090 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1091 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1092 1093 /* Re-initialize RX configuration */ 1094 v = BE_BR_RXCFG_FIFO; 1095 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1096 1097 be_mcreset(sc); 1098 1099 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1100 1101 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1102 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1103 1104 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1105 1106 /* 1107 * Turn off counter expiration interrupts as well as 1108 * 'gotframe' and 'sentframe' 1109 */ 1110 bus_space_write_4(t, br, BE_BRI_IMASK, 1111 BE_BR_IMASK_GOTFRAME | 1112 BE_BR_IMASK_RCNTEXP | 1113 BE_BR_IMASK_ACNTEXP | 1114 BE_BR_IMASK_CCNTEXP | 1115 BE_BR_IMASK_LCNTEXP | 1116 BE_BR_IMASK_CVCNTEXP | 1117 BE_BR_IMASK_SENTFRAME | 1118 BE_BR_IMASK_NCNTEXP | 1119 BE_BR_IMASK_ECNTEXP | 1120 BE_BR_IMASK_LCCNTEXP | 1121 BE_BR_IMASK_FCNTEXP | 1122 BE_BR_IMASK_DTIMEXP); 1123 1124 /* Channel registers: */ 1125 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1126 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1127 1128 qecaddr = sc->sc_channel * qec->sc_msize; 1129 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1130 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1131 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1132 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1133 1134 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1135 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1136 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1137 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1138 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1139 1140 /* Enable transmitter */ 1141 bus_space_write_4(t, br, BE_BRI_TXCFG, 1142 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1143 1144 /* Enable receiver */ 1145 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1146 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1147 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1148 1149 ifp->if_flags |= IFF_RUNNING; 1150 ifp->if_flags &= ~IFF_OACTIVE; 1151 1152 be_ifmedia_upd(ifp); 1153 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1154 splx(s); 1155 } 1156 1157 void 1158 be_mcreset(sc) 1159 struct be_softc *sc; 1160 { 1161 struct ethercom *ec = &sc->sc_ethercom; 1162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1163 bus_space_tag_t t = sc->sc_bustag; 1164 bus_space_handle_t br = sc->sc_br; 1165 u_int32_t crc; 1166 u_int16_t hash[4]; 1167 u_int8_t octet; 1168 u_int32_t v; 1169 int i, j; 1170 struct ether_multi *enm; 1171 struct ether_multistep step; 1172 1173 if (ifp->if_flags & IFF_PROMISC) { 1174 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1175 v |= BE_BR_RXCFG_PMISC; 1176 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1177 return; 1178 } 1179 1180 if (ifp->if_flags & IFF_ALLMULTI) { 1181 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1182 goto chipit; 1183 } 1184 1185 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1186 1187 ETHER_FIRST_MULTI(step, ec, enm); 1188 while (enm != NULL) { 1189 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1190 /* 1191 * We must listen to a range of multicast 1192 * addresses. For now, just accept all 1193 * multicasts, rather than trying to set only 1194 * those filter bits needed to match the range. 1195 * (At this time, the only use of address 1196 * ranges is for IP multicast routing, for 1197 * which the range is big enough to require 1198 * all bits set.) 1199 */ 1200 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1201 ifp->if_flags |= IFF_ALLMULTI; 1202 goto chipit; 1203 } 1204 1205 crc = 0xffffffff; 1206 1207 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1208 octet = enm->enm_addrlo[i]; 1209 1210 for (j = 0; j < 8; j++) { 1211 if ((crc & 1) ^ (octet & 1)) { 1212 crc >>= 1; 1213 crc ^= MC_POLY_LE; 1214 } 1215 else 1216 crc >>= 1; 1217 octet >>= 1; 1218 } 1219 } 1220 1221 crc >>= 26; 1222 hash[crc >> 4] |= 1 << (crc & 0xf); 1223 ETHER_NEXT_MULTI(step, enm); 1224 } 1225 1226 ifp->if_flags &= ~IFF_ALLMULTI; 1227 1228 chipit: 1229 /* Enable the hash filter */ 1230 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1231 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1232 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1233 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1234 1235 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1236 v &= ~BE_BR_RXCFG_PMISC; 1237 v |= BE_BR_RXCFG_HENABLE; 1238 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1239 } 1240 1241 /* 1242 * Set the tcvr to an idle state 1243 */ 1244 void 1245 be_mii_sync(sc) 1246 struct be_softc *sc; 1247 { 1248 bus_space_tag_t t = sc->sc_bustag; 1249 bus_space_handle_t tr = sc->sc_tr; 1250 int n = 32; 1251 1252 while (n--) { 1253 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1254 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1255 MGMT_PAL_OENAB); 1256 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1257 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1258 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1259 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1260 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1261 } 1262 } 1263 1264 void 1265 be_pal_gate(sc, phy) 1266 struct be_softc *sc; 1267 int phy; 1268 { 1269 bus_space_tag_t t = sc->sc_bustag; 1270 bus_space_handle_t tr = sc->sc_tr; 1271 u_int32_t v; 1272 1273 be_mii_sync(sc); 1274 1275 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1276 if (phy == BE_PHY_INTERNAL) 1277 v &= ~TCVR_PAL_SERIAL; 1278 1279 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1280 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1281 } 1282 1283 static int 1284 be_tcvr_read_bit(sc, phy) 1285 struct be_softc *sc; 1286 int phy; 1287 { 1288 bus_space_tag_t t = sc->sc_bustag; 1289 bus_space_handle_t tr = sc->sc_tr; 1290 int ret; 1291 1292 if (phy == BE_PHY_INTERNAL) { 1293 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1294 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1295 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1296 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1297 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1298 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1299 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1300 } else { 1301 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1302 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1303 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1304 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1305 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1306 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1307 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1308 } 1309 1310 return (ret); 1311 } 1312 1313 static void 1314 be_tcvr_write_bit(sc, phy, bit) 1315 struct be_softc *sc; 1316 int phy; 1317 int bit; 1318 { 1319 bus_space_tag_t t = sc->sc_bustag; 1320 bus_space_handle_t tr = sc->sc_tr; 1321 u_int32_t v; 1322 1323 if (phy == BE_PHY_INTERNAL) { 1324 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1325 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1326 } else { 1327 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1328 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1329 } 1330 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1331 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1332 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1333 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1334 } 1335 1336 static void 1337 be_mii_sendbits(sc, phy, data, nbits) 1338 struct be_softc *sc; 1339 int phy; 1340 u_int32_t data; 1341 int nbits; 1342 { 1343 int i; 1344 1345 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1346 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1347 } 1348 } 1349 1350 static int 1351 be_mii_readreg(self, phy, reg) 1352 struct device *self; 1353 int phy, reg; 1354 { 1355 struct be_softc *sc = (struct be_softc *)self; 1356 int val = 0, i; 1357 1358 /* 1359 * Read the PHY register by manually driving the MII control lines. 1360 */ 1361 be_mii_sync(sc); 1362 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1363 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1364 be_mii_sendbits(sc, phy, phy, 5); 1365 be_mii_sendbits(sc, phy, reg, 5); 1366 1367 (void) be_tcvr_read_bit(sc, phy); 1368 (void) be_tcvr_read_bit(sc, phy); 1369 1370 for (i = 15; i >= 0; i--) 1371 val |= (be_tcvr_read_bit(sc, phy) << i); 1372 1373 (void) be_tcvr_read_bit(sc, phy); 1374 (void) be_tcvr_read_bit(sc, phy); 1375 (void) be_tcvr_read_bit(sc, phy); 1376 1377 return (val); 1378 } 1379 1380 void 1381 be_mii_writereg(self, phy, reg, val) 1382 struct device *self; 1383 int phy, reg, val; 1384 { 1385 struct be_softc *sc = (struct be_softc *)self; 1386 int i; 1387 1388 /* 1389 * Write the PHY register by manually driving the MII control lines. 1390 */ 1391 be_mii_sync(sc); 1392 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1393 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1394 be_mii_sendbits(sc, phy, phy, 5); 1395 be_mii_sendbits(sc, phy, reg, 5); 1396 1397 be_tcvr_write_bit(sc, phy, 1); 1398 be_tcvr_write_bit(sc, phy, 0); 1399 1400 for (i = 15; i >= 0; i--) 1401 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1402 } 1403 1404 int 1405 be_mii_reset(sc, phy) 1406 struct be_softc *sc; 1407 int phy; 1408 { 1409 int n; 1410 1411 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1412 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1413 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1414 1415 for (n = 16; n >= 0; n--) { 1416 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1417 if ((bmcr & BMCR_RESET) == 0) 1418 break; 1419 DELAY(20); 1420 } 1421 if (n == 0) { 1422 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1423 return (EIO); 1424 } 1425 1426 return (0); 1427 } 1428 1429 void 1430 be_tick(arg) 1431 void *arg; 1432 { 1433 struct be_softc *sc = arg; 1434 int s = splnet(); 1435 1436 mii_tick(&sc->sc_mii); 1437 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1438 1439 splx(s); 1440 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1441 } 1442 1443 void 1444 be_mii_statchg(self) 1445 struct device *self; 1446 { 1447 struct be_softc *sc = (struct be_softc *)self; 1448 bus_space_tag_t t = sc->sc_bustag; 1449 bus_space_handle_t br = sc->sc_br; 1450 u_int instance; 1451 u_int32_t v; 1452 1453 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1454 #ifdef DIAGNOSTIC 1455 if (instance > 1) 1456 panic("be_mii_statchg: instance %d out of range", instance); 1457 #endif 1458 1459 /* Update duplex mode in TX configuration */ 1460 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1461 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1462 v |= BE_BR_TXCFG_FULLDPLX; 1463 else 1464 v &= ~BE_BR_TXCFG_FULLDPLX; 1465 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1466 1467 /* Change to appropriate gate in transceiver PAL */ 1468 be_pal_gate(sc, sc->sc_phys[instance]); 1469 } 1470 1471 /* 1472 * Get current media settings. 1473 */ 1474 void 1475 be_ifmedia_sts(ifp, ifmr) 1476 struct ifnet *ifp; 1477 struct ifmediareq *ifmr; 1478 { 1479 struct be_softc *sc = ifp->if_softc; 1480 1481 mii_pollstat(&sc->sc_mii); 1482 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1483 1484 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1485 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1486 return; 1487 } 1488 1489 /* 1490 * Set media options. 1491 */ 1492 int 1493 be_ifmedia_upd(ifp) 1494 struct ifnet *ifp; 1495 { 1496 struct be_softc *sc = ifp->if_softc; 1497 int error; 1498 1499 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1500 return (error); 1501 1502 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1503 } 1504 1505 /* 1506 * Service routine for our pseudo-MII internal transceiver. 1507 */ 1508 int 1509 be_intphy_service(sc, mii, cmd) 1510 struct be_softc *sc; 1511 struct mii_data *mii; 1512 int cmd; 1513 { 1514 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1515 int bmcr, bmsr; 1516 int error; 1517 1518 switch (cmd) { 1519 case MII_POLLSTAT: 1520 /* 1521 * If we're not polling our PHY instance, just return. 1522 */ 1523 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1524 return (0); 1525 1526 break; 1527 1528 case MII_MEDIACHG: 1529 1530 /* 1531 * If the media indicates a different PHY instance, 1532 * isolate ourselves. 1533 */ 1534 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1535 bmcr = be_mii_readreg((void *)sc, 1536 BE_PHY_INTERNAL, MII_BMCR); 1537 be_mii_writereg((void *)sc, 1538 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1539 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1540 sc->sc_intphy_curspeed = 0; 1541 return (0); 1542 } 1543 1544 1545 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1546 return (error); 1547 1548 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1549 1550 /* 1551 * Select the new mode and take out of isolation 1552 */ 1553 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1554 bmcr |= BMCR_S100; 1555 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1556 bmcr &= ~BMCR_S100; 1557 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1558 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1559 bmcr &= ~BMCR_S100; 1560 bmcr |= sc->sc_intphy_curspeed; 1561 } else { 1562 /* Keep isolated until link is up */ 1563 bmcr |= BMCR_ISO; 1564 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1565 } 1566 } 1567 1568 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1569 bmcr |= BMCR_FDX; 1570 else 1571 bmcr &= ~BMCR_FDX; 1572 1573 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1574 break; 1575 1576 case MII_TICK: 1577 /* 1578 * If we're not currently selected, just return. 1579 */ 1580 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1581 return (0); 1582 1583 /* Only used for automatic media selection */ 1584 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1585 return (0); 1586 1587 /* Is the interface even up? */ 1588 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1589 return (0); 1590 1591 /* 1592 * Check link status; if we don't have a link, try another 1593 * speed. We can't detect duplex mode, so half-duplex is 1594 * what we have to settle for. 1595 */ 1596 1597 /* Read twice in case the register is latched */ 1598 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1599 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1600 1601 if ((bmsr & BMSR_LINK) != 0) { 1602 /* We have a carrier */ 1603 bmcr = be_mii_readreg((void *)sc, 1604 BE_PHY_INTERNAL, MII_BMCR); 1605 1606 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1607 bmcr = be_mii_readreg((void *)sc, 1608 BE_PHY_INTERNAL, MII_BMCR); 1609 1610 sc->sc_mii_flags |= MIIF_HAVELINK; 1611 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1612 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1613 1614 bmcr &= ~BMCR_ISO; 1615 be_mii_writereg((void *)sc, 1616 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1617 1618 printf("%s: link up at %s Mbps\n", 1619 sc->sc_dev.dv_xname, 1620 (bmcr & BMCR_S100) ? "100" : "10"); 1621 } 1622 return (0); 1623 } 1624 1625 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1626 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1627 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1628 sc->sc_intphy_curspeed = 0; 1629 printf("%s: link down\n", sc->sc_dev.dv_xname); 1630 } 1631 1632 /* Only retry autonegotiation every 5 seconds. */ 1633 if (++sc->sc_mii_ticks < 5) 1634 return(0); 1635 1636 sc->sc_mii_ticks = 0; 1637 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1638 /* Just flip the fast speed bit */ 1639 bmcr ^= BMCR_S100; 1640 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1641 1642 break; 1643 1644 case MII_DOWN: 1645 /* Isolate this phy */ 1646 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1647 be_mii_writereg((void *)sc, 1648 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1649 return (0); 1650 } 1651 1652 /* Update the media status. */ 1653 be_intphy_status(sc); 1654 1655 /* Callback if something changed. */ 1656 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1657 (*mii->mii_statchg)((struct device *)sc); 1658 sc->sc_mii_active = mii->mii_media_active; 1659 } 1660 return (0); 1661 } 1662 1663 /* 1664 * Determine status of internal transceiver 1665 */ 1666 void 1667 be_intphy_status(sc) 1668 struct be_softc *sc; 1669 { 1670 struct mii_data *mii = &sc->sc_mii; 1671 int media_active, media_status; 1672 int bmcr, bmsr; 1673 1674 media_status = IFM_AVALID; 1675 media_active = 0; 1676 1677 /* 1678 * Internal transceiver; do the work here. 1679 */ 1680 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1681 1682 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1683 case (BMCR_S100 | BMCR_FDX): 1684 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1685 break; 1686 case BMCR_S100: 1687 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1688 break; 1689 case BMCR_FDX: 1690 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1691 break; 1692 case 0: 1693 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1694 break; 1695 } 1696 1697 /* Read twice in case the register is latched */ 1698 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1699 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1700 if (bmsr & BMSR_LINK) 1701 media_status |= IFM_ACTIVE; 1702 1703 mii->mii_media_status = media_status; 1704 mii->mii_media_active = media_active; 1705 } 1706
Indexes created Tue Sep 30 11:09:46 GMT 2025