be.c revision 1.20
1 /* $NetBSD: be.c,v 1.20 2000/05/10 14:25:43 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 #ifdef NS 105 #include <netns/ns.h> 106 #include <netns/ns_if.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 #endif 113 114 #include <machine/autoconf.h> 115 #include <machine/cpu.h> 116 117 #include <dev/sbus/sbusvar.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/sbus/qecreg.h> 123 #include <dev/sbus/qecvar.h> 124 #include <dev/sbus/bereg.h> 125 126 struct be_softc { 127 struct device sc_dev; 128 struct sbusdev sc_sd; /* sbus device */ 129 bus_space_tag_t sc_bustag; /* bus & dma tags */ 130 bus_dma_tag_t sc_dmatag; 131 bus_dmamap_t sc_dmamap; 132 struct ethercom sc_ethercom; 133 /*struct ifmedia sc_ifmedia; -* interface media */ 134 struct mii_data sc_mii; /* MII media control */ 135 #define sc_media sc_mii.mii_media/* shorthand */ 136 int sc_phys[2]; /* MII instance -> phy */ 137 138 struct callout sc_tick_ch; 139 140 /* 141 * Some `mii_softc' items we need to emulate MII operation 142 * for our internal transceiver. 143 */ 144 int sc_mii_inst; /* instance of internal phy */ 145 int sc_mii_active; /* currently active medium */ 146 int sc_mii_ticks; /* tick counter */ 147 int sc_mii_flags; /* phy status flags */ 148 #define MIIF_HAVELINK 0x04000000 149 int sc_intphy_curspeed; /* Established link speed */ 150 151 struct qec_softc *sc_qec; /* QEC parent */ 152 153 bus_space_handle_t sc_qr; /* QEC registers */ 154 bus_space_handle_t sc_br; /* BE registers */ 155 bus_space_handle_t sc_cr; /* channel registers */ 156 bus_space_handle_t sc_tr; /* transceiver registers */ 157 158 u_int sc_rev; 159 160 int sc_channel; /* channel number */ 161 int sc_burst; 162 163 struct qec_ring sc_rb; /* Packet Ring Buffer */ 164 165 /* MAC address */ 166 u_int8_t sc_enaddr[6]; 167 }; 168 169 int bematch __P((struct device *, struct cfdata *, void *)); 170 void beattach __P((struct device *, struct device *, void *)); 171 172 void beinit __P((struct be_softc *)); 173 void bestart __P((struct ifnet *)); 174 void bestop __P((struct be_softc *)); 175 void bewatchdog __P((struct ifnet *)); 176 int beioctl __P((struct ifnet *, u_long, caddr_t)); 177 void bereset __P((struct be_softc *)); 178 179 int beintr __P((void *)); 180 int berint __P((struct be_softc *)); 181 int betint __P((struct be_softc *)); 182 int beqint __P((struct be_softc *, u_int32_t)); 183 int beeint __P((struct be_softc *, u_int32_t)); 184 185 static void be_read __P((struct be_softc *, int, int)); 186 static int be_put __P((struct be_softc *, int, struct mbuf *)); 187 static struct mbuf *be_get __P((struct be_softc *, int, int)); 188 189 void be_pal_gate __P((struct be_softc *, int)); 190 191 /* ifmedia callbacks */ 192 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 193 int be_ifmedia_upd __P((struct ifnet *)); 194 195 void be_mcreset __P((struct be_softc *)); 196 197 /* MII methods & callbacks */ 198 static int be_mii_readreg __P((struct device *, int, int)); 199 static void be_mii_writereg __P((struct device *, int, int, int)); 200 static void be_mii_statchg __P((struct device *)); 201 202 /* MII helpers */ 203 static void be_mii_sync __P((struct be_softc *)); 204 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 205 static int be_mii_reset __P((struct be_softc *, int)); 206 static int be_tcvr_read_bit __P((struct be_softc *, int)); 207 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 208 209 void be_tick __P((void *)); 210 void be_intphy_auto __P((struct be_softc *)); 211 void be_intphy_status __P((struct be_softc *)); 212 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 213 214 215 struct cfattach be_ca = { 216 sizeof(struct be_softc), bematch, beattach 217 }; 218 219 int 220 bematch(parent, cf, aux) 221 struct device *parent; 222 struct cfdata *cf; 223 void *aux; 224 { 225 struct sbus_attach_args *sa = aux; 226 227 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 228 } 229 230 void 231 beattach(parent, self, aux) 232 struct device *parent, *self; 233 void *aux; 234 { 235 struct sbus_attach_args *sa = aux; 236 struct qec_softc *qec = (struct qec_softc *)parent; 237 struct be_softc *sc = (struct be_softc *)self; 238 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 239 struct mii_data *mii = &sc->sc_mii; 240 struct mii_softc *child; 241 int node = sa->sa_node; 242 bus_dma_tag_t dmatag = sa->sa_dmatag; 243 bus_dma_segment_t seg; 244 bus_size_t size; 245 int instance; 246 int rseg, error; 247 u_int32_t v; 248 extern void myetheraddr __P((u_char *)); 249 250 if (sa->sa_nreg < 3) { 251 printf("%s: only %d register sets\n", 252 self->dv_xname, sa->sa_nreg); 253 return; 254 } 255 256 if (bus_space_map2(sa->sa_bustag, 257 (bus_type_t)sa->sa_reg[0].sbr_slot, 258 (bus_addr_t)sa->sa_reg[0].sbr_offset, 259 (bus_size_t)sa->sa_reg[0].sbr_size, 260 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 261 printf("beattach: cannot map registers\n"); 262 return; 263 } 264 265 if (bus_space_map2(sa->sa_bustag, 266 (bus_type_t)sa->sa_reg[1].sbr_slot, 267 (bus_addr_t)sa->sa_reg[1].sbr_offset, 268 (bus_size_t)sa->sa_reg[1].sbr_size, 269 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 270 printf("beattach: cannot map registers\n"); 271 return; 272 } 273 274 if (bus_space_map2(sa->sa_bustag, 275 (bus_type_t)sa->sa_reg[2].sbr_slot, 276 (bus_addr_t)sa->sa_reg[2].sbr_offset, 277 (bus_size_t)sa->sa_reg[2].sbr_size, 278 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 279 printf("beattach: cannot map registers\n"); 280 return; 281 } 282 283 sc->sc_qec = qec; 284 sc->sc_qr = qec->sc_regs; 285 286 sc->sc_rev = getpropint(node, "board-version", -1); 287 printf(" rev %x", sc->sc_rev); 288 289 bestop(sc); 290 291 sc->sc_channel = getpropint(node, "channel#", -1); 292 if (sc->sc_channel == -1) 293 sc->sc_channel = 0; 294 295 sc->sc_burst = getpropint(node, "burst-sizes", -1); 296 if (sc->sc_burst == -1) 297 sc->sc_burst = qec->sc_burst; 298 299 /* Clamp at parent's burst sizes */ 300 sc->sc_burst &= qec->sc_burst; 301 302 /* Establish interrupt handler */ 303 if (sa->sa_nintr) 304 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, 305 0, beintr, sc); 306 307 myetheraddr(sc->sc_enaddr); 308 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 309 310 /* 311 * Allocate descriptor ring and buffers. 312 */ 313 314 /* for now, allocate as many bufs as there are ring descriptors */ 315 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 316 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 317 318 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 319 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 320 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 321 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 322 323 /* Get a DMA handle */ 324 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 325 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 326 printf("%s: DMA map create error %d\n", self->dv_xname, error); 327 return; 328 } 329 330 /* Allocate DMA buffer */ 331 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 332 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 333 printf("%s: DMA buffer alloc error %d\n", 334 self->dv_xname, error); 335 return; 336 } 337 338 /* Load the buffer */ 339 if ((error = bus_dmamap_load_raw(dmatag, sc->sc_dmamap, 340 &seg, rseg, size, BUS_DMA_NOWAIT)) != 0) { 341 printf("%s: DMA buffer map load error %d\n", 342 self->dv_xname, error); 343 bus_dmamem_free(dmatag, &seg, rseg); 344 return; 345 } 346 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 347 348 /* Map DMA memory in CPU addressable space */ 349 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 350 &sc->sc_rb.rb_membase, 351 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 352 printf("%s: DMA buffer map error %d\n", 353 self->dv_xname, error); 354 bus_dmamap_unload(dmatag, sc->sc_dmamap); 355 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 356 return; 357 } 358 359 /* 360 * Initialize our media structures and MII info. 361 */ 362 mii->mii_ifp = ifp; 363 mii->mii_readreg = be_mii_readreg; 364 mii->mii_writereg = be_mii_writereg; 365 mii->mii_statchg = be_mii_statchg; 366 367 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 368 369 callout_init(&sc->sc_tick_ch); 370 371 /* 372 * Initialize transceiver and determine which PHY connection to use. 373 */ 374 be_mii_sync(sc); 375 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 376 377 instance = 0; 378 379 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 380 381 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 382 MII_OFFSET_ANY, 0); 383 384 child = LIST_FIRST(&mii->mii_phys); 385 if (child == NULL) { 386 /* No PHY attached */ 387 ifmedia_add(&sc->sc_media, 388 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 389 0, NULL); 390 ifmedia_set(&sc->sc_media, 391 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 392 } else { 393 /* 394 * Note: we support just one PHY on the external 395 * MII connector. 396 */ 397 #ifdef DIAGNOSTIC 398 if (LIST_NEXT(child, mii_list) != NULL) { 399 printf("%s: spurious MII device %s attached\n", 400 sc->sc_dev.dv_xname, 401 child->mii_dev.dv_xname); 402 } 403 #endif 404 if (child->mii_phy != BE_PHY_EXTERNAL || 405 child->mii_inst > 0) { 406 printf("%s: cannot accomodate MII device %s" 407 " at phy %d, instance %d\n", 408 sc->sc_dev.dv_xname, 409 child->mii_dev.dv_xname, 410 child->mii_phy, child->mii_inst); 411 } else { 412 sc->sc_phys[instance] = child->mii_phy; 413 } 414 415 /* 416 * XXX - we can really do the following ONLY if the 417 * phy indeed has the auto negotiation capability!! 418 */ 419 ifmedia_set(&sc->sc_media, 420 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 421 422 /* Mark our current media setting */ 423 be_pal_gate(sc, BE_PHY_EXTERNAL); 424 instance++; 425 } 426 427 } 428 429 if ((v & MGMT_PAL_INT_MDIO) != 0) { 430 /* 431 * The be internal phy looks vaguely like MII hardware, 432 * but not enough to be able to use the MII device 433 * layer. Hence, we have to take care of media selection 434 * ourselves. 435 */ 436 437 sc->sc_mii_inst = instance; 438 sc->sc_phys[instance] = BE_PHY_INTERNAL; 439 440 /* Use `ifm_data' to store BMCR bits */ 441 ifmedia_add(&sc->sc_media, 442 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 443 0, NULL); 444 ifmedia_add(&sc->sc_media, 445 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 446 BMCR_S100, NULL); 447 ifmedia_add(&sc->sc_media, 448 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 449 0, NULL); 450 451 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 452 self->dv_xname); 453 454 be_mii_reset(sc, BE_PHY_INTERNAL); 455 /* Only set default medium here if there's no external PHY */ 456 if (instance == 0) { 457 be_pal_gate(sc, BE_PHY_INTERNAL); 458 ifmedia_set(&sc->sc_media, 459 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 460 } else 461 be_mii_writereg((void *)sc, 462 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 463 } 464 465 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 466 ifp->if_softc = sc; 467 ifp->if_start = bestart; 468 ifp->if_ioctl = beioctl; 469 ifp->if_watchdog = bewatchdog; 470 ifp->if_flags = 471 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 472 473 /* Attach the interface. */ 474 if_attach(ifp); 475 ether_ifattach(ifp, sc->sc_enaddr); 476 477 #if NBPFILTER > 0 478 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 479 #endif 480 } 481 482 483 /* 484 * Routine to copy from mbuf chain to transmit buffer in 485 * network buffer memory. 486 */ 487 static __inline__ int 488 be_put(sc, idx, m) 489 struct be_softc *sc; 490 int idx; 491 struct mbuf *m; 492 { 493 struct mbuf *n; 494 int len, tlen = 0, boff = 0; 495 caddr_t bp; 496 497 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 498 499 for (; m; m = n) { 500 len = m->m_len; 501 if (len == 0) { 502 MFREE(m, n); 503 continue; 504 } 505 bcopy(mtod(m, caddr_t), bp+boff, len); 506 boff += len; 507 tlen += len; 508 MFREE(m, n); 509 } 510 return (tlen); 511 } 512 513 /* 514 * Pull data off an interface. 515 * Len is the length of data, with local net header stripped. 516 * We copy the data into mbufs. When full cluster sized units are present, 517 * we copy into clusters. 518 */ 519 static __inline__ struct mbuf * 520 be_get(sc, idx, totlen) 521 struct be_softc *sc; 522 int idx, totlen; 523 { 524 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 525 struct mbuf *m; 526 struct mbuf *top, **mp; 527 int len, pad, boff = 0; 528 caddr_t bp; 529 530 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 531 532 MGETHDR(m, M_DONTWAIT, MT_DATA); 533 if (m == NULL) 534 return (NULL); 535 m->m_pkthdr.rcvif = ifp; 536 m->m_pkthdr.len = totlen; 537 538 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 539 m->m_data += pad; 540 len = MHLEN - pad; 541 top = NULL; 542 mp = ⊤ 543 544 while (totlen > 0) { 545 if (top) { 546 MGET(m, M_DONTWAIT, MT_DATA); 547 if (m == NULL) { 548 m_freem(top); 549 return (NULL); 550 } 551 len = MLEN; 552 } 553 if (top && totlen >= MINCLSIZE) { 554 MCLGET(m, M_DONTWAIT); 555 if (m->m_flags & M_EXT) 556 len = MCLBYTES; 557 } 558 m->m_len = len = min(totlen, len); 559 bcopy(bp + boff, mtod(m, caddr_t), len); 560 boff += len; 561 totlen -= len; 562 *mp = m; 563 mp = &m->m_next; 564 } 565 566 return (top); 567 } 568 569 /* 570 * Pass a packet to the higher levels. 571 */ 572 static __inline__ void 573 be_read(sc, idx, len) 574 struct be_softc *sc; 575 int idx, len; 576 { 577 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 578 struct mbuf *m; 579 580 if (len <= sizeof(struct ether_header) || 581 len > ETHERMTU + sizeof(struct ether_header)) { 582 583 printf("%s: invalid packet size %d; dropping\n", 584 ifp->if_xname, len); 585 586 ifp->if_ierrors++; 587 return; 588 } 589 590 /* 591 * Pull packet off interface. 592 */ 593 m = be_get(sc, idx, len); 594 if (m == NULL) { 595 ifp->if_ierrors++; 596 return; 597 } 598 ifp->if_ipackets++; 599 600 #if NBPFILTER > 0 601 /* 602 * Check if there's a BPF listener on this interface. 603 * If so, hand off the raw packet to BPF. 604 */ 605 if (ifp->if_bpf) 606 bpf_mtap(ifp->if_bpf, m); 607 #endif 608 /* Pass the packet up. */ 609 (*ifp->if_input)(ifp, m); 610 } 611 612 /* 613 * Start output on interface. 614 * We make two assumptions here: 615 * 1) that the current priority is set to splnet _before_ this code 616 * is called *and* is returned to the appropriate priority after 617 * return 618 * 2) that the IFF_OACTIVE flag is checked before this code is called 619 * (i.e. that the output part of the interface is idle) 620 */ 621 void 622 bestart(ifp) 623 struct ifnet *ifp; 624 { 625 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 626 struct qec_xd *txd = sc->sc_rb.rb_txd; 627 struct mbuf *m; 628 unsigned int bix, len; 629 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 630 631 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 632 return; 633 634 bix = sc->sc_rb.rb_tdhead; 635 636 for (;;) { 637 IF_DEQUEUE(&ifp->if_snd, m); 638 if (m == 0) 639 break; 640 641 #if NBPFILTER > 0 642 /* 643 * If BPF is listening on this interface, let it see the 644 * packet before we commit it to the wire. 645 */ 646 if (ifp->if_bpf) 647 bpf_mtap(ifp->if_bpf, m); 648 #endif 649 650 /* 651 * Copy the mbuf chain into the transmit buffer. 652 */ 653 len = be_put(sc, bix, m); 654 655 /* 656 * Initialize transmit registers and start transmission 657 */ 658 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 659 (len & QEC_XD_LENGTH); 660 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 661 BE_CR_CTRL_TWAKEUP); 662 663 if (++bix == QEC_XD_RING_MAXSIZE) 664 bix = 0; 665 666 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 667 ifp->if_flags |= IFF_OACTIVE; 668 break; 669 } 670 } 671 672 sc->sc_rb.rb_tdhead = bix; 673 } 674 675 void 676 bestop(sc) 677 struct be_softc *sc; 678 { 679 int n; 680 bus_space_tag_t t = sc->sc_bustag; 681 bus_space_handle_t br = sc->sc_br; 682 683 callout_stop(&sc->sc_tick_ch); 684 685 /* Down the MII. */ 686 mii_down(&sc->sc_mii); 687 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 688 689 /* Stop the transmitter */ 690 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 691 for (n = 32; n > 0; n--) { 692 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 693 break; 694 DELAY(20); 695 } 696 697 /* Stop the receiver */ 698 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 699 for (n = 32; n > 0; n--) { 700 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 701 break; 702 DELAY(20); 703 } 704 } 705 706 /* 707 * Reset interface. 708 */ 709 void 710 bereset(sc) 711 struct be_softc *sc; 712 { 713 int s; 714 715 s = splnet(); 716 bestop(sc); 717 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 718 beinit(sc); 719 splx(s); 720 } 721 722 void 723 bewatchdog(ifp) 724 struct ifnet *ifp; 725 { 726 struct be_softc *sc = ifp->if_softc; 727 728 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 729 ++sc->sc_ethercom.ec_if.if_oerrors; 730 731 bereset(sc); 732 } 733 734 int 735 beintr(v) 736 void *v; 737 { 738 struct be_softc *sc = (struct be_softc *)v; 739 bus_space_tag_t t = sc->sc_bustag; 740 u_int32_t whyq, whyb, whyc; 741 int r = 0; 742 743 /* Read QEC status, channel status and BE status */ 744 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 745 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 746 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 747 748 if (whyq & QEC_STAT_BM) 749 r |= beeint(sc, whyb); 750 751 if (whyq & QEC_STAT_ER) 752 r |= beqint(sc, whyc); 753 754 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 755 r |= betint(sc); 756 757 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 758 r |= berint(sc); 759 760 return (r); 761 } 762 763 /* 764 * QEC Interrupt. 765 */ 766 int 767 beqint(sc, why) 768 struct be_softc *sc; 769 u_int32_t why; 770 { 771 int r = 0, rst = 0; 772 773 if (why & BE_CR_STAT_TXIRQ) 774 r |= 1; 775 if (why & BE_CR_STAT_RXIRQ) 776 r |= 1; 777 778 if (why & BE_CR_STAT_BERROR) { 779 r |= 1; 780 rst = 1; 781 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 782 } 783 784 if (why & BE_CR_STAT_TXDERR) { 785 r |= 1; 786 rst = 1; 787 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 788 } 789 790 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 791 r |= 1; 792 rst = 1; 793 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 794 if (why & BE_CR_STAT_TXLERR) 795 printf("Late "); 796 if (why & BE_CR_STAT_TXPERR) 797 printf("Parity "); 798 if (why & BE_CR_STAT_TXSERR) 799 printf("Generic "); 800 printf(")\n"); 801 } 802 803 if (why & BE_CR_STAT_RXDROP) { 804 r |= 1; 805 rst = 1; 806 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 807 } 808 809 if (why & BE_CR_STAT_RXSMALL) { 810 r |= 1; 811 rst = 1; 812 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 813 } 814 815 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 816 r |= 1; 817 rst = 1; 818 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 819 if (why & BE_CR_STAT_RXLERR) 820 printf("Late "); 821 if (why & BE_CR_STAT_RXPERR) 822 printf("Parity "); 823 if (why & BE_CR_STAT_RXSERR) 824 printf("Generic "); 825 printf(")\n"); 826 } 827 828 if (!r) { 829 rst = 1; 830 printf("%s: unexpected error interrupt %08x\n", 831 sc->sc_dev.dv_xname, why); 832 } 833 834 if (rst) { 835 printf("%s: resetting\n", sc->sc_dev.dv_xname); 836 bereset(sc); 837 } 838 839 return (r); 840 } 841 842 /* 843 * Error interrupt. 844 */ 845 int 846 beeint(sc, why) 847 struct be_softc *sc; 848 u_int32_t why; 849 { 850 int r = 0, rst = 0; 851 852 if (why & BE_BR_STAT_RFIFOVF) { 853 r |= 1; 854 rst = 1; 855 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 856 } 857 if (why & BE_BR_STAT_TFIFO_UND) { 858 r |= 1; 859 rst = 1; 860 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 861 } 862 if (why & BE_BR_STAT_MAXPKTERR) { 863 r |= 1; 864 rst = 1; 865 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 866 } 867 868 if (!r) { 869 rst = 1; 870 printf("%s: unexpected error interrupt %08x\n", 871 sc->sc_dev.dv_xname, why); 872 } 873 874 if (rst) { 875 printf("%s: resetting\n", sc->sc_dev.dv_xname); 876 bereset(sc); 877 } 878 879 return (r); 880 } 881 882 /* 883 * Transmit interrupt. 884 */ 885 int 886 betint(sc) 887 struct be_softc *sc; 888 { 889 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 890 bus_space_tag_t t = sc->sc_bustag; 891 bus_space_handle_t br = sc->sc_br; 892 unsigned int bix, txflags; 893 894 /* 895 * Unload collision counters 896 */ 897 ifp->if_collisions += 898 bus_space_read_4(t, br, BE_BRI_NCCNT) + 899 bus_space_read_4(t, br, BE_BRI_FCCNT) + 900 bus_space_read_4(t, br, BE_BRI_EXCNT) + 901 bus_space_read_4(t, br, BE_BRI_LTCNT); 902 903 /* 904 * the clear the hardware counters 905 */ 906 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 907 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 908 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 909 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 910 911 bix = sc->sc_rb.rb_tdtail; 912 913 for (;;) { 914 if (sc->sc_rb.rb_td_nbusy <= 0) 915 break; 916 917 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 918 919 if (txflags & QEC_XD_OWN) 920 break; 921 922 ifp->if_flags &= ~IFF_OACTIVE; 923 ifp->if_opackets++; 924 925 if (++bix == QEC_XD_RING_MAXSIZE) 926 bix = 0; 927 928 --sc->sc_rb.rb_td_nbusy; 929 } 930 931 sc->sc_rb.rb_tdtail = bix; 932 933 bestart(ifp); 934 935 if (sc->sc_rb.rb_td_nbusy == 0) 936 ifp->if_timer = 0; 937 938 return (1); 939 } 940 941 /* 942 * Receive interrupt. 943 */ 944 int 945 berint(sc) 946 struct be_softc *sc; 947 { 948 struct qec_xd *xd = sc->sc_rb.rb_rxd; 949 unsigned int bix, len; 950 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 951 952 bix = sc->sc_rb.rb_rdtail; 953 954 /* 955 * Process all buffers with valid data. 956 */ 957 for (;;) { 958 len = xd[bix].xd_flags; 959 if (len & QEC_XD_OWN) 960 break; 961 962 len &= QEC_XD_LENGTH; 963 be_read(sc, bix, len); 964 965 /* ... */ 966 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 967 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 968 969 if (++bix == QEC_XD_RING_MAXSIZE) 970 bix = 0; 971 } 972 973 sc->sc_rb.rb_rdtail = bix; 974 975 return (1); 976 } 977 978 int 979 beioctl(ifp, cmd, data) 980 struct ifnet *ifp; 981 u_long cmd; 982 caddr_t data; 983 { 984 struct be_softc *sc = ifp->if_softc; 985 struct ifaddr *ifa = (struct ifaddr *)data; 986 struct ifreq *ifr = (struct ifreq *)data; 987 int s, error = 0; 988 989 s = splnet(); 990 991 switch (cmd) { 992 case SIOCSIFADDR: 993 ifp->if_flags |= IFF_UP; 994 switch (ifa->ifa_addr->sa_family) { 995 #ifdef INET 996 case AF_INET: 997 beinit(sc); 998 arp_ifinit(ifp, ifa); 999 break; 1000 #endif /* INET */ 1001 #ifdef NS 1002 case AF_NS: 1003 { 1004 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1005 1006 if (ns_nullhost(*ina)) 1007 ina->x_host = 1008 *(union ns_host *)LLADDR(ifp->if_sadl); 1009 else 1010 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1011 sizeof(sc->sc_enaddr)); 1012 /* Set new address. */ 1013 beinit(sc); 1014 break; 1015 } 1016 #endif /* NS */ 1017 default: 1018 beinit(sc); 1019 break; 1020 } 1021 break; 1022 1023 case SIOCSIFFLAGS: 1024 if ((ifp->if_flags & IFF_UP) == 0 && 1025 (ifp->if_flags & IFF_RUNNING) != 0) { 1026 /* 1027 * If interface is marked down and it is running, then 1028 * stop it. 1029 */ 1030 bestop(sc); 1031 ifp->if_flags &= ~IFF_RUNNING; 1032 } else if ((ifp->if_flags & IFF_UP) != 0 && 1033 (ifp->if_flags & IFF_RUNNING) == 0) { 1034 /* 1035 * If interface is marked up and it is stopped, then 1036 * start it. 1037 */ 1038 beinit(sc); 1039 } else { 1040 /* 1041 * Reset the interface to pick up changes in any other 1042 * flags that affect hardware registers. 1043 */ 1044 bestop(sc); 1045 beinit(sc); 1046 } 1047 #ifdef BEDEBUG 1048 if (ifp->if_flags & IFF_DEBUG) 1049 sc->sc_debug = 1; 1050 else 1051 sc->sc_debug = 0; 1052 #endif 1053 break; 1054 1055 case SIOCADDMULTI: 1056 case SIOCDELMULTI: 1057 error = (cmd == SIOCADDMULTI) ? 1058 ether_addmulti(ifr, &sc->sc_ethercom): 1059 ether_delmulti(ifr, &sc->sc_ethercom); 1060 1061 if (error == ENETRESET) { 1062 /* 1063 * Multicast list has changed; set the hardware filter 1064 * accordingly. 1065 */ 1066 be_mcreset(sc); 1067 error = 0; 1068 } 1069 break; 1070 case SIOCGIFMEDIA: 1071 case SIOCSIFMEDIA: 1072 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1073 break; 1074 default: 1075 error = EINVAL; 1076 break; 1077 } 1078 splx(s); 1079 return (error); 1080 } 1081 1082 1083 void 1084 beinit(sc) 1085 struct be_softc *sc; 1086 { 1087 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1088 bus_space_tag_t t = sc->sc_bustag; 1089 bus_space_handle_t br = sc->sc_br; 1090 bus_space_handle_t cr = sc->sc_cr; 1091 struct qec_softc *qec = sc->sc_qec; 1092 u_int32_t v; 1093 u_int32_t qecaddr; 1094 u_int8_t *ea; 1095 int s; 1096 1097 s = splimp(); 1098 1099 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1100 1101 bestop(sc); 1102 1103 ea = sc->sc_enaddr; 1104 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1105 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1106 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1107 1108 /* Clear hash table */ 1109 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1110 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1111 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1112 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1113 1114 /* Re-initialize RX configuration */ 1115 v = BE_BR_RXCFG_FIFO; 1116 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1117 1118 be_mcreset(sc); 1119 1120 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1121 1122 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1123 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1124 1125 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1126 1127 /* 1128 * Turn off counter expiration interrupts as well as 1129 * 'gotframe' and 'sentframe' 1130 */ 1131 bus_space_write_4(t, br, BE_BRI_IMASK, 1132 BE_BR_IMASK_GOTFRAME | 1133 BE_BR_IMASK_RCNTEXP | 1134 BE_BR_IMASK_ACNTEXP | 1135 BE_BR_IMASK_CCNTEXP | 1136 BE_BR_IMASK_LCNTEXP | 1137 BE_BR_IMASK_CVCNTEXP | 1138 BE_BR_IMASK_SENTFRAME | 1139 BE_BR_IMASK_NCNTEXP | 1140 BE_BR_IMASK_ECNTEXP | 1141 BE_BR_IMASK_LCCNTEXP | 1142 BE_BR_IMASK_FCNTEXP | 1143 BE_BR_IMASK_DTIMEXP); 1144 1145 /* Channel registers: */ 1146 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1147 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1148 1149 qecaddr = sc->sc_channel * qec->sc_msize; 1150 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1151 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1152 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1153 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1154 1155 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1156 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1157 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1158 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1159 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1160 1161 /* Enable transmitter */ 1162 bus_space_write_4(t, br, BE_BRI_TXCFG, 1163 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1164 1165 /* Enable receiver */ 1166 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1167 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1168 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1169 1170 ifp->if_flags |= IFF_RUNNING; 1171 ifp->if_flags &= ~IFF_OACTIVE; 1172 1173 be_ifmedia_upd(ifp); 1174 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1175 splx(s); 1176 } 1177 1178 void 1179 be_mcreset(sc) 1180 struct be_softc *sc; 1181 { 1182 struct ethercom *ec = &sc->sc_ethercom; 1183 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1184 bus_space_tag_t t = sc->sc_bustag; 1185 bus_space_handle_t br = sc->sc_br; 1186 u_int32_t crc; 1187 u_int16_t hash[4]; 1188 u_int8_t octet; 1189 u_int32_t v; 1190 int i, j; 1191 struct ether_multi *enm; 1192 struct ether_multistep step; 1193 1194 if (ifp->if_flags & IFF_PROMISC) { 1195 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1196 v |= BE_BR_RXCFG_PMISC; 1197 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1198 return; 1199 } 1200 1201 if (ifp->if_flags & IFF_ALLMULTI) { 1202 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1203 goto chipit; 1204 } 1205 1206 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1207 1208 ETHER_FIRST_MULTI(step, ec, enm); 1209 while (enm != NULL) { 1210 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1211 /* 1212 * We must listen to a range of multicast 1213 * addresses. For now, just accept all 1214 * multicasts, rather than trying to set only 1215 * those filter bits needed to match the range. 1216 * (At this time, the only use of address 1217 * ranges is for IP multicast routing, for 1218 * which the range is big enough to require 1219 * all bits set.) 1220 */ 1221 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1222 ifp->if_flags |= IFF_ALLMULTI; 1223 goto chipit; 1224 } 1225 1226 crc = 0xffffffff; 1227 1228 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1229 octet = enm->enm_addrlo[i]; 1230 1231 for (j = 0; j < 8; j++) { 1232 if ((crc & 1) ^ (octet & 1)) { 1233 crc >>= 1; 1234 crc ^= MC_POLY_LE; 1235 } 1236 else 1237 crc >>= 1; 1238 octet >>= 1; 1239 } 1240 } 1241 1242 crc >>= 26; 1243 hash[crc >> 4] |= 1 << (crc & 0xf); 1244 ETHER_NEXT_MULTI(step, enm); 1245 } 1246 1247 ifp->if_flags &= ~IFF_ALLMULTI; 1248 1249 chipit: 1250 /* Enable the hash filter */ 1251 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1252 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1253 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1254 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1255 1256 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1257 v &= ~BE_BR_RXCFG_PMISC; 1258 v |= BE_BR_RXCFG_HENABLE; 1259 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1260 } 1261 1262 /* 1263 * Set the tcvr to an idle state 1264 */ 1265 void 1266 be_mii_sync(sc) 1267 struct be_softc *sc; 1268 { 1269 bus_space_tag_t t = sc->sc_bustag; 1270 bus_space_handle_t tr = sc->sc_tr; 1271 int n = 32; 1272 1273 while (n--) { 1274 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1275 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1276 MGMT_PAL_OENAB); 1277 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1278 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1279 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1280 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1281 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1282 } 1283 } 1284 1285 void 1286 be_pal_gate(sc, phy) 1287 struct be_softc *sc; 1288 int phy; 1289 { 1290 bus_space_tag_t t = sc->sc_bustag; 1291 bus_space_handle_t tr = sc->sc_tr; 1292 u_int32_t v; 1293 1294 be_mii_sync(sc); 1295 1296 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1297 if (phy == BE_PHY_INTERNAL) 1298 v &= ~TCVR_PAL_SERIAL; 1299 1300 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1301 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1302 } 1303 1304 static int 1305 be_tcvr_read_bit(sc, phy) 1306 struct be_softc *sc; 1307 int phy; 1308 { 1309 bus_space_tag_t t = sc->sc_bustag; 1310 bus_space_handle_t tr = sc->sc_tr; 1311 int ret; 1312 1313 if (phy == BE_PHY_INTERNAL) { 1314 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1315 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1316 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1317 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1318 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1319 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1320 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1321 } else { 1322 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1323 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1324 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1325 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1326 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1327 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1328 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1329 } 1330 1331 return (ret); 1332 } 1333 1334 static void 1335 be_tcvr_write_bit(sc, phy, bit) 1336 struct be_softc *sc; 1337 int phy; 1338 int bit; 1339 { 1340 bus_space_tag_t t = sc->sc_bustag; 1341 bus_space_handle_t tr = sc->sc_tr; 1342 u_int32_t v; 1343 1344 if (phy == BE_PHY_INTERNAL) { 1345 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1346 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1347 } else { 1348 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1349 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1350 } 1351 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1352 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1353 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1354 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1355 } 1356 1357 static void 1358 be_mii_sendbits(sc, phy, data, nbits) 1359 struct be_softc *sc; 1360 int phy; 1361 u_int32_t data; 1362 int nbits; 1363 { 1364 int i; 1365 1366 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1367 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1368 } 1369 } 1370 1371 static int 1372 be_mii_readreg(self, phy, reg) 1373 struct device *self; 1374 int phy, reg; 1375 { 1376 struct be_softc *sc = (struct be_softc *)self; 1377 int val = 0, i; 1378 1379 /* 1380 * Read the PHY register by manually driving the MII control lines. 1381 */ 1382 be_mii_sync(sc); 1383 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1384 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1385 be_mii_sendbits(sc, phy, phy, 5); 1386 be_mii_sendbits(sc, phy, reg, 5); 1387 1388 (void) be_tcvr_read_bit(sc, phy); 1389 (void) be_tcvr_read_bit(sc, phy); 1390 1391 for (i = 15; i >= 0; i--) 1392 val |= (be_tcvr_read_bit(sc, phy) << i); 1393 1394 (void) be_tcvr_read_bit(sc, phy); 1395 (void) be_tcvr_read_bit(sc, phy); 1396 (void) be_tcvr_read_bit(sc, phy); 1397 1398 return (val); 1399 } 1400 1401 void 1402 be_mii_writereg(self, phy, reg, val) 1403 struct device *self; 1404 int phy, reg, val; 1405 { 1406 struct be_softc *sc = (struct be_softc *)self; 1407 int i; 1408 1409 /* 1410 * Write the PHY register by manually driving the MII control lines. 1411 */ 1412 be_mii_sync(sc); 1413 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1414 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1415 be_mii_sendbits(sc, phy, phy, 5); 1416 be_mii_sendbits(sc, phy, reg, 5); 1417 1418 be_tcvr_write_bit(sc, phy, 1); 1419 be_tcvr_write_bit(sc, phy, 0); 1420 1421 for (i = 15; i >= 0; i--) 1422 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1423 } 1424 1425 int 1426 be_mii_reset(sc, phy) 1427 struct be_softc *sc; 1428 int phy; 1429 { 1430 int n; 1431 1432 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1433 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1434 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1435 1436 for (n = 16; n >= 0; n--) { 1437 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1438 if ((bmcr & BMCR_RESET) == 0) 1439 break; 1440 DELAY(20); 1441 } 1442 if (n == 0) { 1443 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1444 return (EIO); 1445 } 1446 1447 return (0); 1448 } 1449 1450 void 1451 be_tick(arg) 1452 void *arg; 1453 { 1454 struct be_softc *sc = arg; 1455 int s = splnet(); 1456 1457 mii_tick(&sc->sc_mii); 1458 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1459 1460 splx(s); 1461 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1462 } 1463 1464 void 1465 be_mii_statchg(self) 1466 struct device *self; 1467 { 1468 struct be_softc *sc = (struct be_softc *)self; 1469 bus_space_tag_t t = sc->sc_bustag; 1470 bus_space_handle_t br = sc->sc_br; 1471 u_int instance; 1472 u_int32_t v; 1473 1474 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1475 #ifdef DIAGNOSTIC 1476 if (instance > 1) 1477 panic("be_mii_statchg: instance %d out of range", instance); 1478 #endif 1479 1480 /* Update duplex mode in TX configuration */ 1481 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1482 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1483 v |= BE_BR_TXCFG_FULLDPLX; 1484 else 1485 v &= ~BE_BR_TXCFG_FULLDPLX; 1486 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1487 1488 /* Change to appropriate gate in transceiver PAL */ 1489 be_pal_gate(sc, sc->sc_phys[instance]); 1490 } 1491 1492 /* 1493 * Get current media settings. 1494 */ 1495 void 1496 be_ifmedia_sts(ifp, ifmr) 1497 struct ifnet *ifp; 1498 struct ifmediareq *ifmr; 1499 { 1500 struct be_softc *sc = ifp->if_softc; 1501 1502 mii_pollstat(&sc->sc_mii); 1503 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1504 1505 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1506 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1507 return; 1508 } 1509 1510 /* 1511 * Set media options. 1512 */ 1513 int 1514 be_ifmedia_upd(ifp) 1515 struct ifnet *ifp; 1516 { 1517 struct be_softc *sc = ifp->if_softc; 1518 int error; 1519 1520 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1521 return (error); 1522 1523 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1524 } 1525 1526 /* 1527 * Service routine for our pseudo-MII internal transceiver. 1528 */ 1529 int 1530 be_intphy_service(sc, mii, cmd) 1531 struct be_softc *sc; 1532 struct mii_data *mii; 1533 int cmd; 1534 { 1535 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1536 int bmcr, bmsr; 1537 int error; 1538 1539 switch (cmd) { 1540 case MII_POLLSTAT: 1541 /* 1542 * If we're not polling our PHY instance, just return. 1543 */ 1544 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1545 return (0); 1546 1547 break; 1548 1549 case MII_MEDIACHG: 1550 1551 /* 1552 * If the media indicates a different PHY instance, 1553 * isolate ourselves. 1554 */ 1555 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1556 bmcr = be_mii_readreg((void *)sc, 1557 BE_PHY_INTERNAL, MII_BMCR); 1558 be_mii_writereg((void *)sc, 1559 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1560 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1561 sc->sc_intphy_curspeed = 0; 1562 return (0); 1563 } 1564 1565 1566 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1567 return (error); 1568 1569 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1570 1571 /* 1572 * Select the new mode and take out of isolation 1573 */ 1574 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1575 bmcr |= BMCR_S100; 1576 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1577 bmcr &= ~BMCR_S100; 1578 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1579 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1580 bmcr &= ~BMCR_S100; 1581 bmcr |= sc->sc_intphy_curspeed; 1582 } else { 1583 /* Keep isolated until link is up */ 1584 bmcr |= BMCR_ISO; 1585 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1586 } 1587 } 1588 1589 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1590 bmcr |= BMCR_FDX; 1591 else 1592 bmcr &= ~BMCR_FDX; 1593 1594 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1595 break; 1596 1597 case MII_TICK: 1598 /* 1599 * If we're not currently selected, just return. 1600 */ 1601 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1602 return (0); 1603 1604 /* Only used for automatic media selection */ 1605 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1606 return (0); 1607 1608 /* Is the interface even up? */ 1609 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1610 return (0); 1611 1612 /* 1613 * Check link status; if we don't have a link, try another 1614 * speed. We can't detect duplex mode, so half-duplex is 1615 * what we have to settle for. 1616 */ 1617 1618 /* Read twice in case the register is latched */ 1619 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1620 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1621 1622 if ((bmsr & BMSR_LINK) != 0) { 1623 /* We have a carrier */ 1624 bmcr = be_mii_readreg((void *)sc, 1625 BE_PHY_INTERNAL, MII_BMCR); 1626 1627 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1628 bmcr = be_mii_readreg((void *)sc, 1629 BE_PHY_INTERNAL, MII_BMCR); 1630 1631 sc->sc_mii_flags |= MIIF_HAVELINK; 1632 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1633 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1634 1635 bmcr &= ~BMCR_ISO; 1636 be_mii_writereg((void *)sc, 1637 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1638 1639 printf("%s: link up at %s Mbps\n", 1640 sc->sc_dev.dv_xname, 1641 (bmcr & BMCR_S100) ? "100" : "10"); 1642 } 1643 return (0); 1644 } 1645 1646 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1647 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1648 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1649 sc->sc_intphy_curspeed = 0; 1650 printf("%s: link down\n", sc->sc_dev.dv_xname); 1651 } 1652 1653 /* Only retry autonegotiation every 5 seconds. */ 1654 if (++sc->sc_mii_ticks < 5) 1655 return(0); 1656 1657 sc->sc_mii_ticks = 0; 1658 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1659 /* Just flip the fast speed bit */ 1660 bmcr ^= BMCR_S100; 1661 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1662 1663 break; 1664 1665 case MII_DOWN: 1666 /* Isolate this phy */ 1667 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1668 be_mii_writereg((void *)sc, 1669 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1670 return (0); 1671 } 1672 1673 /* Update the media status. */ 1674 be_intphy_status(sc); 1675 1676 /* Callback if something changed. */ 1677 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1678 (*mii->mii_statchg)((struct device *)sc); 1679 sc->sc_mii_active = mii->mii_media_active; 1680 } 1681 return (0); 1682 } 1683 1684 /* 1685 * Determine status of internal transceiver 1686 */ 1687 void 1688 be_intphy_status(sc) 1689 struct be_softc *sc; 1690 { 1691 struct mii_data *mii = &sc->sc_mii; 1692 int media_active, media_status; 1693 int bmcr, bmsr; 1694 1695 media_status = IFM_AVALID; 1696 media_active = 0; 1697 1698 /* 1699 * Internal transceiver; do the work here. 1700 */ 1701 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1702 1703 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1704 case (BMCR_S100 | BMCR_FDX): 1705 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1706 break; 1707 case BMCR_S100: 1708 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1709 break; 1710 case BMCR_FDX: 1711 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1712 break; 1713 case 0: 1714 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1715 break; 1716 } 1717 1718 /* Read twice in case the register is latched */ 1719 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1720 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1721 if (bmsr & BMSR_LINK) 1722 media_status |= IFM_ACTIVE; 1723 1724 mii->mii_media_status = media_status; 1725 mii->mii_media_active = media_active; 1726 } 1727
Indexes created Tue Sep 30 11:09:46 GMT 2025