be.c revision 1.22
1 /* $NetBSD: be.c,v 1.22 2000/11/15 01:02:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 #ifdef NS 105 #include <netns/ns.h> 106 #include <netns/ns_if.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 #endif 113 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 #include <machine/autoconf.h> 117 118 #include <dev/sbus/sbusvar.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/sbus/qecreg.h> 124 #include <dev/sbus/qecvar.h> 125 #include <dev/sbus/bereg.h> 126 127 struct be_softc { 128 struct device sc_dev; 129 struct sbusdev sc_sd; /* sbus device */ 130 bus_space_tag_t sc_bustag; /* bus & dma tags */ 131 bus_dma_tag_t sc_dmatag; 132 bus_dmamap_t sc_dmamap; 133 struct ethercom sc_ethercom; 134 /*struct ifmedia sc_ifmedia; -* interface media */ 135 struct mii_data sc_mii; /* MII media control */ 136 #define sc_media sc_mii.mii_media/* shorthand */ 137 int sc_phys[2]; /* MII instance -> phy */ 138 139 struct callout sc_tick_ch; 140 141 /* 142 * Some `mii_softc' items we need to emulate MII operation 143 * for our internal transceiver. 144 */ 145 int sc_mii_inst; /* instance of internal phy */ 146 int sc_mii_active; /* currently active medium */ 147 int sc_mii_ticks; /* tick counter */ 148 int sc_mii_flags; /* phy status flags */ 149 #define MIIF_HAVELINK 0x04000000 150 int sc_intphy_curspeed; /* Established link speed */ 151 152 struct qec_softc *sc_qec; /* QEC parent */ 153 154 bus_space_handle_t sc_qr; /* QEC registers */ 155 bus_space_handle_t sc_br; /* BE registers */ 156 bus_space_handle_t sc_cr; /* channel registers */ 157 bus_space_handle_t sc_tr; /* transceiver registers */ 158 159 u_int sc_rev; 160 161 int sc_channel; /* channel number */ 162 int sc_burst; 163 164 struct qec_ring sc_rb; /* Packet Ring Buffer */ 165 166 /* MAC address */ 167 u_int8_t sc_enaddr[6]; 168 }; 169 170 int bematch __P((struct device *, struct cfdata *, void *)); 171 void beattach __P((struct device *, struct device *, void *)); 172 173 void beinit __P((struct be_softc *)); 174 void bestart __P((struct ifnet *)); 175 void bestop __P((struct be_softc *)); 176 void bewatchdog __P((struct ifnet *)); 177 int beioctl __P((struct ifnet *, u_long, caddr_t)); 178 void bereset __P((struct be_softc *)); 179 180 int beintr __P((void *)); 181 int berint __P((struct be_softc *)); 182 int betint __P((struct be_softc *)); 183 int beqint __P((struct be_softc *, u_int32_t)); 184 int beeint __P((struct be_softc *, u_int32_t)); 185 186 static void be_read __P((struct be_softc *, int, int)); 187 static int be_put __P((struct be_softc *, int, struct mbuf *)); 188 static struct mbuf *be_get __P((struct be_softc *, int, int)); 189 190 void be_pal_gate __P((struct be_softc *, int)); 191 192 /* ifmedia callbacks */ 193 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 194 int be_ifmedia_upd __P((struct ifnet *)); 195 196 void be_mcreset __P((struct be_softc *)); 197 198 /* MII methods & callbacks */ 199 static int be_mii_readreg __P((struct device *, int, int)); 200 static void be_mii_writereg __P((struct device *, int, int, int)); 201 static void be_mii_statchg __P((struct device *)); 202 203 /* MII helpers */ 204 static void be_mii_sync __P((struct be_softc *)); 205 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 206 static int be_mii_reset __P((struct be_softc *, int)); 207 static int be_tcvr_read_bit __P((struct be_softc *, int)); 208 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 209 210 void be_tick __P((void *)); 211 void be_intphy_auto __P((struct be_softc *)); 212 void be_intphy_status __P((struct be_softc *)); 213 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 214 215 216 struct cfattach be_ca = { 217 sizeof(struct be_softc), bematch, beattach 218 }; 219 220 int 221 bematch(parent, cf, aux) 222 struct device *parent; 223 struct cfdata *cf; 224 void *aux; 225 { 226 struct sbus_attach_args *sa = aux; 227 228 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 229 } 230 231 void 232 beattach(parent, self, aux) 233 struct device *parent, *self; 234 void *aux; 235 { 236 struct sbus_attach_args *sa = aux; 237 struct qec_softc *qec = (struct qec_softc *)parent; 238 struct be_softc *sc = (struct be_softc *)self; 239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 240 struct mii_data *mii = &sc->sc_mii; 241 struct mii_softc *child; 242 int node = sa->sa_node; 243 bus_dma_tag_t dmatag = sa->sa_dmatag; 244 bus_dma_segment_t seg; 245 bus_size_t size; 246 int instance; 247 int rseg, error; 248 u_int32_t v; 249 extern void myetheraddr __P((u_char *)); 250 251 if (sa->sa_nreg < 3) { 252 printf("%s: only %d register sets\n", 253 self->dv_xname, sa->sa_nreg); 254 return; 255 } 256 257 if (bus_space_map2(sa->sa_bustag, 258 (bus_type_t)sa->sa_reg[0].sbr_slot, 259 (bus_addr_t)sa->sa_reg[0].sbr_offset, 260 (bus_size_t)sa->sa_reg[0].sbr_size, 261 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 262 printf("beattach: cannot map registers\n"); 263 return; 264 } 265 266 if (bus_space_map2(sa->sa_bustag, 267 (bus_type_t)sa->sa_reg[1].sbr_slot, 268 (bus_addr_t)sa->sa_reg[1].sbr_offset, 269 (bus_size_t)sa->sa_reg[1].sbr_size, 270 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 271 printf("beattach: cannot map registers\n"); 272 return; 273 } 274 275 if (bus_space_map2(sa->sa_bustag, 276 (bus_type_t)sa->sa_reg[2].sbr_slot, 277 (bus_addr_t)sa->sa_reg[2].sbr_offset, 278 (bus_size_t)sa->sa_reg[2].sbr_size, 279 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 280 printf("beattach: cannot map registers\n"); 281 return; 282 } 283 284 sc->sc_qec = qec; 285 sc->sc_qr = qec->sc_regs; 286 287 sc->sc_rev = getpropint(node, "board-version", -1); 288 printf(" rev %x", sc->sc_rev); 289 290 bestop(sc); 291 292 sc->sc_channel = getpropint(node, "channel#", -1); 293 if (sc->sc_channel == -1) 294 sc->sc_channel = 0; 295 296 sc->sc_burst = getpropint(node, "burst-sizes", -1); 297 if (sc->sc_burst == -1) 298 sc->sc_burst = qec->sc_burst; 299 300 /* Clamp at parent's burst sizes */ 301 sc->sc_burst &= qec->sc_burst; 302 303 /* Establish interrupt handler */ 304 if (sa->sa_nintr) 305 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 306 0, beintr, sc); 307 308 myetheraddr(sc->sc_enaddr); 309 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 310 311 /* 312 * Allocate descriptor ring and buffers. 313 */ 314 315 /* for now, allocate as many bufs as there are ring descriptors */ 316 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 317 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 318 319 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 320 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 321 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 322 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 323 324 /* Get a DMA handle */ 325 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 326 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 327 printf("%s: DMA map create error %d\n", self->dv_xname, error); 328 return; 329 } 330 331 /* Allocate DMA buffer */ 332 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 333 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 334 printf("%s: DMA buffer alloc error %d\n", 335 self->dv_xname, error); 336 return; 337 } 338 339 /* Load the buffer */ 340 if ((error = bus_dmamap_load_raw(dmatag, sc->sc_dmamap, 341 &seg, rseg, size, BUS_DMA_NOWAIT)) != 0) { 342 printf("%s: DMA buffer map load error %d\n", 343 self->dv_xname, error); 344 bus_dmamem_free(dmatag, &seg, rseg); 345 return; 346 } 347 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 348 349 /* Map DMA memory in CPU addressable space */ 350 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 351 &sc->sc_rb.rb_membase, 352 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 353 printf("%s: DMA buffer map error %d\n", 354 self->dv_xname, error); 355 bus_dmamap_unload(dmatag, sc->sc_dmamap); 356 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 357 return; 358 } 359 360 /* 361 * Initialize our media structures and MII info. 362 */ 363 mii->mii_ifp = ifp; 364 mii->mii_readreg = be_mii_readreg; 365 mii->mii_writereg = be_mii_writereg; 366 mii->mii_statchg = be_mii_statchg; 367 368 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 369 370 callout_init(&sc->sc_tick_ch); 371 372 /* 373 * Initialize transceiver and determine which PHY connection to use. 374 */ 375 be_mii_sync(sc); 376 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 377 378 instance = 0; 379 380 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 381 382 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 383 MII_OFFSET_ANY, 0); 384 385 child = LIST_FIRST(&mii->mii_phys); 386 if (child == NULL) { 387 /* No PHY attached */ 388 ifmedia_add(&sc->sc_media, 389 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 390 0, NULL); 391 ifmedia_set(&sc->sc_media, 392 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 393 } else { 394 /* 395 * Note: we support just one PHY on the external 396 * MII connector. 397 */ 398 #ifdef DIAGNOSTIC 399 if (LIST_NEXT(child, mii_list) != NULL) { 400 printf("%s: spurious MII device %s attached\n", 401 sc->sc_dev.dv_xname, 402 child->mii_dev.dv_xname); 403 } 404 #endif 405 if (child->mii_phy != BE_PHY_EXTERNAL || 406 child->mii_inst > 0) { 407 printf("%s: cannot accomodate MII device %s" 408 " at phy %d, instance %d\n", 409 sc->sc_dev.dv_xname, 410 child->mii_dev.dv_xname, 411 child->mii_phy, child->mii_inst); 412 } else { 413 sc->sc_phys[instance] = child->mii_phy; 414 } 415 416 /* 417 * XXX - we can really do the following ONLY if the 418 * phy indeed has the auto negotiation capability!! 419 */ 420 ifmedia_set(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 422 423 /* Mark our current media setting */ 424 be_pal_gate(sc, BE_PHY_EXTERNAL); 425 instance++; 426 } 427 428 } 429 430 if ((v & MGMT_PAL_INT_MDIO) != 0) { 431 /* 432 * The be internal phy looks vaguely like MII hardware, 433 * but not enough to be able to use the MII device 434 * layer. Hence, we have to take care of media selection 435 * ourselves. 436 */ 437 438 sc->sc_mii_inst = instance; 439 sc->sc_phys[instance] = BE_PHY_INTERNAL; 440 441 /* Use `ifm_data' to store BMCR bits */ 442 ifmedia_add(&sc->sc_media, 443 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 444 0, NULL); 445 ifmedia_add(&sc->sc_media, 446 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 447 BMCR_S100, NULL); 448 ifmedia_add(&sc->sc_media, 449 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 450 0, NULL); 451 452 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 453 self->dv_xname); 454 455 be_mii_reset(sc, BE_PHY_INTERNAL); 456 /* Only set default medium here if there's no external PHY */ 457 if (instance == 0) { 458 be_pal_gate(sc, BE_PHY_INTERNAL); 459 ifmedia_set(&sc->sc_media, 460 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 461 } else 462 be_mii_writereg((void *)sc, 463 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 464 } 465 466 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 467 ifp->if_softc = sc; 468 ifp->if_start = bestart; 469 ifp->if_ioctl = beioctl; 470 ifp->if_watchdog = bewatchdog; 471 ifp->if_flags = 472 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 473 474 /* Attach the interface. */ 475 if_attach(ifp); 476 ether_ifattach(ifp, sc->sc_enaddr); 477 } 478 479 480 /* 481 * Routine to copy from mbuf chain to transmit buffer in 482 * network buffer memory. 483 */ 484 static __inline__ int 485 be_put(sc, idx, m) 486 struct be_softc *sc; 487 int idx; 488 struct mbuf *m; 489 { 490 struct mbuf *n; 491 int len, tlen = 0, boff = 0; 492 caddr_t bp; 493 494 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 495 496 for (; m; m = n) { 497 len = m->m_len; 498 if (len == 0) { 499 MFREE(m, n); 500 continue; 501 } 502 bcopy(mtod(m, caddr_t), bp+boff, len); 503 boff += len; 504 tlen += len; 505 MFREE(m, n); 506 } 507 return (tlen); 508 } 509 510 /* 511 * Pull data off an interface. 512 * Len is the length of data, with local net header stripped. 513 * We copy the data into mbufs. When full cluster sized units are present, 514 * we copy into clusters. 515 */ 516 static __inline__ struct mbuf * 517 be_get(sc, idx, totlen) 518 struct be_softc *sc; 519 int idx, totlen; 520 { 521 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 522 struct mbuf *m; 523 struct mbuf *top, **mp; 524 int len, pad, boff = 0; 525 caddr_t bp; 526 527 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 528 529 MGETHDR(m, M_DONTWAIT, MT_DATA); 530 if (m == NULL) 531 return (NULL); 532 m->m_pkthdr.rcvif = ifp; 533 m->m_pkthdr.len = totlen; 534 535 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 536 m->m_data += pad; 537 len = MHLEN - pad; 538 top = NULL; 539 mp = ⊤ 540 541 while (totlen > 0) { 542 if (top) { 543 MGET(m, M_DONTWAIT, MT_DATA); 544 if (m == NULL) { 545 m_freem(top); 546 return (NULL); 547 } 548 len = MLEN; 549 } 550 if (top && totlen >= MINCLSIZE) { 551 MCLGET(m, M_DONTWAIT); 552 if (m->m_flags & M_EXT) 553 len = MCLBYTES; 554 } 555 m->m_len = len = min(totlen, len); 556 bcopy(bp + boff, mtod(m, caddr_t), len); 557 boff += len; 558 totlen -= len; 559 *mp = m; 560 mp = &m->m_next; 561 } 562 563 return (top); 564 } 565 566 /* 567 * Pass a packet to the higher levels. 568 */ 569 static __inline__ void 570 be_read(sc, idx, len) 571 struct be_softc *sc; 572 int idx, len; 573 { 574 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 575 struct mbuf *m; 576 577 if (len <= sizeof(struct ether_header) || 578 len > ETHERMTU + sizeof(struct ether_header)) { 579 580 printf("%s: invalid packet size %d; dropping\n", 581 ifp->if_xname, len); 582 583 ifp->if_ierrors++; 584 return; 585 } 586 587 /* 588 * Pull packet off interface. 589 */ 590 m = be_get(sc, idx, len); 591 if (m == NULL) { 592 ifp->if_ierrors++; 593 return; 594 } 595 ifp->if_ipackets++; 596 597 #if NBPFILTER > 0 598 /* 599 * Check if there's a BPF listener on this interface. 600 * If so, hand off the raw packet to BPF. 601 */ 602 if (ifp->if_bpf) 603 bpf_mtap(ifp->if_bpf, m); 604 #endif 605 /* Pass the packet up. */ 606 (*ifp->if_input)(ifp, m); 607 } 608 609 /* 610 * Start output on interface. 611 * We make two assumptions here: 612 * 1) that the current priority is set to splnet _before_ this code 613 * is called *and* is returned to the appropriate priority after 614 * return 615 * 2) that the IFF_OACTIVE flag is checked before this code is called 616 * (i.e. that the output part of the interface is idle) 617 */ 618 void 619 bestart(ifp) 620 struct ifnet *ifp; 621 { 622 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 623 struct qec_xd *txd = sc->sc_rb.rb_txd; 624 struct mbuf *m; 625 unsigned int bix, len; 626 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 627 628 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 629 return; 630 631 bix = sc->sc_rb.rb_tdhead; 632 633 for (;;) { 634 IF_DEQUEUE(&ifp->if_snd, m); 635 if (m == 0) 636 break; 637 638 #if NBPFILTER > 0 639 /* 640 * If BPF is listening on this interface, let it see the 641 * packet before we commit it to the wire. 642 */ 643 if (ifp->if_bpf) 644 bpf_mtap(ifp->if_bpf, m); 645 #endif 646 647 /* 648 * Copy the mbuf chain into the transmit buffer. 649 */ 650 len = be_put(sc, bix, m); 651 652 /* 653 * Initialize transmit registers and start transmission 654 */ 655 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 656 (len & QEC_XD_LENGTH); 657 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 658 BE_CR_CTRL_TWAKEUP); 659 660 if (++bix == QEC_XD_RING_MAXSIZE) 661 bix = 0; 662 663 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 664 ifp->if_flags |= IFF_OACTIVE; 665 break; 666 } 667 } 668 669 sc->sc_rb.rb_tdhead = bix; 670 } 671 672 void 673 bestop(sc) 674 struct be_softc *sc; 675 { 676 int n; 677 bus_space_tag_t t = sc->sc_bustag; 678 bus_space_handle_t br = sc->sc_br; 679 680 callout_stop(&sc->sc_tick_ch); 681 682 /* Down the MII. */ 683 mii_down(&sc->sc_mii); 684 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 685 686 /* Stop the transmitter */ 687 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 688 for (n = 32; n > 0; n--) { 689 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 690 break; 691 DELAY(20); 692 } 693 694 /* Stop the receiver */ 695 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 696 for (n = 32; n > 0; n--) { 697 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 698 break; 699 DELAY(20); 700 } 701 } 702 703 /* 704 * Reset interface. 705 */ 706 void 707 bereset(sc) 708 struct be_softc *sc; 709 { 710 int s; 711 712 s = splnet(); 713 bestop(sc); 714 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 715 beinit(sc); 716 splx(s); 717 } 718 719 void 720 bewatchdog(ifp) 721 struct ifnet *ifp; 722 { 723 struct be_softc *sc = ifp->if_softc; 724 725 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 726 ++sc->sc_ethercom.ec_if.if_oerrors; 727 728 bereset(sc); 729 } 730 731 int 732 beintr(v) 733 void *v; 734 { 735 struct be_softc *sc = (struct be_softc *)v; 736 bus_space_tag_t t = sc->sc_bustag; 737 u_int32_t whyq, whyb, whyc; 738 int r = 0; 739 740 /* Read QEC status, channel status and BE status */ 741 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 742 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 743 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 744 745 if (whyq & QEC_STAT_BM) 746 r |= beeint(sc, whyb); 747 748 if (whyq & QEC_STAT_ER) 749 r |= beqint(sc, whyc); 750 751 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 752 r |= betint(sc); 753 754 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 755 r |= berint(sc); 756 757 return (r); 758 } 759 760 /* 761 * QEC Interrupt. 762 */ 763 int 764 beqint(sc, why) 765 struct be_softc *sc; 766 u_int32_t why; 767 { 768 int r = 0, rst = 0; 769 770 if (why & BE_CR_STAT_TXIRQ) 771 r |= 1; 772 if (why & BE_CR_STAT_RXIRQ) 773 r |= 1; 774 775 if (why & BE_CR_STAT_BERROR) { 776 r |= 1; 777 rst = 1; 778 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 779 } 780 781 if (why & BE_CR_STAT_TXDERR) { 782 r |= 1; 783 rst = 1; 784 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 785 } 786 787 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 788 r |= 1; 789 rst = 1; 790 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 791 if (why & BE_CR_STAT_TXLERR) 792 printf("Late "); 793 if (why & BE_CR_STAT_TXPERR) 794 printf("Parity "); 795 if (why & BE_CR_STAT_TXSERR) 796 printf("Generic "); 797 printf(")\n"); 798 } 799 800 if (why & BE_CR_STAT_RXDROP) { 801 r |= 1; 802 rst = 1; 803 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 804 } 805 806 if (why & BE_CR_STAT_RXSMALL) { 807 r |= 1; 808 rst = 1; 809 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 810 } 811 812 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 813 r |= 1; 814 rst = 1; 815 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 816 if (why & BE_CR_STAT_RXLERR) 817 printf("Late "); 818 if (why & BE_CR_STAT_RXPERR) 819 printf("Parity "); 820 if (why & BE_CR_STAT_RXSERR) 821 printf("Generic "); 822 printf(")\n"); 823 } 824 825 if (!r) { 826 rst = 1; 827 printf("%s: unexpected error interrupt %08x\n", 828 sc->sc_dev.dv_xname, why); 829 } 830 831 if (rst) { 832 printf("%s: resetting\n", sc->sc_dev.dv_xname); 833 bereset(sc); 834 } 835 836 return (r); 837 } 838 839 /* 840 * Error interrupt. 841 */ 842 int 843 beeint(sc, why) 844 struct be_softc *sc; 845 u_int32_t why; 846 { 847 int r = 0, rst = 0; 848 849 if (why & BE_BR_STAT_RFIFOVF) { 850 r |= 1; 851 rst = 1; 852 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 853 } 854 if (why & BE_BR_STAT_TFIFO_UND) { 855 r |= 1; 856 rst = 1; 857 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 858 } 859 if (why & BE_BR_STAT_MAXPKTERR) { 860 r |= 1; 861 rst = 1; 862 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 863 } 864 865 if (!r) { 866 rst = 1; 867 printf("%s: unexpected error interrupt %08x\n", 868 sc->sc_dev.dv_xname, why); 869 } 870 871 if (rst) { 872 printf("%s: resetting\n", sc->sc_dev.dv_xname); 873 bereset(sc); 874 } 875 876 return (r); 877 } 878 879 /* 880 * Transmit interrupt. 881 */ 882 int 883 betint(sc) 884 struct be_softc *sc; 885 { 886 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 887 bus_space_tag_t t = sc->sc_bustag; 888 bus_space_handle_t br = sc->sc_br; 889 unsigned int bix, txflags; 890 891 /* 892 * Unload collision counters 893 */ 894 ifp->if_collisions += 895 bus_space_read_4(t, br, BE_BRI_NCCNT) + 896 bus_space_read_4(t, br, BE_BRI_FCCNT) + 897 bus_space_read_4(t, br, BE_BRI_EXCNT) + 898 bus_space_read_4(t, br, BE_BRI_LTCNT); 899 900 /* 901 * the clear the hardware counters 902 */ 903 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 904 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 905 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 906 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 907 908 bix = sc->sc_rb.rb_tdtail; 909 910 for (;;) { 911 if (sc->sc_rb.rb_td_nbusy <= 0) 912 break; 913 914 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 915 916 if (txflags & QEC_XD_OWN) 917 break; 918 919 ifp->if_flags &= ~IFF_OACTIVE; 920 ifp->if_opackets++; 921 922 if (++bix == QEC_XD_RING_MAXSIZE) 923 bix = 0; 924 925 --sc->sc_rb.rb_td_nbusy; 926 } 927 928 sc->sc_rb.rb_tdtail = bix; 929 930 bestart(ifp); 931 932 if (sc->sc_rb.rb_td_nbusy == 0) 933 ifp->if_timer = 0; 934 935 return (1); 936 } 937 938 /* 939 * Receive interrupt. 940 */ 941 int 942 berint(sc) 943 struct be_softc *sc; 944 { 945 struct qec_xd *xd = sc->sc_rb.rb_rxd; 946 unsigned int bix, len; 947 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 948 949 bix = sc->sc_rb.rb_rdtail; 950 951 /* 952 * Process all buffers with valid data. 953 */ 954 for (;;) { 955 len = xd[bix].xd_flags; 956 if (len & QEC_XD_OWN) 957 break; 958 959 len &= QEC_XD_LENGTH; 960 be_read(sc, bix, len); 961 962 /* ... */ 963 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 964 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 965 966 if (++bix == QEC_XD_RING_MAXSIZE) 967 bix = 0; 968 } 969 970 sc->sc_rb.rb_rdtail = bix; 971 972 return (1); 973 } 974 975 int 976 beioctl(ifp, cmd, data) 977 struct ifnet *ifp; 978 u_long cmd; 979 caddr_t data; 980 { 981 struct be_softc *sc = ifp->if_softc; 982 struct ifaddr *ifa = (struct ifaddr *)data; 983 struct ifreq *ifr = (struct ifreq *)data; 984 int s, error = 0; 985 986 s = splnet(); 987 988 switch (cmd) { 989 case SIOCSIFADDR: 990 ifp->if_flags |= IFF_UP; 991 switch (ifa->ifa_addr->sa_family) { 992 #ifdef INET 993 case AF_INET: 994 beinit(sc); 995 arp_ifinit(ifp, ifa); 996 break; 997 #endif /* INET */ 998 #ifdef NS 999 case AF_NS: 1000 { 1001 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1002 1003 if (ns_nullhost(*ina)) 1004 ina->x_host = 1005 *(union ns_host *)LLADDR(ifp->if_sadl); 1006 else 1007 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1008 sizeof(sc->sc_enaddr)); 1009 /* Set new address. */ 1010 beinit(sc); 1011 break; 1012 } 1013 #endif /* NS */ 1014 default: 1015 beinit(sc); 1016 break; 1017 } 1018 break; 1019 1020 case SIOCSIFFLAGS: 1021 if ((ifp->if_flags & IFF_UP) == 0 && 1022 (ifp->if_flags & IFF_RUNNING) != 0) { 1023 /* 1024 * If interface is marked down and it is running, then 1025 * stop it. 1026 */ 1027 bestop(sc); 1028 ifp->if_flags &= ~IFF_RUNNING; 1029 } else if ((ifp->if_flags & IFF_UP) != 0 && 1030 (ifp->if_flags & IFF_RUNNING) == 0) { 1031 /* 1032 * If interface is marked up and it is stopped, then 1033 * start it. 1034 */ 1035 beinit(sc); 1036 } else { 1037 /* 1038 * Reset the interface to pick up changes in any other 1039 * flags that affect hardware registers. 1040 */ 1041 bestop(sc); 1042 beinit(sc); 1043 } 1044 #ifdef BEDEBUG 1045 if (ifp->if_flags & IFF_DEBUG) 1046 sc->sc_debug = 1; 1047 else 1048 sc->sc_debug = 0; 1049 #endif 1050 break; 1051 1052 case SIOCADDMULTI: 1053 case SIOCDELMULTI: 1054 error = (cmd == SIOCADDMULTI) ? 1055 ether_addmulti(ifr, &sc->sc_ethercom): 1056 ether_delmulti(ifr, &sc->sc_ethercom); 1057 1058 if (error == ENETRESET) { 1059 /* 1060 * Multicast list has changed; set the hardware filter 1061 * accordingly. 1062 */ 1063 be_mcreset(sc); 1064 error = 0; 1065 } 1066 break; 1067 case SIOCGIFMEDIA: 1068 case SIOCSIFMEDIA: 1069 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1070 break; 1071 default: 1072 error = EINVAL; 1073 break; 1074 } 1075 splx(s); 1076 return (error); 1077 } 1078 1079 1080 void 1081 beinit(sc) 1082 struct be_softc *sc; 1083 { 1084 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1085 bus_space_tag_t t = sc->sc_bustag; 1086 bus_space_handle_t br = sc->sc_br; 1087 bus_space_handle_t cr = sc->sc_cr; 1088 struct qec_softc *qec = sc->sc_qec; 1089 u_int32_t v; 1090 u_int32_t qecaddr; 1091 u_int8_t *ea; 1092 int s; 1093 1094 s = splimp(); 1095 1096 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1097 1098 bestop(sc); 1099 1100 ea = sc->sc_enaddr; 1101 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1102 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1103 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1104 1105 /* Clear hash table */ 1106 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1107 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1108 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1109 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1110 1111 /* Re-initialize RX configuration */ 1112 v = BE_BR_RXCFG_FIFO; 1113 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1114 1115 be_mcreset(sc); 1116 1117 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1118 1119 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1120 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1121 1122 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1123 1124 /* 1125 * Turn off counter expiration interrupts as well as 1126 * 'gotframe' and 'sentframe' 1127 */ 1128 bus_space_write_4(t, br, BE_BRI_IMASK, 1129 BE_BR_IMASK_GOTFRAME | 1130 BE_BR_IMASK_RCNTEXP | 1131 BE_BR_IMASK_ACNTEXP | 1132 BE_BR_IMASK_CCNTEXP | 1133 BE_BR_IMASK_LCNTEXP | 1134 BE_BR_IMASK_CVCNTEXP | 1135 BE_BR_IMASK_SENTFRAME | 1136 BE_BR_IMASK_NCNTEXP | 1137 BE_BR_IMASK_ECNTEXP | 1138 BE_BR_IMASK_LCCNTEXP | 1139 BE_BR_IMASK_FCNTEXP | 1140 BE_BR_IMASK_DTIMEXP); 1141 1142 /* Channel registers: */ 1143 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1144 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1145 1146 qecaddr = sc->sc_channel * qec->sc_msize; 1147 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1148 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1149 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1150 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1151 1152 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1153 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1154 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1155 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1156 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1157 1158 /* Enable transmitter */ 1159 bus_space_write_4(t, br, BE_BRI_TXCFG, 1160 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1161 1162 /* Enable receiver */ 1163 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1164 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1165 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1166 1167 ifp->if_flags |= IFF_RUNNING; 1168 ifp->if_flags &= ~IFF_OACTIVE; 1169 1170 be_ifmedia_upd(ifp); 1171 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1172 splx(s); 1173 } 1174 1175 void 1176 be_mcreset(sc) 1177 struct be_softc *sc; 1178 { 1179 struct ethercom *ec = &sc->sc_ethercom; 1180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181 bus_space_tag_t t = sc->sc_bustag; 1182 bus_space_handle_t br = sc->sc_br; 1183 u_int32_t crc; 1184 u_int16_t hash[4]; 1185 u_int8_t octet; 1186 u_int32_t v; 1187 int i, j; 1188 struct ether_multi *enm; 1189 struct ether_multistep step; 1190 1191 if (ifp->if_flags & IFF_PROMISC) { 1192 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1193 v |= BE_BR_RXCFG_PMISC; 1194 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1195 return; 1196 } 1197 1198 if (ifp->if_flags & IFF_ALLMULTI) { 1199 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1200 goto chipit; 1201 } 1202 1203 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1204 1205 ETHER_FIRST_MULTI(step, ec, enm); 1206 while (enm != NULL) { 1207 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1208 /* 1209 * We must listen to a range of multicast 1210 * addresses. For now, just accept all 1211 * multicasts, rather than trying to set only 1212 * those filter bits needed to match the range. 1213 * (At this time, the only use of address 1214 * ranges is for IP multicast routing, for 1215 * which the range is big enough to require 1216 * all bits set.) 1217 */ 1218 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1219 ifp->if_flags |= IFF_ALLMULTI; 1220 goto chipit; 1221 } 1222 1223 crc = 0xffffffff; 1224 1225 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1226 octet = enm->enm_addrlo[i]; 1227 1228 for (j = 0; j < 8; j++) { 1229 if ((crc & 1) ^ (octet & 1)) { 1230 crc >>= 1; 1231 crc ^= MC_POLY_LE; 1232 } 1233 else 1234 crc >>= 1; 1235 octet >>= 1; 1236 } 1237 } 1238 1239 crc >>= 26; 1240 hash[crc >> 4] |= 1 << (crc & 0xf); 1241 ETHER_NEXT_MULTI(step, enm); 1242 } 1243 1244 ifp->if_flags &= ~IFF_ALLMULTI; 1245 1246 chipit: 1247 /* Enable the hash filter */ 1248 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1249 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1250 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1251 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1252 1253 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1254 v &= ~BE_BR_RXCFG_PMISC; 1255 v |= BE_BR_RXCFG_HENABLE; 1256 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1257 } 1258 1259 /* 1260 * Set the tcvr to an idle state 1261 */ 1262 void 1263 be_mii_sync(sc) 1264 struct be_softc *sc; 1265 { 1266 bus_space_tag_t t = sc->sc_bustag; 1267 bus_space_handle_t tr = sc->sc_tr; 1268 int n = 32; 1269 1270 while (n--) { 1271 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1272 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1273 MGMT_PAL_OENAB); 1274 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1275 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1276 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1277 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1278 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1279 } 1280 } 1281 1282 void 1283 be_pal_gate(sc, phy) 1284 struct be_softc *sc; 1285 int phy; 1286 { 1287 bus_space_tag_t t = sc->sc_bustag; 1288 bus_space_handle_t tr = sc->sc_tr; 1289 u_int32_t v; 1290 1291 be_mii_sync(sc); 1292 1293 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1294 if (phy == BE_PHY_INTERNAL) 1295 v &= ~TCVR_PAL_SERIAL; 1296 1297 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1298 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1299 } 1300 1301 static int 1302 be_tcvr_read_bit(sc, phy) 1303 struct be_softc *sc; 1304 int phy; 1305 { 1306 bus_space_tag_t t = sc->sc_bustag; 1307 bus_space_handle_t tr = sc->sc_tr; 1308 int ret; 1309 1310 if (phy == BE_PHY_INTERNAL) { 1311 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1312 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1313 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1314 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1315 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1316 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1317 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1318 } else { 1319 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1320 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1321 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1322 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1323 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1324 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1325 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1326 } 1327 1328 return (ret); 1329 } 1330 1331 static void 1332 be_tcvr_write_bit(sc, phy, bit) 1333 struct be_softc *sc; 1334 int phy; 1335 int bit; 1336 { 1337 bus_space_tag_t t = sc->sc_bustag; 1338 bus_space_handle_t tr = sc->sc_tr; 1339 u_int32_t v; 1340 1341 if (phy == BE_PHY_INTERNAL) { 1342 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1343 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1344 } else { 1345 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1346 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1347 } 1348 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1349 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1350 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1351 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1352 } 1353 1354 static void 1355 be_mii_sendbits(sc, phy, data, nbits) 1356 struct be_softc *sc; 1357 int phy; 1358 u_int32_t data; 1359 int nbits; 1360 { 1361 int i; 1362 1363 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1364 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1365 } 1366 } 1367 1368 static int 1369 be_mii_readreg(self, phy, reg) 1370 struct device *self; 1371 int phy, reg; 1372 { 1373 struct be_softc *sc = (struct be_softc *)self; 1374 int val = 0, i; 1375 1376 /* 1377 * Read the PHY register by manually driving the MII control lines. 1378 */ 1379 be_mii_sync(sc); 1380 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1381 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1382 be_mii_sendbits(sc, phy, phy, 5); 1383 be_mii_sendbits(sc, phy, reg, 5); 1384 1385 (void) be_tcvr_read_bit(sc, phy); 1386 (void) be_tcvr_read_bit(sc, phy); 1387 1388 for (i = 15; i >= 0; i--) 1389 val |= (be_tcvr_read_bit(sc, phy) << i); 1390 1391 (void) be_tcvr_read_bit(sc, phy); 1392 (void) be_tcvr_read_bit(sc, phy); 1393 (void) be_tcvr_read_bit(sc, phy); 1394 1395 return (val); 1396 } 1397 1398 void 1399 be_mii_writereg(self, phy, reg, val) 1400 struct device *self; 1401 int phy, reg, val; 1402 { 1403 struct be_softc *sc = (struct be_softc *)self; 1404 int i; 1405 1406 /* 1407 * Write the PHY register by manually driving the MII control lines. 1408 */ 1409 be_mii_sync(sc); 1410 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1411 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1412 be_mii_sendbits(sc, phy, phy, 5); 1413 be_mii_sendbits(sc, phy, reg, 5); 1414 1415 be_tcvr_write_bit(sc, phy, 1); 1416 be_tcvr_write_bit(sc, phy, 0); 1417 1418 for (i = 15; i >= 0; i--) 1419 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1420 } 1421 1422 int 1423 be_mii_reset(sc, phy) 1424 struct be_softc *sc; 1425 int phy; 1426 { 1427 int n; 1428 1429 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1430 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1431 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1432 1433 for (n = 16; n >= 0; n--) { 1434 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1435 if ((bmcr & BMCR_RESET) == 0) 1436 break; 1437 DELAY(20); 1438 } 1439 if (n == 0) { 1440 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1441 return (EIO); 1442 } 1443 1444 return (0); 1445 } 1446 1447 void 1448 be_tick(arg) 1449 void *arg; 1450 { 1451 struct be_softc *sc = arg; 1452 int s = splnet(); 1453 1454 mii_tick(&sc->sc_mii); 1455 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1456 1457 splx(s); 1458 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1459 } 1460 1461 void 1462 be_mii_statchg(self) 1463 struct device *self; 1464 { 1465 struct be_softc *sc = (struct be_softc *)self; 1466 bus_space_tag_t t = sc->sc_bustag; 1467 bus_space_handle_t br = sc->sc_br; 1468 u_int instance; 1469 u_int32_t v; 1470 1471 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1472 #ifdef DIAGNOSTIC 1473 if (instance > 1) 1474 panic("be_mii_statchg: instance %d out of range", instance); 1475 #endif 1476 1477 /* Update duplex mode in TX configuration */ 1478 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1479 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1480 v |= BE_BR_TXCFG_FULLDPLX; 1481 else 1482 v &= ~BE_BR_TXCFG_FULLDPLX; 1483 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1484 1485 /* Change to appropriate gate in transceiver PAL */ 1486 be_pal_gate(sc, sc->sc_phys[instance]); 1487 } 1488 1489 /* 1490 * Get current media settings. 1491 */ 1492 void 1493 be_ifmedia_sts(ifp, ifmr) 1494 struct ifnet *ifp; 1495 struct ifmediareq *ifmr; 1496 { 1497 struct be_softc *sc = ifp->if_softc; 1498 1499 mii_pollstat(&sc->sc_mii); 1500 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1501 1502 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1503 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1504 return; 1505 } 1506 1507 /* 1508 * Set media options. 1509 */ 1510 int 1511 be_ifmedia_upd(ifp) 1512 struct ifnet *ifp; 1513 { 1514 struct be_softc *sc = ifp->if_softc; 1515 int error; 1516 1517 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1518 return (error); 1519 1520 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1521 } 1522 1523 /* 1524 * Service routine for our pseudo-MII internal transceiver. 1525 */ 1526 int 1527 be_intphy_service(sc, mii, cmd) 1528 struct be_softc *sc; 1529 struct mii_data *mii; 1530 int cmd; 1531 { 1532 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1533 int bmcr, bmsr; 1534 int error; 1535 1536 switch (cmd) { 1537 case MII_POLLSTAT: 1538 /* 1539 * If we're not polling our PHY instance, just return. 1540 */ 1541 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1542 return (0); 1543 1544 break; 1545 1546 case MII_MEDIACHG: 1547 1548 /* 1549 * If the media indicates a different PHY instance, 1550 * isolate ourselves. 1551 */ 1552 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1553 bmcr = be_mii_readreg((void *)sc, 1554 BE_PHY_INTERNAL, MII_BMCR); 1555 be_mii_writereg((void *)sc, 1556 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1557 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1558 sc->sc_intphy_curspeed = 0; 1559 return (0); 1560 } 1561 1562 1563 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1564 return (error); 1565 1566 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1567 1568 /* 1569 * Select the new mode and take out of isolation 1570 */ 1571 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1572 bmcr |= BMCR_S100; 1573 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1574 bmcr &= ~BMCR_S100; 1575 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1576 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1577 bmcr &= ~BMCR_S100; 1578 bmcr |= sc->sc_intphy_curspeed; 1579 } else { 1580 /* Keep isolated until link is up */ 1581 bmcr |= BMCR_ISO; 1582 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1583 } 1584 } 1585 1586 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1587 bmcr |= BMCR_FDX; 1588 else 1589 bmcr &= ~BMCR_FDX; 1590 1591 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1592 break; 1593 1594 case MII_TICK: 1595 /* 1596 * If we're not currently selected, just return. 1597 */ 1598 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1599 return (0); 1600 1601 /* Only used for automatic media selection */ 1602 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1603 return (0); 1604 1605 /* Is the interface even up? */ 1606 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1607 return (0); 1608 1609 /* 1610 * Check link status; if we don't have a link, try another 1611 * speed. We can't detect duplex mode, so half-duplex is 1612 * what we have to settle for. 1613 */ 1614 1615 /* Read twice in case the register is latched */ 1616 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1617 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1618 1619 if ((bmsr & BMSR_LINK) != 0) { 1620 /* We have a carrier */ 1621 bmcr = be_mii_readreg((void *)sc, 1622 BE_PHY_INTERNAL, MII_BMCR); 1623 1624 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1625 bmcr = be_mii_readreg((void *)sc, 1626 BE_PHY_INTERNAL, MII_BMCR); 1627 1628 sc->sc_mii_flags |= MIIF_HAVELINK; 1629 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1630 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1631 1632 bmcr &= ~BMCR_ISO; 1633 be_mii_writereg((void *)sc, 1634 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1635 1636 printf("%s: link up at %s Mbps\n", 1637 sc->sc_dev.dv_xname, 1638 (bmcr & BMCR_S100) ? "100" : "10"); 1639 } 1640 return (0); 1641 } 1642 1643 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1644 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1645 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1646 sc->sc_intphy_curspeed = 0; 1647 printf("%s: link down\n", sc->sc_dev.dv_xname); 1648 } 1649 1650 /* Only retry autonegotiation every 5 seconds. */ 1651 if (++sc->sc_mii_ticks < 5) 1652 return(0); 1653 1654 sc->sc_mii_ticks = 0; 1655 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1656 /* Just flip the fast speed bit */ 1657 bmcr ^= BMCR_S100; 1658 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1659 1660 break; 1661 1662 case MII_DOWN: 1663 /* Isolate this phy */ 1664 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1665 be_mii_writereg((void *)sc, 1666 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1667 return (0); 1668 } 1669 1670 /* Update the media status. */ 1671 be_intphy_status(sc); 1672 1673 /* Callback if something changed. */ 1674 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1675 (*mii->mii_statchg)((struct device *)sc); 1676 sc->sc_mii_active = mii->mii_media_active; 1677 } 1678 return (0); 1679 } 1680 1681 /* 1682 * Determine status of internal transceiver 1683 */ 1684 void 1685 be_intphy_status(sc) 1686 struct be_softc *sc; 1687 { 1688 struct mii_data *mii = &sc->sc_mii; 1689 int media_active, media_status; 1690 int bmcr, bmsr; 1691 1692 media_status = IFM_AVALID; 1693 media_active = 0; 1694 1695 /* 1696 * Internal transceiver; do the work here. 1697 */ 1698 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1699 1700 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1701 case (BMCR_S100 | BMCR_FDX): 1702 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1703 break; 1704 case BMCR_S100: 1705 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1706 break; 1707 case BMCR_FDX: 1708 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1709 break; 1710 case 0: 1711 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1712 break; 1713 } 1714 1715 /* Read twice in case the register is latched */ 1716 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1717 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1718 if (bmsr & BMSR_LINK) 1719 media_status |= IFM_ACTIVE; 1720 1721 mii->mii_media_status = media_status; 1722 mii->mii_media_active = media_active; 1723 } 1724
Indexes created Sat Oct 25 16:10:12 GMT 2025