be.c revision 1.25
1 /* $NetBSD: be.c,v 1.25 2001/03/08 02:20:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include "opt_ddb.h" 67 #include "opt_inet.h" 68 #include "opt_ccitt.h" 69 #include "opt_llc.h" 70 #include "opt_ns.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 #ifdef NS 105 #include <netns/ns.h> 106 #include <netns/ns_if.h> 107 #endif 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #include <net/bpfdesc.h> 112 #endif 113 114 #include <machine/bus.h> 115 #include <machine/intr.h> 116 #include <machine/autoconf.h> 117 118 #include <dev/sbus/sbusvar.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/miivar.h> 122 123 #include <dev/sbus/qecreg.h> 124 #include <dev/sbus/qecvar.h> 125 #include <dev/sbus/bereg.h> 126 127 struct be_softc { 128 struct device sc_dev; 129 struct sbusdev sc_sd; /* sbus device */ 130 bus_space_tag_t sc_bustag; /* bus & dma tags */ 131 bus_dma_tag_t sc_dmatag; 132 bus_dmamap_t sc_dmamap; 133 struct ethercom sc_ethercom; 134 /*struct ifmedia sc_ifmedia; -* interface media */ 135 struct mii_data sc_mii; /* MII media control */ 136 #define sc_media sc_mii.mii_media/* shorthand */ 137 int sc_phys[2]; /* MII instance -> phy */ 138 139 struct callout sc_tick_ch; 140 141 /* 142 * Some `mii_softc' items we need to emulate MII operation 143 * for our internal transceiver. 144 */ 145 int sc_mii_inst; /* instance of internal phy */ 146 int sc_mii_active; /* currently active medium */ 147 int sc_mii_ticks; /* tick counter */ 148 int sc_mii_flags; /* phy status flags */ 149 #define MIIF_HAVELINK 0x04000000 150 int sc_intphy_curspeed; /* Established link speed */ 151 152 struct qec_softc *sc_qec; /* QEC parent */ 153 154 bus_space_handle_t sc_qr; /* QEC registers */ 155 bus_space_handle_t sc_br; /* BE registers */ 156 bus_space_handle_t sc_cr; /* channel registers */ 157 bus_space_handle_t sc_tr; /* transceiver registers */ 158 159 u_int sc_rev; 160 161 int sc_channel; /* channel number */ 162 int sc_burst; 163 164 struct qec_ring sc_rb; /* Packet Ring Buffer */ 165 166 /* MAC address */ 167 u_int8_t sc_enaddr[6]; 168 }; 169 170 int bematch __P((struct device *, struct cfdata *, void *)); 171 void beattach __P((struct device *, struct device *, void *)); 172 173 void beinit __P((struct be_softc *)); 174 void bestart __P((struct ifnet *)); 175 void bestop __P((struct be_softc *)); 176 void bewatchdog __P((struct ifnet *)); 177 int beioctl __P((struct ifnet *, u_long, caddr_t)); 178 void bereset __P((struct be_softc *)); 179 180 int beintr __P((void *)); 181 int berint __P((struct be_softc *)); 182 int betint __P((struct be_softc *)); 183 int beqint __P((struct be_softc *, u_int32_t)); 184 int beeint __P((struct be_softc *, u_int32_t)); 185 186 static void be_read __P((struct be_softc *, int, int)); 187 static int be_put __P((struct be_softc *, int, struct mbuf *)); 188 static struct mbuf *be_get __P((struct be_softc *, int, int)); 189 190 void be_pal_gate __P((struct be_softc *, int)); 191 192 /* ifmedia callbacks */ 193 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 194 int be_ifmedia_upd __P((struct ifnet *)); 195 196 void be_mcreset __P((struct be_softc *)); 197 198 /* MII methods & callbacks */ 199 static int be_mii_readreg __P((struct device *, int, int)); 200 static void be_mii_writereg __P((struct device *, int, int, int)); 201 static void be_mii_statchg __P((struct device *)); 202 203 /* MII helpers */ 204 static void be_mii_sync __P((struct be_softc *)); 205 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 206 static int be_mii_reset __P((struct be_softc *, int)); 207 static int be_tcvr_read_bit __P((struct be_softc *, int)); 208 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 209 210 void be_tick __P((void *)); 211 void be_intphy_auto __P((struct be_softc *)); 212 void be_intphy_status __P((struct be_softc *)); 213 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 214 215 216 struct cfattach be_ca = { 217 sizeof(struct be_softc), bematch, beattach 218 }; 219 220 int 221 bematch(parent, cf, aux) 222 struct device *parent; 223 struct cfdata *cf; 224 void *aux; 225 { 226 struct sbus_attach_args *sa = aux; 227 228 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 229 } 230 231 void 232 beattach(parent, self, aux) 233 struct device *parent, *self; 234 void *aux; 235 { 236 struct sbus_attach_args *sa = aux; 237 struct qec_softc *qec = (struct qec_softc *)parent; 238 struct be_softc *sc = (struct be_softc *)self; 239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 240 struct mii_data *mii = &sc->sc_mii; 241 struct mii_softc *child; 242 int node = sa->sa_node; 243 bus_dma_tag_t dmatag = sa->sa_dmatag; 244 bus_dma_segment_t seg; 245 bus_size_t size; 246 int instance; 247 int rseg, error; 248 u_int32_t v; 249 extern void myetheraddr __P((u_char *)); 250 251 if (sa->sa_nreg < 3) { 252 printf("%s: only %d register sets\n", 253 self->dv_xname, sa->sa_nreg); 254 return; 255 } 256 257 if (bus_space_map2(sa->sa_bustag, 258 (bus_type_t)sa->sa_reg[0].sbr_slot, 259 (bus_addr_t)sa->sa_reg[0].sbr_offset, 260 (bus_size_t)sa->sa_reg[0].sbr_size, 261 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_cr) != 0) { 262 printf("beattach: cannot map registers\n"); 263 return; 264 } 265 266 if (bus_space_map2(sa->sa_bustag, 267 (bus_type_t)sa->sa_reg[1].sbr_slot, 268 (bus_addr_t)sa->sa_reg[1].sbr_offset, 269 (bus_size_t)sa->sa_reg[1].sbr_size, 270 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_br) != 0) { 271 printf("beattach: cannot map registers\n"); 272 return; 273 } 274 275 if (bus_space_map2(sa->sa_bustag, 276 (bus_type_t)sa->sa_reg[2].sbr_slot, 277 (bus_addr_t)sa->sa_reg[2].sbr_offset, 278 (bus_size_t)sa->sa_reg[2].sbr_size, 279 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_tr) != 0) { 280 printf("beattach: cannot map registers\n"); 281 return; 282 } 283 284 sc->sc_qec = qec; 285 sc->sc_qr = qec->sc_regs; 286 287 sc->sc_rev = getpropint(node, "board-version", -1); 288 printf(" rev %x", sc->sc_rev); 289 290 bestop(sc); 291 292 sc->sc_channel = getpropint(node, "channel#", -1); 293 if (sc->sc_channel == -1) 294 sc->sc_channel = 0; 295 296 sc->sc_burst = getpropint(node, "burst-sizes", -1); 297 if (sc->sc_burst == -1) 298 sc->sc_burst = qec->sc_burst; 299 300 /* Clamp at parent's burst sizes */ 301 sc->sc_burst &= qec->sc_burst; 302 303 /* Establish interrupt handler */ 304 if (sa->sa_nintr) 305 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 306 0, beintr, sc); 307 308 myetheraddr(sc->sc_enaddr); 309 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 310 311 /* 312 * Allocate descriptor ring and buffers. 313 */ 314 315 /* for now, allocate as many bufs as there are ring descriptors */ 316 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 317 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 318 319 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 320 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 321 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 322 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 323 324 /* Get a DMA handle */ 325 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 326 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 327 printf("%s: DMA map create error %d\n", self->dv_xname, error); 328 return; 329 } 330 331 /* Allocate DMA buffer */ 332 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 333 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 334 printf("%s: DMA buffer alloc error %d\n", 335 self->dv_xname, error); 336 return; 337 } 338 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 339 340 /* Map DMA memory in CPU addressable space */ 341 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 342 &sc->sc_rb.rb_membase, 343 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 344 printf("%s: DMA buffer map error %d\n", 345 self->dv_xname, error); 346 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 347 return; 348 } 349 350 /* Load the buffer */ 351 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 352 sc->sc_rb.rb_membase, size, NULL, 353 BUS_DMA_NOWAIT)) != 0) { 354 printf("%s: DMA buffer map load error %d\n", 355 self->dv_xname, error); 356 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 357 bus_dmamem_free(dmatag, &seg, rseg); 358 return; 359 } 360 361 /* 362 * Initialize our media structures and MII info. 363 */ 364 mii->mii_ifp = ifp; 365 mii->mii_readreg = be_mii_readreg; 366 mii->mii_writereg = be_mii_writereg; 367 mii->mii_statchg = be_mii_statchg; 368 369 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 370 371 callout_init(&sc->sc_tick_ch); 372 373 /* 374 * Initialize transceiver and determine which PHY connection to use. 375 */ 376 be_mii_sync(sc); 377 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 378 379 instance = 0; 380 381 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 382 383 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 384 MII_OFFSET_ANY, 0); 385 386 child = LIST_FIRST(&mii->mii_phys); 387 if (child == NULL) { 388 /* No PHY attached */ 389 ifmedia_add(&sc->sc_media, 390 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 391 0, NULL); 392 ifmedia_set(&sc->sc_media, 393 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 394 } else { 395 /* 396 * Note: we support just one PHY on the external 397 * MII connector. 398 */ 399 #ifdef DIAGNOSTIC 400 if (LIST_NEXT(child, mii_list) != NULL) { 401 printf("%s: spurious MII device %s attached\n", 402 sc->sc_dev.dv_xname, 403 child->mii_dev.dv_xname); 404 } 405 #endif 406 if (child->mii_phy != BE_PHY_EXTERNAL || 407 child->mii_inst > 0) { 408 printf("%s: cannot accomodate MII device %s" 409 " at phy %d, instance %d\n", 410 sc->sc_dev.dv_xname, 411 child->mii_dev.dv_xname, 412 child->mii_phy, child->mii_inst); 413 } else { 414 sc->sc_phys[instance] = child->mii_phy; 415 } 416 417 /* 418 * XXX - we can really do the following ONLY if the 419 * phy indeed has the auto negotiation capability!! 420 */ 421 ifmedia_set(&sc->sc_media, 422 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 423 424 /* Mark our current media setting */ 425 be_pal_gate(sc, BE_PHY_EXTERNAL); 426 instance++; 427 } 428 429 } 430 431 if ((v & MGMT_PAL_INT_MDIO) != 0) { 432 /* 433 * The be internal phy looks vaguely like MII hardware, 434 * but not enough to be able to use the MII device 435 * layer. Hence, we have to take care of media selection 436 * ourselves. 437 */ 438 439 sc->sc_mii_inst = instance; 440 sc->sc_phys[instance] = BE_PHY_INTERNAL; 441 442 /* Use `ifm_data' to store BMCR bits */ 443 ifmedia_add(&sc->sc_media, 444 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 445 0, NULL); 446 ifmedia_add(&sc->sc_media, 447 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 448 BMCR_S100, NULL); 449 ifmedia_add(&sc->sc_media, 450 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 451 0, NULL); 452 453 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 454 self->dv_xname); 455 456 be_mii_reset(sc, BE_PHY_INTERNAL); 457 /* Only set default medium here if there's no external PHY */ 458 if (instance == 0) { 459 be_pal_gate(sc, BE_PHY_INTERNAL); 460 ifmedia_set(&sc->sc_media, 461 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 462 } else 463 be_mii_writereg((void *)sc, 464 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 465 } 466 467 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 468 ifp->if_softc = sc; 469 ifp->if_start = bestart; 470 ifp->if_ioctl = beioctl; 471 ifp->if_watchdog = bewatchdog; 472 ifp->if_flags = 473 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 474 IFQ_SET_READY(&ifp->if_snd); 475 476 /* Attach the interface. */ 477 if_attach(ifp); 478 ether_ifattach(ifp, sc->sc_enaddr); 479 } 480 481 482 /* 483 * Routine to copy from mbuf chain to transmit buffer in 484 * network buffer memory. 485 */ 486 static __inline__ int 487 be_put(sc, idx, m) 488 struct be_softc *sc; 489 int idx; 490 struct mbuf *m; 491 { 492 struct mbuf *n; 493 int len, tlen = 0, boff = 0; 494 caddr_t bp; 495 496 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 497 498 for (; m; m = n) { 499 len = m->m_len; 500 if (len == 0) { 501 MFREE(m, n); 502 continue; 503 } 504 bcopy(mtod(m, caddr_t), bp+boff, len); 505 boff += len; 506 tlen += len; 507 MFREE(m, n); 508 } 509 return (tlen); 510 } 511 512 /* 513 * Pull data off an interface. 514 * Len is the length of data, with local net header stripped. 515 * We copy the data into mbufs. When full cluster sized units are present, 516 * we copy into clusters. 517 */ 518 static __inline__ struct mbuf * 519 be_get(sc, idx, totlen) 520 struct be_softc *sc; 521 int idx, totlen; 522 { 523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 524 struct mbuf *m; 525 struct mbuf *top, **mp; 526 int len, pad, boff = 0; 527 caddr_t bp; 528 529 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 530 531 MGETHDR(m, M_DONTWAIT, MT_DATA); 532 if (m == NULL) 533 return (NULL); 534 m->m_pkthdr.rcvif = ifp; 535 m->m_pkthdr.len = totlen; 536 537 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 538 m->m_data += pad; 539 len = MHLEN - pad; 540 top = NULL; 541 mp = ⊤ 542 543 while (totlen > 0) { 544 if (top) { 545 MGET(m, M_DONTWAIT, MT_DATA); 546 if (m == NULL) { 547 m_freem(top); 548 return (NULL); 549 } 550 len = MLEN; 551 } 552 if (top && totlen >= MINCLSIZE) { 553 MCLGET(m, M_DONTWAIT); 554 if (m->m_flags & M_EXT) 555 len = MCLBYTES; 556 } 557 m->m_len = len = min(totlen, len); 558 bcopy(bp + boff, mtod(m, caddr_t), len); 559 boff += len; 560 totlen -= len; 561 *mp = m; 562 mp = &m->m_next; 563 } 564 565 return (top); 566 } 567 568 /* 569 * Pass a packet to the higher levels. 570 */ 571 static __inline__ void 572 be_read(sc, idx, len) 573 struct be_softc *sc; 574 int idx, len; 575 { 576 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 577 struct mbuf *m; 578 579 if (len <= sizeof(struct ether_header) || 580 len > ETHERMTU + sizeof(struct ether_header)) { 581 582 printf("%s: invalid packet size %d; dropping\n", 583 ifp->if_xname, len); 584 585 ifp->if_ierrors++; 586 return; 587 } 588 589 /* 590 * Pull packet off interface. 591 */ 592 m = be_get(sc, idx, len); 593 if (m == NULL) { 594 ifp->if_ierrors++; 595 return; 596 } 597 ifp->if_ipackets++; 598 599 #if NBPFILTER > 0 600 /* 601 * Check if there's a BPF listener on this interface. 602 * If so, hand off the raw packet to BPF. 603 */ 604 if (ifp->if_bpf) 605 bpf_mtap(ifp->if_bpf, m); 606 #endif 607 /* Pass the packet up. */ 608 (*ifp->if_input)(ifp, m); 609 } 610 611 /* 612 * Start output on interface. 613 * We make two assumptions here: 614 * 1) that the current priority is set to splnet _before_ this code 615 * is called *and* is returned to the appropriate priority after 616 * return 617 * 2) that the IFF_OACTIVE flag is checked before this code is called 618 * (i.e. that the output part of the interface is idle) 619 */ 620 void 621 bestart(ifp) 622 struct ifnet *ifp; 623 { 624 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 625 struct qec_xd *txd = sc->sc_rb.rb_txd; 626 struct mbuf *m; 627 unsigned int bix, len; 628 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 629 630 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 631 return; 632 633 bix = sc->sc_rb.rb_tdhead; 634 635 for (;;) { 636 IFQ_DEQUEUE(&ifp->if_snd, m); 637 if (m == 0) 638 break; 639 640 #if NBPFILTER > 0 641 /* 642 * If BPF is listening on this interface, let it see the 643 * packet before we commit it to the wire. 644 */ 645 if (ifp->if_bpf) 646 bpf_mtap(ifp->if_bpf, m); 647 #endif 648 649 /* 650 * Copy the mbuf chain into the transmit buffer. 651 */ 652 len = be_put(sc, bix, m); 653 654 /* 655 * Initialize transmit registers and start transmission 656 */ 657 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 658 (len & QEC_XD_LENGTH); 659 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 660 BE_CR_CTRL_TWAKEUP); 661 662 if (++bix == QEC_XD_RING_MAXSIZE) 663 bix = 0; 664 665 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 666 ifp->if_flags |= IFF_OACTIVE; 667 break; 668 } 669 } 670 671 sc->sc_rb.rb_tdhead = bix; 672 } 673 674 void 675 bestop(sc) 676 struct be_softc *sc; 677 { 678 int n; 679 bus_space_tag_t t = sc->sc_bustag; 680 bus_space_handle_t br = sc->sc_br; 681 682 callout_stop(&sc->sc_tick_ch); 683 684 /* Down the MII. */ 685 mii_down(&sc->sc_mii); 686 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 687 688 /* Stop the transmitter */ 689 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 690 for (n = 32; n > 0; n--) { 691 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 692 break; 693 DELAY(20); 694 } 695 696 /* Stop the receiver */ 697 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 698 for (n = 32; n > 0; n--) { 699 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 700 break; 701 DELAY(20); 702 } 703 } 704 705 /* 706 * Reset interface. 707 */ 708 void 709 bereset(sc) 710 struct be_softc *sc; 711 { 712 int s; 713 714 s = splnet(); 715 bestop(sc); 716 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 717 beinit(sc); 718 splx(s); 719 } 720 721 void 722 bewatchdog(ifp) 723 struct ifnet *ifp; 724 { 725 struct be_softc *sc = ifp->if_softc; 726 727 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 728 ++sc->sc_ethercom.ec_if.if_oerrors; 729 730 bereset(sc); 731 } 732 733 int 734 beintr(v) 735 void *v; 736 { 737 struct be_softc *sc = (struct be_softc *)v; 738 bus_space_tag_t t = sc->sc_bustag; 739 u_int32_t whyq, whyb, whyc; 740 int r = 0; 741 742 /* Read QEC status, channel status and BE status */ 743 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 744 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 745 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 746 747 if (whyq & QEC_STAT_BM) 748 r |= beeint(sc, whyb); 749 750 if (whyq & QEC_STAT_ER) 751 r |= beqint(sc, whyc); 752 753 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 754 r |= betint(sc); 755 756 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 757 r |= berint(sc); 758 759 return (r); 760 } 761 762 /* 763 * QEC Interrupt. 764 */ 765 int 766 beqint(sc, why) 767 struct be_softc *sc; 768 u_int32_t why; 769 { 770 int r = 0, rst = 0; 771 772 if (why & BE_CR_STAT_TXIRQ) 773 r |= 1; 774 if (why & BE_CR_STAT_RXIRQ) 775 r |= 1; 776 777 if (why & BE_CR_STAT_BERROR) { 778 r |= 1; 779 rst = 1; 780 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 781 } 782 783 if (why & BE_CR_STAT_TXDERR) { 784 r |= 1; 785 rst = 1; 786 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 787 } 788 789 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 790 r |= 1; 791 rst = 1; 792 printf("%s: tx dma error ( ", sc->sc_dev.dv_xname); 793 if (why & BE_CR_STAT_TXLERR) 794 printf("Late "); 795 if (why & BE_CR_STAT_TXPERR) 796 printf("Parity "); 797 if (why & BE_CR_STAT_TXSERR) 798 printf("Generic "); 799 printf(")\n"); 800 } 801 802 if (why & BE_CR_STAT_RXDROP) { 803 r |= 1; 804 rst = 1; 805 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 806 } 807 808 if (why & BE_CR_STAT_RXSMALL) { 809 r |= 1; 810 rst = 1; 811 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 812 } 813 814 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 815 r |= 1; 816 rst = 1; 817 printf("%s: rx dma error ( ", sc->sc_dev.dv_xname); 818 if (why & BE_CR_STAT_RXLERR) 819 printf("Late "); 820 if (why & BE_CR_STAT_RXPERR) 821 printf("Parity "); 822 if (why & BE_CR_STAT_RXSERR) 823 printf("Generic "); 824 printf(")\n"); 825 } 826 827 if (!r) { 828 rst = 1; 829 printf("%s: unexpected error interrupt %08x\n", 830 sc->sc_dev.dv_xname, why); 831 } 832 833 if (rst) { 834 printf("%s: resetting\n", sc->sc_dev.dv_xname); 835 bereset(sc); 836 } 837 838 return (r); 839 } 840 841 /* 842 * Error interrupt. 843 */ 844 int 845 beeint(sc, why) 846 struct be_softc *sc; 847 u_int32_t why; 848 { 849 int r = 0, rst = 0; 850 851 if (why & BE_BR_STAT_RFIFOVF) { 852 r |= 1; 853 rst = 1; 854 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 855 } 856 if (why & BE_BR_STAT_TFIFO_UND) { 857 r |= 1; 858 rst = 1; 859 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 860 } 861 if (why & BE_BR_STAT_MAXPKTERR) { 862 r |= 1; 863 rst = 1; 864 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 865 } 866 867 if (!r) { 868 rst = 1; 869 printf("%s: unexpected error interrupt %08x\n", 870 sc->sc_dev.dv_xname, why); 871 } 872 873 if (rst) { 874 printf("%s: resetting\n", sc->sc_dev.dv_xname); 875 bereset(sc); 876 } 877 878 return (r); 879 } 880 881 /* 882 * Transmit interrupt. 883 */ 884 int 885 betint(sc) 886 struct be_softc *sc; 887 { 888 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 889 bus_space_tag_t t = sc->sc_bustag; 890 bus_space_handle_t br = sc->sc_br; 891 unsigned int bix, txflags; 892 893 /* 894 * Unload collision counters 895 */ 896 ifp->if_collisions += 897 bus_space_read_4(t, br, BE_BRI_NCCNT) + 898 bus_space_read_4(t, br, BE_BRI_FCCNT) + 899 bus_space_read_4(t, br, BE_BRI_EXCNT) + 900 bus_space_read_4(t, br, BE_BRI_LTCNT); 901 902 /* 903 * the clear the hardware counters 904 */ 905 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 906 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 907 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 908 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 909 910 bix = sc->sc_rb.rb_tdtail; 911 912 for (;;) { 913 if (sc->sc_rb.rb_td_nbusy <= 0) 914 break; 915 916 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 917 918 if (txflags & QEC_XD_OWN) 919 break; 920 921 ifp->if_flags &= ~IFF_OACTIVE; 922 ifp->if_opackets++; 923 924 if (++bix == QEC_XD_RING_MAXSIZE) 925 bix = 0; 926 927 --sc->sc_rb.rb_td_nbusy; 928 } 929 930 sc->sc_rb.rb_tdtail = bix; 931 932 bestart(ifp); 933 934 if (sc->sc_rb.rb_td_nbusy == 0) 935 ifp->if_timer = 0; 936 937 return (1); 938 } 939 940 /* 941 * Receive interrupt. 942 */ 943 int 944 berint(sc) 945 struct be_softc *sc; 946 { 947 struct qec_xd *xd = sc->sc_rb.rb_rxd; 948 unsigned int bix, len; 949 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 950 951 bix = sc->sc_rb.rb_rdtail; 952 953 /* 954 * Process all buffers with valid data. 955 */ 956 for (;;) { 957 len = xd[bix].xd_flags; 958 if (len & QEC_XD_OWN) 959 break; 960 961 len &= QEC_XD_LENGTH; 962 be_read(sc, bix, len); 963 964 /* ... */ 965 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 966 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 967 968 if (++bix == QEC_XD_RING_MAXSIZE) 969 bix = 0; 970 } 971 972 sc->sc_rb.rb_rdtail = bix; 973 974 return (1); 975 } 976 977 int 978 beioctl(ifp, cmd, data) 979 struct ifnet *ifp; 980 u_long cmd; 981 caddr_t data; 982 { 983 struct be_softc *sc = ifp->if_softc; 984 struct ifaddr *ifa = (struct ifaddr *)data; 985 struct ifreq *ifr = (struct ifreq *)data; 986 int s, error = 0; 987 988 s = splnet(); 989 990 switch (cmd) { 991 case SIOCSIFADDR: 992 ifp->if_flags |= IFF_UP; 993 switch (ifa->ifa_addr->sa_family) { 994 #ifdef INET 995 case AF_INET: 996 beinit(sc); 997 arp_ifinit(ifp, ifa); 998 break; 999 #endif /* INET */ 1000 #ifdef NS 1001 case AF_NS: 1002 { 1003 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1004 1005 if (ns_nullhost(*ina)) 1006 ina->x_host = 1007 *(union ns_host *)LLADDR(ifp->if_sadl); 1008 else 1009 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1010 sizeof(sc->sc_enaddr)); 1011 /* Set new address. */ 1012 beinit(sc); 1013 break; 1014 } 1015 #endif /* NS */ 1016 default: 1017 beinit(sc); 1018 break; 1019 } 1020 break; 1021 1022 case SIOCSIFFLAGS: 1023 if ((ifp->if_flags & IFF_UP) == 0 && 1024 (ifp->if_flags & IFF_RUNNING) != 0) { 1025 /* 1026 * If interface is marked down and it is running, then 1027 * stop it. 1028 */ 1029 bestop(sc); 1030 ifp->if_flags &= ~IFF_RUNNING; 1031 } else if ((ifp->if_flags & IFF_UP) != 0 && 1032 (ifp->if_flags & IFF_RUNNING) == 0) { 1033 /* 1034 * If interface is marked up and it is stopped, then 1035 * start it. 1036 */ 1037 beinit(sc); 1038 } else { 1039 /* 1040 * Reset the interface to pick up changes in any other 1041 * flags that affect hardware registers. 1042 */ 1043 bestop(sc); 1044 beinit(sc); 1045 } 1046 #ifdef BEDEBUG 1047 if (ifp->if_flags & IFF_DEBUG) 1048 sc->sc_debug = 1; 1049 else 1050 sc->sc_debug = 0; 1051 #endif 1052 break; 1053 1054 case SIOCADDMULTI: 1055 case SIOCDELMULTI: 1056 error = (cmd == SIOCADDMULTI) ? 1057 ether_addmulti(ifr, &sc->sc_ethercom): 1058 ether_delmulti(ifr, &sc->sc_ethercom); 1059 1060 if (error == ENETRESET) { 1061 /* 1062 * Multicast list has changed; set the hardware filter 1063 * accordingly. 1064 */ 1065 be_mcreset(sc); 1066 error = 0; 1067 } 1068 break; 1069 case SIOCGIFMEDIA: 1070 case SIOCSIFMEDIA: 1071 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1072 break; 1073 default: 1074 error = EINVAL; 1075 break; 1076 } 1077 splx(s); 1078 return (error); 1079 } 1080 1081 1082 void 1083 beinit(sc) 1084 struct be_softc *sc; 1085 { 1086 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1087 bus_space_tag_t t = sc->sc_bustag; 1088 bus_space_handle_t br = sc->sc_br; 1089 bus_space_handle_t cr = sc->sc_cr; 1090 struct qec_softc *qec = sc->sc_qec; 1091 u_int32_t v; 1092 u_int32_t qecaddr; 1093 u_int8_t *ea; 1094 int s; 1095 1096 s = splnet(); 1097 1098 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1099 1100 bestop(sc); 1101 1102 ea = sc->sc_enaddr; 1103 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1104 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1105 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1106 1107 /* Clear hash table */ 1108 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1109 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1110 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1111 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1112 1113 /* Re-initialize RX configuration */ 1114 v = BE_BR_RXCFG_FIFO; 1115 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1116 1117 be_mcreset(sc); 1118 1119 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1120 1121 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1122 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1123 1124 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1125 1126 /* 1127 * Turn off counter expiration interrupts as well as 1128 * 'gotframe' and 'sentframe' 1129 */ 1130 bus_space_write_4(t, br, BE_BRI_IMASK, 1131 BE_BR_IMASK_GOTFRAME | 1132 BE_BR_IMASK_RCNTEXP | 1133 BE_BR_IMASK_ACNTEXP | 1134 BE_BR_IMASK_CCNTEXP | 1135 BE_BR_IMASK_LCNTEXP | 1136 BE_BR_IMASK_CVCNTEXP | 1137 BE_BR_IMASK_SENTFRAME | 1138 BE_BR_IMASK_NCNTEXP | 1139 BE_BR_IMASK_ECNTEXP | 1140 BE_BR_IMASK_LCCNTEXP | 1141 BE_BR_IMASK_FCNTEXP | 1142 BE_BR_IMASK_DTIMEXP); 1143 1144 /* Channel registers: */ 1145 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1146 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1147 1148 qecaddr = sc->sc_channel * qec->sc_msize; 1149 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1150 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1151 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1152 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1153 1154 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1155 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1156 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1157 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1158 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1159 1160 /* Enable transmitter */ 1161 bus_space_write_4(t, br, BE_BRI_TXCFG, 1162 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1163 1164 /* Enable receiver */ 1165 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1166 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1167 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1168 1169 ifp->if_flags |= IFF_RUNNING; 1170 ifp->if_flags &= ~IFF_OACTIVE; 1171 1172 be_ifmedia_upd(ifp); 1173 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1174 splx(s); 1175 } 1176 1177 void 1178 be_mcreset(sc) 1179 struct be_softc *sc; 1180 { 1181 struct ethercom *ec = &sc->sc_ethercom; 1182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1183 bus_space_tag_t t = sc->sc_bustag; 1184 bus_space_handle_t br = sc->sc_br; 1185 u_int32_t crc; 1186 u_int16_t hash[4]; 1187 u_int8_t octet; 1188 u_int32_t v; 1189 int i, j; 1190 struct ether_multi *enm; 1191 struct ether_multistep step; 1192 1193 if (ifp->if_flags & IFF_PROMISC) { 1194 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1195 v |= BE_BR_RXCFG_PMISC; 1196 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1197 return; 1198 } 1199 1200 if (ifp->if_flags & IFF_ALLMULTI) { 1201 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1202 goto chipit; 1203 } 1204 1205 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1206 1207 ETHER_FIRST_MULTI(step, ec, enm); 1208 while (enm != NULL) { 1209 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1210 /* 1211 * We must listen to a range of multicast 1212 * addresses. For now, just accept all 1213 * multicasts, rather than trying to set only 1214 * those filter bits needed to match the range. 1215 * (At this time, the only use of address 1216 * ranges is for IP multicast routing, for 1217 * which the range is big enough to require 1218 * all bits set.) 1219 */ 1220 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1221 ifp->if_flags |= IFF_ALLMULTI; 1222 goto chipit; 1223 } 1224 1225 crc = 0xffffffff; 1226 1227 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1228 octet = enm->enm_addrlo[i]; 1229 1230 for (j = 0; j < 8; j++) { 1231 if ((crc & 1) ^ (octet & 1)) { 1232 crc >>= 1; 1233 crc ^= MC_POLY_LE; 1234 } 1235 else 1236 crc >>= 1; 1237 octet >>= 1; 1238 } 1239 } 1240 1241 crc >>= 26; 1242 hash[crc >> 4] |= 1 << (crc & 0xf); 1243 ETHER_NEXT_MULTI(step, enm); 1244 } 1245 1246 ifp->if_flags &= ~IFF_ALLMULTI; 1247 1248 chipit: 1249 /* Enable the hash filter */ 1250 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1251 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1252 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1253 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1254 1255 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1256 v &= ~BE_BR_RXCFG_PMISC; 1257 v |= BE_BR_RXCFG_HENABLE; 1258 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1259 } 1260 1261 /* 1262 * Set the tcvr to an idle state 1263 */ 1264 void 1265 be_mii_sync(sc) 1266 struct be_softc *sc; 1267 { 1268 bus_space_tag_t t = sc->sc_bustag; 1269 bus_space_handle_t tr = sc->sc_tr; 1270 int n = 32; 1271 1272 while (n--) { 1273 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1274 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1275 MGMT_PAL_OENAB); 1276 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1277 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1278 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1279 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1280 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1281 } 1282 } 1283 1284 void 1285 be_pal_gate(sc, phy) 1286 struct be_softc *sc; 1287 int phy; 1288 { 1289 bus_space_tag_t t = sc->sc_bustag; 1290 bus_space_handle_t tr = sc->sc_tr; 1291 u_int32_t v; 1292 1293 be_mii_sync(sc); 1294 1295 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1296 if (phy == BE_PHY_INTERNAL) 1297 v &= ~TCVR_PAL_SERIAL; 1298 1299 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1300 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1301 } 1302 1303 static int 1304 be_tcvr_read_bit(sc, phy) 1305 struct be_softc *sc; 1306 int phy; 1307 { 1308 bus_space_tag_t t = sc->sc_bustag; 1309 bus_space_handle_t tr = sc->sc_tr; 1310 int ret; 1311 1312 if (phy == BE_PHY_INTERNAL) { 1313 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1314 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1315 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1316 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1317 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1318 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1319 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1320 } else { 1321 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1322 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1323 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1324 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1325 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1326 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1327 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1328 } 1329 1330 return (ret); 1331 } 1332 1333 static void 1334 be_tcvr_write_bit(sc, phy, bit) 1335 struct be_softc *sc; 1336 int phy; 1337 int bit; 1338 { 1339 bus_space_tag_t t = sc->sc_bustag; 1340 bus_space_handle_t tr = sc->sc_tr; 1341 u_int32_t v; 1342 1343 if (phy == BE_PHY_INTERNAL) { 1344 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1345 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1346 } else { 1347 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1348 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1349 } 1350 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1351 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1352 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1353 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1354 } 1355 1356 static void 1357 be_mii_sendbits(sc, phy, data, nbits) 1358 struct be_softc *sc; 1359 int phy; 1360 u_int32_t data; 1361 int nbits; 1362 { 1363 int i; 1364 1365 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1366 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1367 } 1368 } 1369 1370 static int 1371 be_mii_readreg(self, phy, reg) 1372 struct device *self; 1373 int phy, reg; 1374 { 1375 struct be_softc *sc = (struct be_softc *)self; 1376 int val = 0, i; 1377 1378 /* 1379 * Read the PHY register by manually driving the MII control lines. 1380 */ 1381 be_mii_sync(sc); 1382 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1383 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1384 be_mii_sendbits(sc, phy, phy, 5); 1385 be_mii_sendbits(sc, phy, reg, 5); 1386 1387 (void) be_tcvr_read_bit(sc, phy); 1388 (void) be_tcvr_read_bit(sc, phy); 1389 1390 for (i = 15; i >= 0; i--) 1391 val |= (be_tcvr_read_bit(sc, phy) << i); 1392 1393 (void) be_tcvr_read_bit(sc, phy); 1394 (void) be_tcvr_read_bit(sc, phy); 1395 (void) be_tcvr_read_bit(sc, phy); 1396 1397 return (val); 1398 } 1399 1400 void 1401 be_mii_writereg(self, phy, reg, val) 1402 struct device *self; 1403 int phy, reg, val; 1404 { 1405 struct be_softc *sc = (struct be_softc *)self; 1406 int i; 1407 1408 /* 1409 * Write the PHY register by manually driving the MII control lines. 1410 */ 1411 be_mii_sync(sc); 1412 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1413 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1414 be_mii_sendbits(sc, phy, phy, 5); 1415 be_mii_sendbits(sc, phy, reg, 5); 1416 1417 be_tcvr_write_bit(sc, phy, 1); 1418 be_tcvr_write_bit(sc, phy, 0); 1419 1420 for (i = 15; i >= 0; i--) 1421 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1422 } 1423 1424 int 1425 be_mii_reset(sc, phy) 1426 struct be_softc *sc; 1427 int phy; 1428 { 1429 int n; 1430 1431 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1432 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1433 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1434 1435 for (n = 16; n >= 0; n--) { 1436 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1437 if ((bmcr & BMCR_RESET) == 0) 1438 break; 1439 DELAY(20); 1440 } 1441 if (n == 0) { 1442 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1443 return (EIO); 1444 } 1445 1446 return (0); 1447 } 1448 1449 void 1450 be_tick(arg) 1451 void *arg; 1452 { 1453 struct be_softc *sc = arg; 1454 int s = splnet(); 1455 1456 mii_tick(&sc->sc_mii); 1457 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1458 1459 splx(s); 1460 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1461 } 1462 1463 void 1464 be_mii_statchg(self) 1465 struct device *self; 1466 { 1467 struct be_softc *sc = (struct be_softc *)self; 1468 bus_space_tag_t t = sc->sc_bustag; 1469 bus_space_handle_t br = sc->sc_br; 1470 u_int instance; 1471 u_int32_t v; 1472 1473 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1474 #ifdef DIAGNOSTIC 1475 if (instance > 1) 1476 panic("be_mii_statchg: instance %d out of range", instance); 1477 #endif 1478 1479 /* Update duplex mode in TX configuration */ 1480 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1481 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1482 v |= BE_BR_TXCFG_FULLDPLX; 1483 else 1484 v &= ~BE_BR_TXCFG_FULLDPLX; 1485 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1486 1487 /* Change to appropriate gate in transceiver PAL */ 1488 be_pal_gate(sc, sc->sc_phys[instance]); 1489 } 1490 1491 /* 1492 * Get current media settings. 1493 */ 1494 void 1495 be_ifmedia_sts(ifp, ifmr) 1496 struct ifnet *ifp; 1497 struct ifmediareq *ifmr; 1498 { 1499 struct be_softc *sc = ifp->if_softc; 1500 1501 mii_pollstat(&sc->sc_mii); 1502 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1503 1504 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1505 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1506 return; 1507 } 1508 1509 /* 1510 * Set media options. 1511 */ 1512 int 1513 be_ifmedia_upd(ifp) 1514 struct ifnet *ifp; 1515 { 1516 struct be_softc *sc = ifp->if_softc; 1517 int error; 1518 1519 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1520 return (error); 1521 1522 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1523 } 1524 1525 /* 1526 * Service routine for our pseudo-MII internal transceiver. 1527 */ 1528 int 1529 be_intphy_service(sc, mii, cmd) 1530 struct be_softc *sc; 1531 struct mii_data *mii; 1532 int cmd; 1533 { 1534 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1535 int bmcr, bmsr; 1536 int error; 1537 1538 switch (cmd) { 1539 case MII_POLLSTAT: 1540 /* 1541 * If we're not polling our PHY instance, just return. 1542 */ 1543 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1544 return (0); 1545 1546 break; 1547 1548 case MII_MEDIACHG: 1549 1550 /* 1551 * If the media indicates a different PHY instance, 1552 * isolate ourselves. 1553 */ 1554 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1555 bmcr = be_mii_readreg((void *)sc, 1556 BE_PHY_INTERNAL, MII_BMCR); 1557 be_mii_writereg((void *)sc, 1558 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1559 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1560 sc->sc_intphy_curspeed = 0; 1561 return (0); 1562 } 1563 1564 1565 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1566 return (error); 1567 1568 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1569 1570 /* 1571 * Select the new mode and take out of isolation 1572 */ 1573 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1574 bmcr |= BMCR_S100; 1575 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1576 bmcr &= ~BMCR_S100; 1577 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1578 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1579 bmcr &= ~BMCR_S100; 1580 bmcr |= sc->sc_intphy_curspeed; 1581 } else { 1582 /* Keep isolated until link is up */ 1583 bmcr |= BMCR_ISO; 1584 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1585 } 1586 } 1587 1588 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1589 bmcr |= BMCR_FDX; 1590 else 1591 bmcr &= ~BMCR_FDX; 1592 1593 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1594 break; 1595 1596 case MII_TICK: 1597 /* 1598 * If we're not currently selected, just return. 1599 */ 1600 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1601 return (0); 1602 1603 /* Only used for automatic media selection */ 1604 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1605 return (0); 1606 1607 /* Is the interface even up? */ 1608 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1609 return (0); 1610 1611 /* 1612 * Check link status; if we don't have a link, try another 1613 * speed. We can't detect duplex mode, so half-duplex is 1614 * what we have to settle for. 1615 */ 1616 1617 /* Read twice in case the register is latched */ 1618 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1619 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1620 1621 if ((bmsr & BMSR_LINK) != 0) { 1622 /* We have a carrier */ 1623 bmcr = be_mii_readreg((void *)sc, 1624 BE_PHY_INTERNAL, MII_BMCR); 1625 1626 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1627 bmcr = be_mii_readreg((void *)sc, 1628 BE_PHY_INTERNAL, MII_BMCR); 1629 1630 sc->sc_mii_flags |= MIIF_HAVELINK; 1631 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1632 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1633 1634 bmcr &= ~BMCR_ISO; 1635 be_mii_writereg((void *)sc, 1636 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1637 1638 printf("%s: link up at %s Mbps\n", 1639 sc->sc_dev.dv_xname, 1640 (bmcr & BMCR_S100) ? "100" : "10"); 1641 } 1642 return (0); 1643 } 1644 1645 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1646 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1647 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1648 sc->sc_intphy_curspeed = 0; 1649 printf("%s: link down\n", sc->sc_dev.dv_xname); 1650 } 1651 1652 /* Only retry autonegotiation every 5 seconds. */ 1653 if (++sc->sc_mii_ticks < 5) 1654 return(0); 1655 1656 sc->sc_mii_ticks = 0; 1657 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1658 /* Just flip the fast speed bit */ 1659 bmcr ^= BMCR_S100; 1660 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1661 1662 break; 1663 1664 case MII_DOWN: 1665 /* Isolate this phy */ 1666 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1667 be_mii_writereg((void *)sc, 1668 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1669 return (0); 1670 } 1671 1672 /* Update the media status. */ 1673 be_intphy_status(sc); 1674 1675 /* Callback if something changed. */ 1676 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1677 (*mii->mii_statchg)((struct device *)sc); 1678 sc->sc_mii_active = mii->mii_media_active; 1679 } 1680 return (0); 1681 } 1682 1683 /* 1684 * Determine status of internal transceiver 1685 */ 1686 void 1687 be_intphy_status(sc) 1688 struct be_softc *sc; 1689 { 1690 struct mii_data *mii = &sc->sc_mii; 1691 int media_active, media_status; 1692 int bmcr, bmsr; 1693 1694 media_status = IFM_AVALID; 1695 media_active = 0; 1696 1697 /* 1698 * Internal transceiver; do the work here. 1699 */ 1700 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1701 1702 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1703 case (BMCR_S100 | BMCR_FDX): 1704 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1705 break; 1706 case BMCR_S100: 1707 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1708 break; 1709 case BMCR_FDX: 1710 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1711 break; 1712 case 0: 1713 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1714 break; 1715 } 1716 1717 /* Read twice in case the register is latched */ 1718 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1719 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1720 if (bmsr & BMSR_LINK) 1721 media_status |= IFM_ACTIVE; 1722 1723 mii->mii_media_status = media_status; 1724 mii->mii_media_active = media_active; 1725 } 1726
Indexes created Tue Sep 30 07:10:03 GMT 2025