be.c revision 1.40
1 /* $NetBSD: be.c,v 1.40 2003/10/16 07:20:54 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.40 2003/10/16 07:20:54 pk Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_inet.h" 71 #include "opt_ccitt.h" 72 #include "opt_llc.h" 73 #include "opt_ns.h" 74 #include "bpfilter.h" 75 #include "rnd.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/callout.h> 80 #include <sys/kernel.h> 81 #include <sys/errno.h> 82 #include <sys/ioctl.h> 83 #include <sys/mbuf.h> 84 #include <sys/socket.h> 85 #include <sys/syslog.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #if NRND > 0 89 #include <sys/rnd.h> 90 #endif 91 92 #include <net/if.h> 93 #include <net/if_dl.h> 94 #include <net/if_types.h> 95 #include <net/netisr.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_inarp.h> 102 #include <netinet/in_systm.h> 103 #include <netinet/in_var.h> 104 #include <netinet/ip.h> 105 #endif 106 107 #ifdef NS 108 #include <netns/ns.h> 109 #include <netns/ns_if.h> 110 #endif 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #include <net/bpfdesc.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 #include <machine/autoconf.h> 120 121 #include <dev/sbus/sbusvar.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/sbus/qecreg.h> 127 #include <dev/sbus/qecvar.h> 128 #include <dev/sbus/bereg.h> 129 130 struct be_softc { 131 struct device sc_dev; 132 struct sbusdev sc_sd; /* sbus device */ 133 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 134 bus_dma_tag_t sc_dmatag; 135 bus_dmamap_t sc_dmamap; 136 struct ethercom sc_ethercom; 137 /*struct ifmedia sc_ifmedia; -* interface media */ 138 struct mii_data sc_mii; /* MII media control */ 139 #define sc_media sc_mii.mii_media/* shorthand */ 140 int sc_phys[2]; /* MII instance -> phy */ 141 142 struct callout sc_tick_ch; 143 144 /* 145 * Some `mii_softc' items we need to emulate MII operation 146 * for our internal transceiver. 147 */ 148 int sc_mii_inst; /* instance of internal phy */ 149 int sc_mii_active; /* currently active medium */ 150 int sc_mii_ticks; /* tick counter */ 151 int sc_mii_flags; /* phy status flags */ 152 #define MIIF_HAVELINK 0x04000000 153 int sc_intphy_curspeed; /* Established link speed */ 154 155 struct qec_softc *sc_qec; /* QEC parent */ 156 157 bus_space_handle_t sc_qr; /* QEC registers */ 158 bus_space_handle_t sc_br; /* BE registers */ 159 bus_space_handle_t sc_cr; /* channel registers */ 160 bus_space_handle_t sc_tr; /* transceiver registers */ 161 162 u_int sc_rev; 163 164 int sc_channel; /* channel number */ 165 int sc_burst; 166 167 struct qec_ring sc_rb; /* Packet Ring Buffer */ 168 169 /* MAC address */ 170 u_int8_t sc_enaddr[6]; 171 }; 172 173 int bematch __P((struct device *, struct cfdata *, void *)); 174 void beattach __P((struct device *, struct device *, void *)); 175 176 void beinit __P((struct be_softc *)); 177 void bestart __P((struct ifnet *)); 178 void bestop __P((struct be_softc *)); 179 void bewatchdog __P((struct ifnet *)); 180 int beioctl __P((struct ifnet *, u_long, caddr_t)); 181 void bereset __P((struct be_softc *)); 182 183 int beintr __P((void *)); 184 int berint __P((struct be_softc *)); 185 int betint __P((struct be_softc *)); 186 int beqint __P((struct be_softc *, u_int32_t)); 187 int beeint __P((struct be_softc *, u_int32_t)); 188 189 static void be_read __P((struct be_softc *, int, int)); 190 static int be_put __P((struct be_softc *, int, struct mbuf *)); 191 static struct mbuf *be_get __P((struct be_softc *, int, int)); 192 193 void be_pal_gate __P((struct be_softc *, int)); 194 195 /* ifmedia callbacks */ 196 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 197 int be_ifmedia_upd __P((struct ifnet *)); 198 199 void be_mcreset __P((struct be_softc *)); 200 201 /* MII methods & callbacks */ 202 static int be_mii_readreg __P((struct device *, int, int)); 203 static void be_mii_writereg __P((struct device *, int, int, int)); 204 static void be_mii_statchg __P((struct device *)); 205 206 /* MII helpers */ 207 static void be_mii_sync __P((struct be_softc *)); 208 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 209 static int be_mii_reset __P((struct be_softc *, int)); 210 static int be_tcvr_read_bit __P((struct be_softc *, int)); 211 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 212 213 void be_tick __P((void *)); 214 void be_intphy_auto __P((struct be_softc *)); 215 void be_intphy_status __P((struct be_softc *)); 216 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 217 218 219 CFATTACH_DECL(be, sizeof(struct be_softc), 220 bematch, beattach, NULL, NULL); 221 222 int 223 bematch(parent, cf, aux) 224 struct device *parent; 225 struct cfdata *cf; 226 void *aux; 227 { 228 struct sbus_attach_args *sa = aux; 229 230 return (strcmp(cf->cf_name, sa->sa_name) == 0); 231 } 232 233 void 234 beattach(parent, self, aux) 235 struct device *parent, *self; 236 void *aux; 237 { 238 struct sbus_attach_args *sa = aux; 239 struct qec_softc *qec = (struct qec_softc *)parent; 240 struct be_softc *sc = (struct be_softc *)self; 241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 242 struct mii_data *mii = &sc->sc_mii; 243 struct mii_softc *child; 244 int node = sa->sa_node; 245 bus_dma_tag_t dmatag = sa->sa_dmatag; 246 bus_dma_segment_t seg; 247 bus_size_t size; 248 int instance; 249 int rseg, error; 250 u_int32_t v; 251 extern void myetheraddr __P((u_char *)); 252 253 if (sa->sa_nreg < 3) { 254 printf("%s: only %d register sets\n", 255 self->dv_xname, sa->sa_nreg); 256 return; 257 } 258 259 if (bus_space_map(sa->sa_bustag, 260 (bus_addr_t)BUS_ADDR( 261 sa->sa_reg[0].oa_space, 262 sa->sa_reg[0].oa_base), 263 (bus_size_t)sa->sa_reg[0].oa_size, 264 0, &sc->sc_cr) != 0) { 265 printf("beattach: cannot map registers\n"); 266 return; 267 } 268 269 if (bus_space_map(sa->sa_bustag, 270 (bus_addr_t)BUS_ADDR( 271 sa->sa_reg[1].oa_space, 272 sa->sa_reg[1].oa_base), 273 (bus_size_t)sa->sa_reg[1].oa_size, 274 0, &sc->sc_br) != 0) { 275 printf("beattach: cannot map registers\n"); 276 return; 277 } 278 279 if (bus_space_map(sa->sa_bustag, 280 (bus_addr_t)BUS_ADDR( 281 sa->sa_reg[2].oa_space, 282 sa->sa_reg[2].oa_base), 283 (bus_size_t)sa->sa_reg[2].oa_size, 284 0, &sc->sc_tr) != 0) { 285 printf("beattach: cannot map registers\n"); 286 return; 287 } 288 289 sc->sc_bustag = sa->sa_bustag; 290 sc->sc_qec = qec; 291 sc->sc_qr = qec->sc_regs; 292 293 sc->sc_rev = PROM_getpropint(node, "board-version", -1); 294 printf(" rev %x", sc->sc_rev); 295 296 bestop(sc); 297 298 sc->sc_channel = PROM_getpropint(node, "channel#", -1); 299 if (sc->sc_channel == -1) 300 sc->sc_channel = 0; 301 302 sc->sc_burst = PROM_getpropint(node, "burst-sizes", -1); 303 if (sc->sc_burst == -1) 304 sc->sc_burst = qec->sc_burst; 305 306 /* Clamp at parent's burst sizes */ 307 sc->sc_burst &= qec->sc_burst; 308 309 /* Establish interrupt handler */ 310 if (sa->sa_nintr) 311 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 312 beintr, sc); 313 314 myetheraddr(sc->sc_enaddr); 315 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 316 317 /* 318 * Allocate descriptor ring and buffers. 319 */ 320 321 /* for now, allocate as many bufs as there are ring descriptors */ 322 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 323 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 324 325 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 326 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 327 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 328 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 329 330 /* Get a DMA handle */ 331 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 332 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 333 printf("%s: DMA map create error %d\n", self->dv_xname, error); 334 return; 335 } 336 337 /* Allocate DMA buffer */ 338 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 339 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 340 printf("%s: DMA buffer alloc error %d\n", 341 self->dv_xname, error); 342 return; 343 } 344 345 /* Map DMA memory in CPU addressable space */ 346 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 347 &sc->sc_rb.rb_membase, 348 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 349 printf("%s: DMA buffer map error %d\n", 350 self->dv_xname, error); 351 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 352 return; 353 } 354 355 /* Load the buffer */ 356 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 357 sc->sc_rb.rb_membase, size, NULL, 358 BUS_DMA_NOWAIT)) != 0) { 359 printf("%s: DMA buffer map load error %d\n", 360 self->dv_xname, error); 361 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 362 bus_dmamem_free(dmatag, &seg, rseg); 363 return; 364 } 365 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 366 367 /* 368 * Initialize our media structures and MII info. 369 */ 370 mii->mii_ifp = ifp; 371 mii->mii_readreg = be_mii_readreg; 372 mii->mii_writereg = be_mii_writereg; 373 mii->mii_statchg = be_mii_statchg; 374 375 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 376 377 callout_init(&sc->sc_tick_ch); 378 379 /* 380 * Initialize transceiver and determine which PHY connection to use. 381 */ 382 be_mii_sync(sc); 383 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 384 385 instance = 0; 386 387 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 388 389 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 390 MII_OFFSET_ANY, 0); 391 392 child = LIST_FIRST(&mii->mii_phys); 393 if (child == NULL) { 394 /* No PHY attached */ 395 ifmedia_add(&sc->sc_media, 396 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 397 0, NULL); 398 ifmedia_set(&sc->sc_media, 399 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 400 } else { 401 /* 402 * Note: we support just one PHY on the external 403 * MII connector. 404 */ 405 #ifdef DIAGNOSTIC 406 if (LIST_NEXT(child, mii_list) != NULL) { 407 printf("%s: spurious MII device %s attached\n", 408 sc->sc_dev.dv_xname, 409 child->mii_dev.dv_xname); 410 } 411 #endif 412 if (child->mii_phy != BE_PHY_EXTERNAL || 413 child->mii_inst > 0) { 414 printf("%s: cannot accomodate MII device %s" 415 " at phy %d, instance %d\n", 416 sc->sc_dev.dv_xname, 417 child->mii_dev.dv_xname, 418 child->mii_phy, child->mii_inst); 419 } else { 420 sc->sc_phys[instance] = child->mii_phy; 421 } 422 423 /* 424 * XXX - we can really do the following ONLY if the 425 * phy indeed has the auto negotiation capability!! 426 */ 427 ifmedia_set(&sc->sc_media, 428 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 429 430 /* Mark our current media setting */ 431 be_pal_gate(sc, BE_PHY_EXTERNAL); 432 instance++; 433 } 434 435 } 436 437 if ((v & MGMT_PAL_INT_MDIO) != 0) { 438 /* 439 * The be internal phy looks vaguely like MII hardware, 440 * but not enough to be able to use the MII device 441 * layer. Hence, we have to take care of media selection 442 * ourselves. 443 */ 444 445 sc->sc_mii_inst = instance; 446 sc->sc_phys[instance] = BE_PHY_INTERNAL; 447 448 /* Use `ifm_data' to store BMCR bits */ 449 ifmedia_add(&sc->sc_media, 450 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 451 0, NULL); 452 ifmedia_add(&sc->sc_media, 453 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 454 BMCR_S100, NULL); 455 ifmedia_add(&sc->sc_media, 456 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 457 0, NULL); 458 459 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 460 self->dv_xname); 461 462 be_mii_reset(sc, BE_PHY_INTERNAL); 463 /* Only set default medium here if there's no external PHY */ 464 if (instance == 0) { 465 be_pal_gate(sc, BE_PHY_INTERNAL); 466 ifmedia_set(&sc->sc_media, 467 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 468 } else 469 be_mii_writereg((void *)sc, 470 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 471 } 472 473 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 474 ifp->if_softc = sc; 475 ifp->if_start = bestart; 476 ifp->if_ioctl = beioctl; 477 ifp->if_watchdog = bewatchdog; 478 ifp->if_flags = 479 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 480 IFQ_SET_READY(&ifp->if_snd); 481 482 /* claim 802.1q capability */ 483 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 484 485 /* Attach the interface. */ 486 if_attach(ifp); 487 ether_ifattach(ifp, sc->sc_enaddr); 488 } 489 490 491 /* 492 * Routine to copy from mbuf chain to transmit buffer in 493 * network buffer memory. 494 */ 495 static __inline__ int 496 be_put(sc, idx, m) 497 struct be_softc *sc; 498 int idx; 499 struct mbuf *m; 500 { 501 struct mbuf *n; 502 int len, tlen = 0, boff = 0; 503 caddr_t bp; 504 505 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 506 507 for (; m; m = n) { 508 len = m->m_len; 509 if (len == 0) { 510 MFREE(m, n); 511 continue; 512 } 513 bcopy(mtod(m, caddr_t), bp+boff, len); 514 boff += len; 515 tlen += len; 516 MFREE(m, n); 517 } 518 return (tlen); 519 } 520 521 /* 522 * Pull data off an interface. 523 * Len is the length of data, with local net header stripped. 524 * We copy the data into mbufs. When full cluster sized units are present, 525 * we copy into clusters. 526 */ 527 static __inline__ struct mbuf * 528 be_get(sc, idx, totlen) 529 struct be_softc *sc; 530 int idx, totlen; 531 { 532 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 533 struct mbuf *m; 534 struct mbuf *top, **mp; 535 int len, pad, boff = 0; 536 caddr_t bp; 537 538 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 539 540 MGETHDR(m, M_DONTWAIT, MT_DATA); 541 if (m == NULL) 542 return (NULL); 543 m->m_pkthdr.rcvif = ifp; 544 m->m_pkthdr.len = totlen; 545 546 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 547 m->m_data += pad; 548 len = MHLEN - pad; 549 top = NULL; 550 mp = ⊤ 551 552 while (totlen > 0) { 553 if (top) { 554 MGET(m, M_DONTWAIT, MT_DATA); 555 if (m == NULL) { 556 m_freem(top); 557 return (NULL); 558 } 559 len = MLEN; 560 } 561 if (top && totlen >= MINCLSIZE) { 562 MCLGET(m, M_DONTWAIT); 563 if (m->m_flags & M_EXT) 564 len = MCLBYTES; 565 } 566 m->m_len = len = min(totlen, len); 567 bcopy(bp + boff, mtod(m, caddr_t), len); 568 boff += len; 569 totlen -= len; 570 *mp = m; 571 mp = &m->m_next; 572 } 573 574 return (top); 575 } 576 577 /* 578 * Pass a packet to the higher levels. 579 */ 580 static __inline__ void 581 be_read(sc, idx, len) 582 struct be_softc *sc; 583 int idx, len; 584 { 585 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 586 struct mbuf *m; 587 588 #ifdef DIAGNOSTIC 589 if (len < ETHER_MIN_LEN || len > ETHER_MAX_LEN + ETHERCAP_VLAN_MTU) { 590 printf("%s: invalid packet size %d; dropping\n", 591 ifp->if_xname, len); 592 ifp->if_ierrors++; 593 return; 594 } 595 #endif 596 597 /* 598 * Pull packet off interface. 599 */ 600 m = be_get(sc, idx, len); 601 if (m == NULL) { 602 ifp->if_ierrors++; 603 return; 604 } 605 ifp->if_ipackets++; 606 607 #if NBPFILTER > 0 608 /* 609 * Check if there's a BPF listener on this interface. 610 * If so, hand off the raw packet to BPF. 611 */ 612 if (ifp->if_bpf) 613 bpf_mtap(ifp->if_bpf, m); 614 #endif 615 /* Pass the packet up. */ 616 (*ifp->if_input)(ifp, m); 617 } 618 619 /* 620 * Start output on interface. 621 * We make two assumptions here: 622 * 1) that the current priority is set to splnet _before_ this code 623 * is called *and* is returned to the appropriate priority after 624 * return 625 * 2) that the IFF_OACTIVE flag is checked before this code is called 626 * (i.e. that the output part of the interface is idle) 627 */ 628 void 629 bestart(ifp) 630 struct ifnet *ifp; 631 { 632 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 633 struct qec_xd *txd = sc->sc_rb.rb_txd; 634 struct mbuf *m; 635 unsigned int bix, len; 636 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 637 638 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 639 return; 640 641 bix = sc->sc_rb.rb_tdhead; 642 643 for (;;) { 644 IFQ_DEQUEUE(&ifp->if_snd, m); 645 if (m == 0) 646 break; 647 648 #if NBPFILTER > 0 649 /* 650 * If BPF is listening on this interface, let it see the 651 * packet before we commit it to the wire. 652 */ 653 if (ifp->if_bpf) 654 bpf_mtap(ifp->if_bpf, m); 655 #endif 656 657 /* 658 * Copy the mbuf chain into the transmit buffer. 659 */ 660 len = be_put(sc, bix, m); 661 662 /* 663 * Initialize transmit registers and start transmission 664 */ 665 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 666 (len & QEC_XD_LENGTH); 667 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 668 BE_CR_CTRL_TWAKEUP); 669 670 if (++bix == QEC_XD_RING_MAXSIZE) 671 bix = 0; 672 673 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 674 ifp->if_flags |= IFF_OACTIVE; 675 break; 676 } 677 } 678 679 sc->sc_rb.rb_tdhead = bix; 680 } 681 682 void 683 bestop(sc) 684 struct be_softc *sc; 685 { 686 int n; 687 bus_space_tag_t t = sc->sc_bustag; 688 bus_space_handle_t br = sc->sc_br; 689 690 callout_stop(&sc->sc_tick_ch); 691 692 /* Down the MII. */ 693 mii_down(&sc->sc_mii); 694 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 695 696 /* Stop the transmitter */ 697 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 698 for (n = 32; n > 0; n--) { 699 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 700 break; 701 DELAY(20); 702 } 703 704 /* Stop the receiver */ 705 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 706 for (n = 32; n > 0; n--) { 707 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 708 break; 709 DELAY(20); 710 } 711 } 712 713 /* 714 * Reset interface. 715 */ 716 void 717 bereset(sc) 718 struct be_softc *sc; 719 { 720 int s; 721 722 s = splnet(); 723 bestop(sc); 724 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 725 beinit(sc); 726 splx(s); 727 } 728 729 void 730 bewatchdog(ifp) 731 struct ifnet *ifp; 732 { 733 struct be_softc *sc = ifp->if_softc; 734 735 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 736 ++sc->sc_ethercom.ec_if.if_oerrors; 737 738 bereset(sc); 739 } 740 741 int 742 beintr(v) 743 void *v; 744 { 745 struct be_softc *sc = (struct be_softc *)v; 746 bus_space_tag_t t = sc->sc_bustag; 747 u_int32_t whyq, whyb, whyc; 748 int r = 0; 749 750 /* Read QEC status, channel status and BE status */ 751 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 752 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 753 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 754 755 if (whyq & QEC_STAT_BM) 756 r |= beeint(sc, whyb); 757 758 if (whyq & QEC_STAT_ER) 759 r |= beqint(sc, whyc); 760 761 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 762 r |= betint(sc); 763 764 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 765 r |= berint(sc); 766 767 return (r); 768 } 769 770 /* 771 * QEC Interrupt. 772 */ 773 int 774 beqint(sc, why) 775 struct be_softc *sc; 776 u_int32_t why; 777 { 778 int r = 0, rst = 0; 779 780 if (why & BE_CR_STAT_TXIRQ) 781 r |= 1; 782 if (why & BE_CR_STAT_RXIRQ) 783 r |= 1; 784 785 if (why & BE_CR_STAT_BERROR) { 786 r |= 1; 787 rst = 1; 788 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 789 } 790 791 if (why & BE_CR_STAT_TXDERR) { 792 r |= 1; 793 rst = 1; 794 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 795 } 796 797 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 798 r |= 1; 799 rst = 1; 800 printf("%s: tx DMA error ( ", sc->sc_dev.dv_xname); 801 if (why & BE_CR_STAT_TXLERR) 802 printf("Late "); 803 if (why & BE_CR_STAT_TXPERR) 804 printf("Parity "); 805 if (why & BE_CR_STAT_TXSERR) 806 printf("Generic "); 807 printf(")\n"); 808 } 809 810 if (why & BE_CR_STAT_RXDROP) { 811 r |= 1; 812 rst = 1; 813 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 814 } 815 816 if (why & BE_CR_STAT_RXSMALL) { 817 r |= 1; 818 rst = 1; 819 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 820 } 821 822 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 823 r |= 1; 824 rst = 1; 825 printf("%s: rx DMA error ( ", sc->sc_dev.dv_xname); 826 if (why & BE_CR_STAT_RXLERR) 827 printf("Late "); 828 if (why & BE_CR_STAT_RXPERR) 829 printf("Parity "); 830 if (why & BE_CR_STAT_RXSERR) 831 printf("Generic "); 832 printf(")\n"); 833 } 834 835 if (!r) { 836 rst = 1; 837 printf("%s: unexpected error interrupt %08x\n", 838 sc->sc_dev.dv_xname, why); 839 } 840 841 if (rst) { 842 printf("%s: resetting\n", sc->sc_dev.dv_xname); 843 bereset(sc); 844 } 845 846 return (r); 847 } 848 849 /* 850 * Error interrupt. 851 */ 852 int 853 beeint(sc, why) 854 struct be_softc *sc; 855 u_int32_t why; 856 { 857 int r = 0, rst = 0; 858 859 if (why & BE_BR_STAT_RFIFOVF) { 860 r |= 1; 861 rst = 1; 862 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 863 } 864 if (why & BE_BR_STAT_TFIFO_UND) { 865 r |= 1; 866 rst = 1; 867 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 868 } 869 if (why & BE_BR_STAT_MAXPKTERR) { 870 r |= 1; 871 rst = 1; 872 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 873 } 874 875 if (!r) { 876 rst = 1; 877 printf("%s: unexpected error interrupt %08x\n", 878 sc->sc_dev.dv_xname, why); 879 } 880 881 if (rst) { 882 printf("%s: resetting\n", sc->sc_dev.dv_xname); 883 bereset(sc); 884 } 885 886 return (r); 887 } 888 889 /* 890 * Transmit interrupt. 891 */ 892 int 893 betint(sc) 894 struct be_softc *sc; 895 { 896 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 897 bus_space_tag_t t = sc->sc_bustag; 898 bus_space_handle_t br = sc->sc_br; 899 unsigned int bix, txflags; 900 901 /* 902 * Unload collision counters 903 */ 904 ifp->if_collisions += 905 bus_space_read_4(t, br, BE_BRI_NCCNT) + 906 bus_space_read_4(t, br, BE_BRI_FCCNT) + 907 bus_space_read_4(t, br, BE_BRI_EXCNT) + 908 bus_space_read_4(t, br, BE_BRI_LTCNT); 909 910 /* 911 * the clear the hardware counters 912 */ 913 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 914 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 915 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 916 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 917 918 bix = sc->sc_rb.rb_tdtail; 919 920 for (;;) { 921 if (sc->sc_rb.rb_td_nbusy <= 0) 922 break; 923 924 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 925 926 if (txflags & QEC_XD_OWN) 927 break; 928 929 ifp->if_flags &= ~IFF_OACTIVE; 930 ifp->if_opackets++; 931 932 if (++bix == QEC_XD_RING_MAXSIZE) 933 bix = 0; 934 935 --sc->sc_rb.rb_td_nbusy; 936 } 937 938 sc->sc_rb.rb_tdtail = bix; 939 940 bestart(ifp); 941 942 if (sc->sc_rb.rb_td_nbusy == 0) 943 ifp->if_timer = 0; 944 945 return (1); 946 } 947 948 /* 949 * Receive interrupt. 950 */ 951 int 952 berint(sc) 953 struct be_softc *sc; 954 { 955 struct qec_xd *xd = sc->sc_rb.rb_rxd; 956 unsigned int bix, len; 957 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 958 959 bix = sc->sc_rb.rb_rdtail; 960 961 /* 962 * Process all buffers with valid data. 963 */ 964 for (;;) { 965 len = xd[bix].xd_flags; 966 if (len & QEC_XD_OWN) 967 break; 968 969 len &= QEC_XD_LENGTH; 970 be_read(sc, bix, len); 971 972 /* ... */ 973 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 974 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 975 976 if (++bix == QEC_XD_RING_MAXSIZE) 977 bix = 0; 978 } 979 980 sc->sc_rb.rb_rdtail = bix; 981 982 return (1); 983 } 984 985 int 986 beioctl(ifp, cmd, data) 987 struct ifnet *ifp; 988 u_long cmd; 989 caddr_t data; 990 { 991 struct be_softc *sc = ifp->if_softc; 992 struct ifaddr *ifa = (struct ifaddr *)data; 993 struct ifreq *ifr = (struct ifreq *)data; 994 int s, error = 0; 995 996 s = splnet(); 997 998 switch (cmd) { 999 case SIOCSIFADDR: 1000 ifp->if_flags |= IFF_UP; 1001 switch (ifa->ifa_addr->sa_family) { 1002 #ifdef INET 1003 case AF_INET: 1004 beinit(sc); 1005 arp_ifinit(ifp, ifa); 1006 break; 1007 #endif /* INET */ 1008 #ifdef NS 1009 case AF_NS: 1010 { 1011 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1012 1013 if (ns_nullhost(*ina)) 1014 ina->x_host = 1015 *(union ns_host *)LLADDR(ifp->if_sadl); 1016 else 1017 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1018 sizeof(sc->sc_enaddr)); 1019 /* Set new address. */ 1020 beinit(sc); 1021 break; 1022 } 1023 #endif /* NS */ 1024 default: 1025 beinit(sc); 1026 break; 1027 } 1028 break; 1029 1030 case SIOCSIFFLAGS: 1031 if ((ifp->if_flags & IFF_UP) == 0 && 1032 (ifp->if_flags & IFF_RUNNING) != 0) { 1033 /* 1034 * If interface is marked down and it is running, then 1035 * stop it. 1036 */ 1037 bestop(sc); 1038 ifp->if_flags &= ~IFF_RUNNING; 1039 } else if ((ifp->if_flags & IFF_UP) != 0 && 1040 (ifp->if_flags & IFF_RUNNING) == 0) { 1041 /* 1042 * If interface is marked up and it is stopped, then 1043 * start it. 1044 */ 1045 beinit(sc); 1046 } else { 1047 /* 1048 * Reset the interface to pick up changes in any other 1049 * flags that affect hardware registers. 1050 */ 1051 bestop(sc); 1052 beinit(sc); 1053 } 1054 #ifdef BEDEBUG 1055 if (ifp->if_flags & IFF_DEBUG) 1056 sc->sc_debug = 1; 1057 else 1058 sc->sc_debug = 0; 1059 #endif 1060 break; 1061 1062 case SIOCADDMULTI: 1063 case SIOCDELMULTI: 1064 error = (cmd == SIOCADDMULTI) ? 1065 ether_addmulti(ifr, &sc->sc_ethercom): 1066 ether_delmulti(ifr, &sc->sc_ethercom); 1067 1068 if (error == ENETRESET) { 1069 /* 1070 * Multicast list has changed; set the hardware filter 1071 * accordingly. 1072 */ 1073 be_mcreset(sc); 1074 error = 0; 1075 } 1076 break; 1077 case SIOCGIFMEDIA: 1078 case SIOCSIFMEDIA: 1079 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1080 break; 1081 default: 1082 error = EINVAL; 1083 break; 1084 } 1085 splx(s); 1086 return (error); 1087 } 1088 1089 1090 void 1091 beinit(sc) 1092 struct be_softc *sc; 1093 { 1094 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1095 bus_space_tag_t t = sc->sc_bustag; 1096 bus_space_handle_t br = sc->sc_br; 1097 bus_space_handle_t cr = sc->sc_cr; 1098 struct qec_softc *qec = sc->sc_qec; 1099 u_int32_t v; 1100 u_int32_t qecaddr; 1101 u_int8_t *ea; 1102 int s; 1103 1104 s = splnet(); 1105 1106 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1107 1108 bestop(sc); 1109 1110 ea = sc->sc_enaddr; 1111 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1112 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1113 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1114 1115 /* Clear hash table */ 1116 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1117 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1118 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1119 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1120 1121 /* Re-initialize RX configuration */ 1122 v = BE_BR_RXCFG_FIFO; 1123 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1124 1125 be_mcreset(sc); 1126 1127 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1128 1129 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1130 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1131 1132 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1133 1134 /* 1135 * Turn off counter expiration interrupts as well as 1136 * 'gotframe' and 'sentframe' 1137 */ 1138 bus_space_write_4(t, br, BE_BRI_IMASK, 1139 BE_BR_IMASK_GOTFRAME | 1140 BE_BR_IMASK_RCNTEXP | 1141 BE_BR_IMASK_ACNTEXP | 1142 BE_BR_IMASK_CCNTEXP | 1143 BE_BR_IMASK_LCNTEXP | 1144 BE_BR_IMASK_CVCNTEXP | 1145 BE_BR_IMASK_SENTFRAME | 1146 BE_BR_IMASK_NCNTEXP | 1147 BE_BR_IMASK_ECNTEXP | 1148 BE_BR_IMASK_LCCNTEXP | 1149 BE_BR_IMASK_FCNTEXP | 1150 BE_BR_IMASK_DTIMEXP); 1151 1152 /* Channel registers: */ 1153 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1154 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1155 1156 qecaddr = sc->sc_channel * qec->sc_msize; 1157 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1158 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1159 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1160 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1161 1162 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1163 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1164 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1165 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1166 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1167 1168 /* Set max packet length */ 1169 v = ETHER_MAX_LEN; 1170 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1171 v += ETHER_VLAN_ENCAP_LEN; 1172 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1173 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1174 1175 /* Enable transmitter */ 1176 bus_space_write_4(t, br, BE_BRI_TXCFG, 1177 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1178 1179 /* Enable receiver */ 1180 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1181 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1182 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1183 1184 ifp->if_flags |= IFF_RUNNING; 1185 ifp->if_flags &= ~IFF_OACTIVE; 1186 1187 be_ifmedia_upd(ifp); 1188 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1189 splx(s); 1190 } 1191 1192 void 1193 be_mcreset(sc) 1194 struct be_softc *sc; 1195 { 1196 struct ethercom *ec = &sc->sc_ethercom; 1197 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1198 bus_space_tag_t t = sc->sc_bustag; 1199 bus_space_handle_t br = sc->sc_br; 1200 u_int32_t crc; 1201 u_int16_t hash[4]; 1202 u_int8_t octet; 1203 u_int32_t v; 1204 int i, j; 1205 struct ether_multi *enm; 1206 struct ether_multistep step; 1207 1208 if (ifp->if_flags & IFF_PROMISC) { 1209 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1210 v |= BE_BR_RXCFG_PMISC; 1211 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1212 return; 1213 } 1214 1215 if (ifp->if_flags & IFF_ALLMULTI) { 1216 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1217 goto chipit; 1218 } 1219 1220 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1221 1222 ETHER_FIRST_MULTI(step, ec, enm); 1223 while (enm != NULL) { 1224 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1225 /* 1226 * We must listen to a range of multicast 1227 * addresses. For now, just accept all 1228 * multicasts, rather than trying to set only 1229 * those filter bits needed to match the range. 1230 * (At this time, the only use of address 1231 * ranges is for IP multicast routing, for 1232 * which the range is big enough to require 1233 * all bits set.) 1234 */ 1235 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1236 ifp->if_flags |= IFF_ALLMULTI; 1237 goto chipit; 1238 } 1239 1240 crc = 0xffffffff; 1241 1242 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1243 octet = enm->enm_addrlo[i]; 1244 1245 for (j = 0; j < 8; j++) { 1246 if ((crc & 1) ^ (octet & 1)) { 1247 crc >>= 1; 1248 crc ^= MC_POLY_LE; 1249 } 1250 else 1251 crc >>= 1; 1252 octet >>= 1; 1253 } 1254 } 1255 1256 crc >>= 26; 1257 hash[crc >> 4] |= 1 << (crc & 0xf); 1258 ETHER_NEXT_MULTI(step, enm); 1259 } 1260 1261 ifp->if_flags &= ~IFF_ALLMULTI; 1262 1263 chipit: 1264 /* Enable the hash filter */ 1265 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1266 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1267 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1268 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1269 1270 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1271 v &= ~BE_BR_RXCFG_PMISC; 1272 v |= BE_BR_RXCFG_HENABLE; 1273 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1274 } 1275 1276 /* 1277 * Set the tcvr to an idle state 1278 */ 1279 void 1280 be_mii_sync(sc) 1281 struct be_softc *sc; 1282 { 1283 bus_space_tag_t t = sc->sc_bustag; 1284 bus_space_handle_t tr = sc->sc_tr; 1285 int n = 32; 1286 1287 while (n--) { 1288 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1289 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1290 MGMT_PAL_OENAB); 1291 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1292 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1293 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1294 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1295 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1296 } 1297 } 1298 1299 void 1300 be_pal_gate(sc, phy) 1301 struct be_softc *sc; 1302 int phy; 1303 { 1304 bus_space_tag_t t = sc->sc_bustag; 1305 bus_space_handle_t tr = sc->sc_tr; 1306 u_int32_t v; 1307 1308 be_mii_sync(sc); 1309 1310 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1311 if (phy == BE_PHY_INTERNAL) 1312 v &= ~TCVR_PAL_SERIAL; 1313 1314 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1315 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1316 } 1317 1318 static int 1319 be_tcvr_read_bit(sc, phy) 1320 struct be_softc *sc; 1321 int phy; 1322 { 1323 bus_space_tag_t t = sc->sc_bustag; 1324 bus_space_handle_t tr = sc->sc_tr; 1325 int ret; 1326 1327 if (phy == BE_PHY_INTERNAL) { 1328 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1329 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1330 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1331 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1332 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1333 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1334 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1335 } else { 1336 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1337 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1338 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1339 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1340 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1341 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1342 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1343 } 1344 1345 return (ret); 1346 } 1347 1348 static void 1349 be_tcvr_write_bit(sc, phy, bit) 1350 struct be_softc *sc; 1351 int phy; 1352 int bit; 1353 { 1354 bus_space_tag_t t = sc->sc_bustag; 1355 bus_space_handle_t tr = sc->sc_tr; 1356 u_int32_t v; 1357 1358 if (phy == BE_PHY_INTERNAL) { 1359 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1360 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1361 } else { 1362 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1363 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1364 } 1365 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1366 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1367 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1368 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1369 } 1370 1371 static void 1372 be_mii_sendbits(sc, phy, data, nbits) 1373 struct be_softc *sc; 1374 int phy; 1375 u_int32_t data; 1376 int nbits; 1377 { 1378 int i; 1379 1380 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1381 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1382 } 1383 } 1384 1385 static int 1386 be_mii_readreg(self, phy, reg) 1387 struct device *self; 1388 int phy, reg; 1389 { 1390 struct be_softc *sc = (struct be_softc *)self; 1391 int val = 0, i; 1392 1393 /* 1394 * Read the PHY register by manually driving the MII control lines. 1395 */ 1396 be_mii_sync(sc); 1397 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1398 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1399 be_mii_sendbits(sc, phy, phy, 5); 1400 be_mii_sendbits(sc, phy, reg, 5); 1401 1402 (void) be_tcvr_read_bit(sc, phy); 1403 (void) be_tcvr_read_bit(sc, phy); 1404 1405 for (i = 15; i >= 0; i--) 1406 val |= (be_tcvr_read_bit(sc, phy) << i); 1407 1408 (void) be_tcvr_read_bit(sc, phy); 1409 (void) be_tcvr_read_bit(sc, phy); 1410 (void) be_tcvr_read_bit(sc, phy); 1411 1412 return (val); 1413 } 1414 1415 void 1416 be_mii_writereg(self, phy, reg, val) 1417 struct device *self; 1418 int phy, reg, val; 1419 { 1420 struct be_softc *sc = (struct be_softc *)self; 1421 int i; 1422 1423 /* 1424 * Write the PHY register by manually driving the MII control lines. 1425 */ 1426 be_mii_sync(sc); 1427 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1428 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1429 be_mii_sendbits(sc, phy, phy, 5); 1430 be_mii_sendbits(sc, phy, reg, 5); 1431 1432 be_tcvr_write_bit(sc, phy, 1); 1433 be_tcvr_write_bit(sc, phy, 0); 1434 1435 for (i = 15; i >= 0; i--) 1436 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1437 } 1438 1439 int 1440 be_mii_reset(sc, phy) 1441 struct be_softc *sc; 1442 int phy; 1443 { 1444 int n; 1445 1446 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1447 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1448 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1449 1450 for (n = 16; n >= 0; n--) { 1451 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1452 if ((bmcr & BMCR_RESET) == 0) 1453 break; 1454 DELAY(20); 1455 } 1456 if (n == 0) { 1457 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1458 return (EIO); 1459 } 1460 1461 return (0); 1462 } 1463 1464 void 1465 be_tick(arg) 1466 void *arg; 1467 { 1468 struct be_softc *sc = arg; 1469 int s = splnet(); 1470 1471 mii_tick(&sc->sc_mii); 1472 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1473 1474 splx(s); 1475 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1476 } 1477 1478 void 1479 be_mii_statchg(self) 1480 struct device *self; 1481 { 1482 struct be_softc *sc = (struct be_softc *)self; 1483 bus_space_tag_t t = sc->sc_bustag; 1484 bus_space_handle_t br = sc->sc_br; 1485 u_int instance; 1486 u_int32_t v; 1487 1488 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1489 #ifdef DIAGNOSTIC 1490 if (instance > 1) 1491 panic("be_mii_statchg: instance %d out of range", instance); 1492 #endif 1493 1494 /* Update duplex mode in TX configuration */ 1495 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1496 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1497 v |= BE_BR_TXCFG_FULLDPLX; 1498 else 1499 v &= ~BE_BR_TXCFG_FULLDPLX; 1500 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1501 1502 /* Change to appropriate gate in transceiver PAL */ 1503 be_pal_gate(sc, sc->sc_phys[instance]); 1504 } 1505 1506 /* 1507 * Get current media settings. 1508 */ 1509 void 1510 be_ifmedia_sts(ifp, ifmr) 1511 struct ifnet *ifp; 1512 struct ifmediareq *ifmr; 1513 { 1514 struct be_softc *sc = ifp->if_softc; 1515 1516 mii_pollstat(&sc->sc_mii); 1517 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1518 1519 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1520 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1521 return; 1522 } 1523 1524 /* 1525 * Set media options. 1526 */ 1527 int 1528 be_ifmedia_upd(ifp) 1529 struct ifnet *ifp; 1530 { 1531 struct be_softc *sc = ifp->if_softc; 1532 int error; 1533 1534 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1535 return (error); 1536 1537 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1538 } 1539 1540 /* 1541 * Service routine for our pseudo-MII internal transceiver. 1542 */ 1543 int 1544 be_intphy_service(sc, mii, cmd) 1545 struct be_softc *sc; 1546 struct mii_data *mii; 1547 int cmd; 1548 { 1549 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1550 int bmcr, bmsr; 1551 int error; 1552 1553 switch (cmd) { 1554 case MII_POLLSTAT: 1555 /* 1556 * If we're not polling our PHY instance, just return. 1557 */ 1558 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1559 return (0); 1560 1561 break; 1562 1563 case MII_MEDIACHG: 1564 1565 /* 1566 * If the media indicates a different PHY instance, 1567 * isolate ourselves. 1568 */ 1569 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1570 bmcr = be_mii_readreg((void *)sc, 1571 BE_PHY_INTERNAL, MII_BMCR); 1572 be_mii_writereg((void *)sc, 1573 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1574 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1575 sc->sc_intphy_curspeed = 0; 1576 return (0); 1577 } 1578 1579 1580 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1581 return (error); 1582 1583 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1584 1585 /* 1586 * Select the new mode and take out of isolation 1587 */ 1588 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1589 bmcr |= BMCR_S100; 1590 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1591 bmcr &= ~BMCR_S100; 1592 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1593 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1594 bmcr &= ~BMCR_S100; 1595 bmcr |= sc->sc_intphy_curspeed; 1596 } else { 1597 /* Keep isolated until link is up */ 1598 bmcr |= BMCR_ISO; 1599 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1600 } 1601 } 1602 1603 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1604 bmcr |= BMCR_FDX; 1605 else 1606 bmcr &= ~BMCR_FDX; 1607 1608 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1609 break; 1610 1611 case MII_TICK: 1612 /* 1613 * If we're not currently selected, just return. 1614 */ 1615 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1616 return (0); 1617 1618 /* Only used for automatic media selection */ 1619 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1620 return (0); 1621 1622 /* Is the interface even up? */ 1623 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1624 return (0); 1625 1626 /* 1627 * Check link status; if we don't have a link, try another 1628 * speed. We can't detect duplex mode, so half-duplex is 1629 * what we have to settle for. 1630 */ 1631 1632 /* Read twice in case the register is latched */ 1633 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1634 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1635 1636 if ((bmsr & BMSR_LINK) != 0) { 1637 /* We have a carrier */ 1638 bmcr = be_mii_readreg((void *)sc, 1639 BE_PHY_INTERNAL, MII_BMCR); 1640 1641 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1642 bmcr = be_mii_readreg((void *)sc, 1643 BE_PHY_INTERNAL, MII_BMCR); 1644 1645 sc->sc_mii_flags |= MIIF_HAVELINK; 1646 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1647 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1648 1649 bmcr &= ~BMCR_ISO; 1650 be_mii_writereg((void *)sc, 1651 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1652 1653 printf("%s: link up at %s Mbps\n", 1654 sc->sc_dev.dv_xname, 1655 (bmcr & BMCR_S100) ? "100" : "10"); 1656 } 1657 return (0); 1658 } 1659 1660 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1661 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1662 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1663 sc->sc_intphy_curspeed = 0; 1664 printf("%s: link down\n", sc->sc_dev.dv_xname); 1665 } 1666 1667 /* Only retry autonegotiation every 5 seconds. */ 1668 if (++sc->sc_mii_ticks < 5) 1669 return(0); 1670 1671 sc->sc_mii_ticks = 0; 1672 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1673 /* Just flip the fast speed bit */ 1674 bmcr ^= BMCR_S100; 1675 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1676 1677 break; 1678 1679 case MII_DOWN: 1680 /* Isolate this phy */ 1681 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1682 be_mii_writereg((void *)sc, 1683 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1684 return (0); 1685 } 1686 1687 /* Update the media status. */ 1688 be_intphy_status(sc); 1689 1690 /* Callback if something changed. */ 1691 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1692 (*mii->mii_statchg)((struct device *)sc); 1693 sc->sc_mii_active = mii->mii_media_active; 1694 } 1695 return (0); 1696 } 1697 1698 /* 1699 * Determine status of internal transceiver 1700 */ 1701 void 1702 be_intphy_status(sc) 1703 struct be_softc *sc; 1704 { 1705 struct mii_data *mii = &sc->sc_mii; 1706 int media_active, media_status; 1707 int bmcr, bmsr; 1708 1709 media_status = IFM_AVALID; 1710 media_active = 0; 1711 1712 /* 1713 * Internal transceiver; do the work here. 1714 */ 1715 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1716 1717 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1718 case (BMCR_S100 | BMCR_FDX): 1719 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1720 break; 1721 case BMCR_S100: 1722 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1723 break; 1724 case BMCR_FDX: 1725 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1726 break; 1727 case 0: 1728 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1729 break; 1730 } 1731 1732 /* Read twice in case the register is latched */ 1733 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1734 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1735 if (bmsr & BMSR_LINK) 1736 media_status |= IFM_ACTIVE; 1737 1738 mii->mii_media_status = media_status; 1739 mii->mii_media_active = media_active; 1740 } 1741
Indexes created Tue Sep 30 11:09:46 GMT 2025