be.c revision 1.42
1 /* $NetBSD: be.c,v 1.42 2004/03/17 17:04:58 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.42 2004/03/17 17:04:58 pk Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_inet.h" 71 #include "opt_ccitt.h" 72 #include "opt_llc.h" 73 #include "opt_ns.h" 74 #include "bpfilter.h" 75 #include "rnd.h" 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/callout.h> 80 #include <sys/kernel.h> 81 #include <sys/errno.h> 82 #include <sys/ioctl.h> 83 #include <sys/mbuf.h> 84 #include <sys/socket.h> 85 #include <sys/syslog.h> 86 #include <sys/device.h> 87 #include <sys/malloc.h> 88 #if NRND > 0 89 #include <sys/rnd.h> 90 #endif 91 92 #include <net/if.h> 93 #include <net/if_dl.h> 94 #include <net/if_types.h> 95 #include <net/netisr.h> 96 #include <net/if_media.h> 97 #include <net/if_ether.h> 98 99 #ifdef INET 100 #include <netinet/in.h> 101 #include <netinet/if_inarp.h> 102 #include <netinet/in_systm.h> 103 #include <netinet/in_var.h> 104 #include <netinet/ip.h> 105 #endif 106 107 #ifdef NS 108 #include <netns/ns.h> 109 #include <netns/ns_if.h> 110 #endif 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #include <net/bpfdesc.h> 115 #endif 116 117 #include <machine/bus.h> 118 #include <machine/intr.h> 119 #include <machine/autoconf.h> 120 121 #include <dev/sbus/sbusvar.h> 122 123 #include <dev/mii/mii.h> 124 #include <dev/mii/miivar.h> 125 126 #include <dev/sbus/qecreg.h> 127 #include <dev/sbus/qecvar.h> 128 #include <dev/sbus/bereg.h> 129 130 struct be_softc { 131 struct device sc_dev; 132 struct sbusdev sc_sd; /* sbus device */ 133 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 134 bus_dma_tag_t sc_dmatag; 135 bus_dmamap_t sc_dmamap; 136 struct ethercom sc_ethercom; 137 /*struct ifmedia sc_ifmedia; -* interface media */ 138 struct mii_data sc_mii; /* MII media control */ 139 #define sc_media sc_mii.mii_media/* shorthand */ 140 int sc_phys[2]; /* MII instance -> phy */ 141 142 struct callout sc_tick_ch; 143 144 /* 145 * Some `mii_softc' items we need to emulate MII operation 146 * for our internal transceiver. 147 */ 148 int sc_mii_inst; /* instance of internal phy */ 149 int sc_mii_active; /* currently active medium */ 150 int sc_mii_ticks; /* tick counter */ 151 int sc_mii_flags; /* phy status flags */ 152 #define MIIF_HAVELINK 0x04000000 153 int sc_intphy_curspeed; /* Established link speed */ 154 155 struct qec_softc *sc_qec; /* QEC parent */ 156 157 bus_space_handle_t sc_qr; /* QEC registers */ 158 bus_space_handle_t sc_br; /* BE registers */ 159 bus_space_handle_t sc_cr; /* channel registers */ 160 bus_space_handle_t sc_tr; /* transceiver registers */ 161 162 u_int sc_rev; 163 164 int sc_channel; /* channel number */ 165 int sc_burst; 166 167 struct qec_ring sc_rb; /* Packet Ring Buffer */ 168 169 /* MAC address */ 170 u_int8_t sc_enaddr[6]; 171 }; 172 173 int bematch __P((struct device *, struct cfdata *, void *)); 174 void beattach __P((struct device *, struct device *, void *)); 175 176 void beinit __P((struct be_softc *)); 177 void bestart __P((struct ifnet *)); 178 void bestop __P((struct be_softc *)); 179 void bewatchdog __P((struct ifnet *)); 180 int beioctl __P((struct ifnet *, u_long, caddr_t)); 181 void bereset __P((struct be_softc *)); 182 183 int beintr __P((void *)); 184 int berint __P((struct be_softc *)); 185 int betint __P((struct be_softc *)); 186 int beqint __P((struct be_softc *, u_int32_t)); 187 int beeint __P((struct be_softc *, u_int32_t)); 188 189 static void be_read __P((struct be_softc *, int, int)); 190 static int be_put __P((struct be_softc *, int, struct mbuf *)); 191 static struct mbuf *be_get __P((struct be_softc *, int, int)); 192 193 void be_pal_gate __P((struct be_softc *, int)); 194 195 /* ifmedia callbacks */ 196 void be_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 197 int be_ifmedia_upd __P((struct ifnet *)); 198 199 void be_mcreset __P((struct be_softc *)); 200 201 /* MII methods & callbacks */ 202 static int be_mii_readreg __P((struct device *, int, int)); 203 static void be_mii_writereg __P((struct device *, int, int, int)); 204 static void be_mii_statchg __P((struct device *)); 205 206 /* MII helpers */ 207 static void be_mii_sync __P((struct be_softc *)); 208 static void be_mii_sendbits __P((struct be_softc *, int, u_int32_t, int)); 209 static int be_mii_reset __P((struct be_softc *, int)); 210 static int be_tcvr_read_bit __P((struct be_softc *, int)); 211 static void be_tcvr_write_bit __P((struct be_softc *, int, int)); 212 213 void be_tick __P((void *)); 214 void be_intphy_auto __P((struct be_softc *)); 215 void be_intphy_status __P((struct be_softc *)); 216 int be_intphy_service __P((struct be_softc *, struct mii_data *, int)); 217 218 219 CFATTACH_DECL(be, sizeof(struct be_softc), 220 bematch, beattach, NULL, NULL); 221 222 int 223 bematch(parent, cf, aux) 224 struct device *parent; 225 struct cfdata *cf; 226 void *aux; 227 { 228 struct sbus_attach_args *sa = aux; 229 230 return (strcmp(cf->cf_name, sa->sa_name) == 0); 231 } 232 233 void 234 beattach(parent, self, aux) 235 struct device *parent, *self; 236 void *aux; 237 { 238 struct sbus_attach_args *sa = aux; 239 struct qec_softc *qec = (struct qec_softc *)parent; 240 struct be_softc *sc = (struct be_softc *)self; 241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 242 struct mii_data *mii = &sc->sc_mii; 243 struct mii_softc *child; 244 int node = sa->sa_node; 245 bus_dma_tag_t dmatag = sa->sa_dmatag; 246 bus_dma_segment_t seg; 247 bus_size_t size; 248 int instance; 249 int rseg, error; 250 u_int32_t v; 251 252 if (sa->sa_nreg < 3) { 253 printf("%s: only %d register sets\n", 254 self->dv_xname, sa->sa_nreg); 255 return; 256 } 257 258 if (bus_space_map(sa->sa_bustag, 259 (bus_addr_t)BUS_ADDR( 260 sa->sa_reg[0].oa_space, 261 sa->sa_reg[0].oa_base), 262 (bus_size_t)sa->sa_reg[0].oa_size, 263 0, &sc->sc_cr) != 0) { 264 printf("beattach: cannot map registers\n"); 265 return; 266 } 267 268 if (bus_space_map(sa->sa_bustag, 269 (bus_addr_t)BUS_ADDR( 270 sa->sa_reg[1].oa_space, 271 sa->sa_reg[1].oa_base), 272 (bus_size_t)sa->sa_reg[1].oa_size, 273 0, &sc->sc_br) != 0) { 274 printf("beattach: cannot map registers\n"); 275 return; 276 } 277 278 if (bus_space_map(sa->sa_bustag, 279 (bus_addr_t)BUS_ADDR( 280 sa->sa_reg[2].oa_space, 281 sa->sa_reg[2].oa_base), 282 (bus_size_t)sa->sa_reg[2].oa_size, 283 0, &sc->sc_tr) != 0) { 284 printf("beattach: cannot map registers\n"); 285 return; 286 } 287 288 sc->sc_bustag = sa->sa_bustag; 289 sc->sc_qec = qec; 290 sc->sc_qr = qec->sc_regs; 291 292 sc->sc_rev = prom_getpropint(node, "board-version", -1); 293 printf(" rev %x", sc->sc_rev); 294 295 bestop(sc); 296 297 sc->sc_channel = prom_getpropint(node, "channel#", -1); 298 if (sc->sc_channel == -1) 299 sc->sc_channel = 0; 300 301 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 302 if (sc->sc_burst == -1) 303 sc->sc_burst = qec->sc_burst; 304 305 /* Clamp at parent's burst sizes */ 306 sc->sc_burst &= qec->sc_burst; 307 308 /* Establish interrupt handler */ 309 if (sa->sa_nintr) 310 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 311 beintr, sc); 312 313 prom_getether(node, sc->sc_enaddr); 314 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 315 316 /* 317 * Allocate descriptor ring and buffers. 318 */ 319 320 /* for now, allocate as many bufs as there are ring descriptors */ 321 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 322 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 323 324 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 325 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 326 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 327 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 328 329 /* Get a DMA handle */ 330 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 331 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 332 printf("%s: DMA map create error %d\n", self->dv_xname, error); 333 return; 334 } 335 336 /* Allocate DMA buffer */ 337 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 338 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 339 printf("%s: DMA buffer alloc error %d\n", 340 self->dv_xname, error); 341 return; 342 } 343 344 /* Map DMA memory in CPU addressable space */ 345 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 346 &sc->sc_rb.rb_membase, 347 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 348 printf("%s: DMA buffer map error %d\n", 349 self->dv_xname, error); 350 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 351 return; 352 } 353 354 /* Load the buffer */ 355 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 356 sc->sc_rb.rb_membase, size, NULL, 357 BUS_DMA_NOWAIT)) != 0) { 358 printf("%s: DMA buffer map load error %d\n", 359 self->dv_xname, error); 360 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 361 bus_dmamem_free(dmatag, &seg, rseg); 362 return; 363 } 364 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 365 366 /* 367 * Initialize our media structures and MII info. 368 */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = be_mii_readreg; 371 mii->mii_writereg = be_mii_writereg; 372 mii->mii_statchg = be_mii_statchg; 373 374 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 375 376 callout_init(&sc->sc_tick_ch); 377 378 /* 379 * Initialize transceiver and determine which PHY connection to use. 380 */ 381 be_mii_sync(sc); 382 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 383 384 instance = 0; 385 386 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 387 388 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 389 MII_OFFSET_ANY, 0); 390 391 child = LIST_FIRST(&mii->mii_phys); 392 if (child == NULL) { 393 /* No PHY attached */ 394 ifmedia_add(&sc->sc_media, 395 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 396 0, NULL); 397 ifmedia_set(&sc->sc_media, 398 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 399 } else { 400 /* 401 * Note: we support just one PHY on the external 402 * MII connector. 403 */ 404 #ifdef DIAGNOSTIC 405 if (LIST_NEXT(child, mii_list) != NULL) { 406 printf("%s: spurious MII device %s attached\n", 407 sc->sc_dev.dv_xname, 408 child->mii_dev.dv_xname); 409 } 410 #endif 411 if (child->mii_phy != BE_PHY_EXTERNAL || 412 child->mii_inst > 0) { 413 printf("%s: cannot accomodate MII device %s" 414 " at phy %d, instance %d\n", 415 sc->sc_dev.dv_xname, 416 child->mii_dev.dv_xname, 417 child->mii_phy, child->mii_inst); 418 } else { 419 sc->sc_phys[instance] = child->mii_phy; 420 } 421 422 /* 423 * XXX - we can really do the following ONLY if the 424 * phy indeed has the auto negotiation capability!! 425 */ 426 ifmedia_set(&sc->sc_media, 427 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 428 429 /* Mark our current media setting */ 430 be_pal_gate(sc, BE_PHY_EXTERNAL); 431 instance++; 432 } 433 434 } 435 436 if ((v & MGMT_PAL_INT_MDIO) != 0) { 437 /* 438 * The be internal phy looks vaguely like MII hardware, 439 * but not enough to be able to use the MII device 440 * layer. Hence, we have to take care of media selection 441 * ourselves. 442 */ 443 444 sc->sc_mii_inst = instance; 445 sc->sc_phys[instance] = BE_PHY_INTERNAL; 446 447 /* Use `ifm_data' to store BMCR bits */ 448 ifmedia_add(&sc->sc_media, 449 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 450 0, NULL); 451 ifmedia_add(&sc->sc_media, 452 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 453 BMCR_S100, NULL); 454 ifmedia_add(&sc->sc_media, 455 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 456 0, NULL); 457 458 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 459 self->dv_xname); 460 461 be_mii_reset(sc, BE_PHY_INTERNAL); 462 /* Only set default medium here if there's no external PHY */ 463 if (instance == 0) { 464 be_pal_gate(sc, BE_PHY_INTERNAL); 465 ifmedia_set(&sc->sc_media, 466 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 467 } else 468 be_mii_writereg((void *)sc, 469 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 470 } 471 472 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 473 ifp->if_softc = sc; 474 ifp->if_start = bestart; 475 ifp->if_ioctl = beioctl; 476 ifp->if_watchdog = bewatchdog; 477 ifp->if_flags = 478 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 479 IFQ_SET_READY(&ifp->if_snd); 480 481 /* claim 802.1q capability */ 482 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 483 484 /* Attach the interface. */ 485 if_attach(ifp); 486 ether_ifattach(ifp, sc->sc_enaddr); 487 } 488 489 490 /* 491 * Routine to copy from mbuf chain to transmit buffer in 492 * network buffer memory. 493 */ 494 static __inline__ int 495 be_put(sc, idx, m) 496 struct be_softc *sc; 497 int idx; 498 struct mbuf *m; 499 { 500 struct mbuf *n; 501 int len, tlen = 0, boff = 0; 502 caddr_t bp; 503 504 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 505 506 for (; m; m = n) { 507 len = m->m_len; 508 if (len == 0) { 509 MFREE(m, n); 510 continue; 511 } 512 bcopy(mtod(m, caddr_t), bp+boff, len); 513 boff += len; 514 tlen += len; 515 MFREE(m, n); 516 } 517 return (tlen); 518 } 519 520 /* 521 * Pull data off an interface. 522 * Len is the length of data, with local net header stripped. 523 * We copy the data into mbufs. When full cluster sized units are present, 524 * we copy into clusters. 525 */ 526 static __inline__ struct mbuf * 527 be_get(sc, idx, totlen) 528 struct be_softc *sc; 529 int idx, totlen; 530 { 531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 532 struct mbuf *m; 533 struct mbuf *top, **mp; 534 int len, pad, boff = 0; 535 caddr_t bp; 536 537 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 538 539 MGETHDR(m, M_DONTWAIT, MT_DATA); 540 if (m == NULL) 541 return (NULL); 542 m->m_pkthdr.rcvif = ifp; 543 m->m_pkthdr.len = totlen; 544 545 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 546 m->m_data += pad; 547 len = MHLEN - pad; 548 top = NULL; 549 mp = ⊤ 550 551 while (totlen > 0) { 552 if (top) { 553 MGET(m, M_DONTWAIT, MT_DATA); 554 if (m == NULL) { 555 m_freem(top); 556 return (NULL); 557 } 558 len = MLEN; 559 } 560 if (top && totlen >= MINCLSIZE) { 561 MCLGET(m, M_DONTWAIT); 562 if (m->m_flags & M_EXT) 563 len = MCLBYTES; 564 } 565 m->m_len = len = min(totlen, len); 566 bcopy(bp + boff, mtod(m, caddr_t), len); 567 boff += len; 568 totlen -= len; 569 *mp = m; 570 mp = &m->m_next; 571 } 572 573 return (top); 574 } 575 576 /* 577 * Pass a packet to the higher levels. 578 */ 579 static __inline__ void 580 be_read(sc, idx, len) 581 struct be_softc *sc; 582 int idx, len; 583 { 584 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 585 struct mbuf *m; 586 587 #ifdef DIAGNOSTIC 588 if (len < ETHER_MIN_LEN || len > ETHER_MAX_LEN + ETHERCAP_VLAN_MTU) { 589 printf("%s: invalid packet size %d; dropping\n", 590 ifp->if_xname, len); 591 ifp->if_ierrors++; 592 return; 593 } 594 #endif 595 596 /* 597 * Pull packet off interface. 598 */ 599 m = be_get(sc, idx, len); 600 if (m == NULL) { 601 ifp->if_ierrors++; 602 return; 603 } 604 ifp->if_ipackets++; 605 606 #if NBPFILTER > 0 607 /* 608 * Check if there's a BPF listener on this interface. 609 * If so, hand off the raw packet to BPF. 610 */ 611 if (ifp->if_bpf) 612 bpf_mtap(ifp->if_bpf, m); 613 #endif 614 /* Pass the packet up. */ 615 (*ifp->if_input)(ifp, m); 616 } 617 618 /* 619 * Start output on interface. 620 * We make two assumptions here: 621 * 1) that the current priority is set to splnet _before_ this code 622 * is called *and* is returned to the appropriate priority after 623 * return 624 * 2) that the IFF_OACTIVE flag is checked before this code is called 625 * (i.e. that the output part of the interface is idle) 626 */ 627 void 628 bestart(ifp) 629 struct ifnet *ifp; 630 { 631 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 632 struct qec_xd *txd = sc->sc_rb.rb_txd; 633 struct mbuf *m; 634 unsigned int bix, len; 635 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 636 637 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 638 return; 639 640 bix = sc->sc_rb.rb_tdhead; 641 642 for (;;) { 643 IFQ_DEQUEUE(&ifp->if_snd, m); 644 if (m == 0) 645 break; 646 647 #if NBPFILTER > 0 648 /* 649 * If BPF is listening on this interface, let it see the 650 * packet before we commit it to the wire. 651 */ 652 if (ifp->if_bpf) 653 bpf_mtap(ifp->if_bpf, m); 654 #endif 655 656 /* 657 * Copy the mbuf chain into the transmit buffer. 658 */ 659 len = be_put(sc, bix, m); 660 661 /* 662 * Initialize transmit registers and start transmission 663 */ 664 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 665 (len & QEC_XD_LENGTH); 666 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 667 BE_CR_CTRL_TWAKEUP); 668 669 if (++bix == QEC_XD_RING_MAXSIZE) 670 bix = 0; 671 672 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 673 ifp->if_flags |= IFF_OACTIVE; 674 break; 675 } 676 } 677 678 sc->sc_rb.rb_tdhead = bix; 679 } 680 681 void 682 bestop(sc) 683 struct be_softc *sc; 684 { 685 int n; 686 bus_space_tag_t t = sc->sc_bustag; 687 bus_space_handle_t br = sc->sc_br; 688 689 callout_stop(&sc->sc_tick_ch); 690 691 /* Down the MII. */ 692 mii_down(&sc->sc_mii); 693 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 694 695 /* Stop the transmitter */ 696 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 697 for (n = 32; n > 0; n--) { 698 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 699 break; 700 DELAY(20); 701 } 702 703 /* Stop the receiver */ 704 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 705 for (n = 32; n > 0; n--) { 706 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 707 break; 708 DELAY(20); 709 } 710 } 711 712 /* 713 * Reset interface. 714 */ 715 void 716 bereset(sc) 717 struct be_softc *sc; 718 { 719 int s; 720 721 s = splnet(); 722 bestop(sc); 723 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 724 beinit(sc); 725 splx(s); 726 } 727 728 void 729 bewatchdog(ifp) 730 struct ifnet *ifp; 731 { 732 struct be_softc *sc = ifp->if_softc; 733 734 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 735 ++sc->sc_ethercom.ec_if.if_oerrors; 736 737 bereset(sc); 738 } 739 740 int 741 beintr(v) 742 void *v; 743 { 744 struct be_softc *sc = (struct be_softc *)v; 745 bus_space_tag_t t = sc->sc_bustag; 746 u_int32_t whyq, whyb, whyc; 747 int r = 0; 748 749 /* Read QEC status, channel status and BE status */ 750 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 751 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 752 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 753 754 if (whyq & QEC_STAT_BM) 755 r |= beeint(sc, whyb); 756 757 if (whyq & QEC_STAT_ER) 758 r |= beqint(sc, whyc); 759 760 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 761 r |= betint(sc); 762 763 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 764 r |= berint(sc); 765 766 return (r); 767 } 768 769 /* 770 * QEC Interrupt. 771 */ 772 int 773 beqint(sc, why) 774 struct be_softc *sc; 775 u_int32_t why; 776 { 777 int r = 0, rst = 0; 778 779 if (why & BE_CR_STAT_TXIRQ) 780 r |= 1; 781 if (why & BE_CR_STAT_RXIRQ) 782 r |= 1; 783 784 if (why & BE_CR_STAT_BERROR) { 785 r |= 1; 786 rst = 1; 787 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 788 } 789 790 if (why & BE_CR_STAT_TXDERR) { 791 r |= 1; 792 rst = 1; 793 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 794 } 795 796 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 797 r |= 1; 798 rst = 1; 799 printf("%s: tx DMA error ( ", sc->sc_dev.dv_xname); 800 if (why & BE_CR_STAT_TXLERR) 801 printf("Late "); 802 if (why & BE_CR_STAT_TXPERR) 803 printf("Parity "); 804 if (why & BE_CR_STAT_TXSERR) 805 printf("Generic "); 806 printf(")\n"); 807 } 808 809 if (why & BE_CR_STAT_RXDROP) { 810 r |= 1; 811 rst = 1; 812 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 813 } 814 815 if (why & BE_CR_STAT_RXSMALL) { 816 r |= 1; 817 rst = 1; 818 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 819 } 820 821 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 822 r |= 1; 823 rst = 1; 824 printf("%s: rx DMA error ( ", sc->sc_dev.dv_xname); 825 if (why & BE_CR_STAT_RXLERR) 826 printf("Late "); 827 if (why & BE_CR_STAT_RXPERR) 828 printf("Parity "); 829 if (why & BE_CR_STAT_RXSERR) 830 printf("Generic "); 831 printf(")\n"); 832 } 833 834 if (!r) { 835 rst = 1; 836 printf("%s: unexpected error interrupt %08x\n", 837 sc->sc_dev.dv_xname, why); 838 } 839 840 if (rst) { 841 printf("%s: resetting\n", sc->sc_dev.dv_xname); 842 bereset(sc); 843 } 844 845 return (r); 846 } 847 848 /* 849 * Error interrupt. 850 */ 851 int 852 beeint(sc, why) 853 struct be_softc *sc; 854 u_int32_t why; 855 { 856 int r = 0, rst = 0; 857 858 if (why & BE_BR_STAT_RFIFOVF) { 859 r |= 1; 860 rst = 1; 861 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 862 } 863 if (why & BE_BR_STAT_TFIFO_UND) { 864 r |= 1; 865 rst = 1; 866 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 867 } 868 if (why & BE_BR_STAT_MAXPKTERR) { 869 r |= 1; 870 rst = 1; 871 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 872 } 873 874 if (!r) { 875 rst = 1; 876 printf("%s: unexpected error interrupt %08x\n", 877 sc->sc_dev.dv_xname, why); 878 } 879 880 if (rst) { 881 printf("%s: resetting\n", sc->sc_dev.dv_xname); 882 bereset(sc); 883 } 884 885 return (r); 886 } 887 888 /* 889 * Transmit interrupt. 890 */ 891 int 892 betint(sc) 893 struct be_softc *sc; 894 { 895 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 896 bus_space_tag_t t = sc->sc_bustag; 897 bus_space_handle_t br = sc->sc_br; 898 unsigned int bix, txflags; 899 900 /* 901 * Unload collision counters 902 */ 903 ifp->if_collisions += 904 bus_space_read_4(t, br, BE_BRI_NCCNT) + 905 bus_space_read_4(t, br, BE_BRI_FCCNT) + 906 bus_space_read_4(t, br, BE_BRI_EXCNT) + 907 bus_space_read_4(t, br, BE_BRI_LTCNT); 908 909 /* 910 * the clear the hardware counters 911 */ 912 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 913 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 914 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 915 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 916 917 bix = sc->sc_rb.rb_tdtail; 918 919 for (;;) { 920 if (sc->sc_rb.rb_td_nbusy <= 0) 921 break; 922 923 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 924 925 if (txflags & QEC_XD_OWN) 926 break; 927 928 ifp->if_flags &= ~IFF_OACTIVE; 929 ifp->if_opackets++; 930 931 if (++bix == QEC_XD_RING_MAXSIZE) 932 bix = 0; 933 934 --sc->sc_rb.rb_td_nbusy; 935 } 936 937 sc->sc_rb.rb_tdtail = bix; 938 939 bestart(ifp); 940 941 if (sc->sc_rb.rb_td_nbusy == 0) 942 ifp->if_timer = 0; 943 944 return (1); 945 } 946 947 /* 948 * Receive interrupt. 949 */ 950 int 951 berint(sc) 952 struct be_softc *sc; 953 { 954 struct qec_xd *xd = sc->sc_rb.rb_rxd; 955 unsigned int bix, len; 956 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 957 958 bix = sc->sc_rb.rb_rdtail; 959 960 /* 961 * Process all buffers with valid data. 962 */ 963 for (;;) { 964 len = xd[bix].xd_flags; 965 if (len & QEC_XD_OWN) 966 break; 967 968 len &= QEC_XD_LENGTH; 969 be_read(sc, bix, len); 970 971 /* ... */ 972 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 973 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 974 975 if (++bix == QEC_XD_RING_MAXSIZE) 976 bix = 0; 977 } 978 979 sc->sc_rb.rb_rdtail = bix; 980 981 return (1); 982 } 983 984 int 985 beioctl(ifp, cmd, data) 986 struct ifnet *ifp; 987 u_long cmd; 988 caddr_t data; 989 { 990 struct be_softc *sc = ifp->if_softc; 991 struct ifaddr *ifa = (struct ifaddr *)data; 992 struct ifreq *ifr = (struct ifreq *)data; 993 int s, error = 0; 994 995 s = splnet(); 996 997 switch (cmd) { 998 case SIOCSIFADDR: 999 ifp->if_flags |= IFF_UP; 1000 switch (ifa->ifa_addr->sa_family) { 1001 #ifdef INET 1002 case AF_INET: 1003 beinit(sc); 1004 arp_ifinit(ifp, ifa); 1005 break; 1006 #endif /* INET */ 1007 #ifdef NS 1008 case AF_NS: 1009 { 1010 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1011 1012 if (ns_nullhost(*ina)) 1013 ina->x_host = 1014 *(union ns_host *)LLADDR(ifp->if_sadl); 1015 else 1016 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1017 sizeof(sc->sc_enaddr)); 1018 /* Set new address. */ 1019 beinit(sc); 1020 break; 1021 } 1022 #endif /* NS */ 1023 default: 1024 beinit(sc); 1025 break; 1026 } 1027 break; 1028 1029 case SIOCSIFFLAGS: 1030 if ((ifp->if_flags & IFF_UP) == 0 && 1031 (ifp->if_flags & IFF_RUNNING) != 0) { 1032 /* 1033 * If interface is marked down and it is running, then 1034 * stop it. 1035 */ 1036 bestop(sc); 1037 ifp->if_flags &= ~IFF_RUNNING; 1038 } else if ((ifp->if_flags & IFF_UP) != 0 && 1039 (ifp->if_flags & IFF_RUNNING) == 0) { 1040 /* 1041 * If interface is marked up and it is stopped, then 1042 * start it. 1043 */ 1044 beinit(sc); 1045 } else { 1046 /* 1047 * Reset the interface to pick up changes in any other 1048 * flags that affect hardware registers. 1049 */ 1050 bestop(sc); 1051 beinit(sc); 1052 } 1053 #ifdef BEDEBUG 1054 if (ifp->if_flags & IFF_DEBUG) 1055 sc->sc_debug = 1; 1056 else 1057 sc->sc_debug = 0; 1058 #endif 1059 break; 1060 1061 case SIOCADDMULTI: 1062 case SIOCDELMULTI: 1063 error = (cmd == SIOCADDMULTI) ? 1064 ether_addmulti(ifr, &sc->sc_ethercom): 1065 ether_delmulti(ifr, &sc->sc_ethercom); 1066 1067 if (error == ENETRESET) { 1068 /* 1069 * Multicast list has changed; set the hardware filter 1070 * accordingly. 1071 */ 1072 be_mcreset(sc); 1073 error = 0; 1074 } 1075 break; 1076 case SIOCGIFMEDIA: 1077 case SIOCSIFMEDIA: 1078 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1079 break; 1080 default: 1081 error = EINVAL; 1082 break; 1083 } 1084 splx(s); 1085 return (error); 1086 } 1087 1088 1089 void 1090 beinit(sc) 1091 struct be_softc *sc; 1092 { 1093 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1094 bus_space_tag_t t = sc->sc_bustag; 1095 bus_space_handle_t br = sc->sc_br; 1096 bus_space_handle_t cr = sc->sc_cr; 1097 struct qec_softc *qec = sc->sc_qec; 1098 u_int32_t v; 1099 u_int32_t qecaddr; 1100 u_int8_t *ea; 1101 int s; 1102 1103 s = splnet(); 1104 1105 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1106 1107 bestop(sc); 1108 1109 ea = sc->sc_enaddr; 1110 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1111 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1112 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1113 1114 /* Clear hash table */ 1115 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1116 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1117 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1118 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1119 1120 /* Re-initialize RX configuration */ 1121 v = BE_BR_RXCFG_FIFO; 1122 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1123 1124 be_mcreset(sc); 1125 1126 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1127 1128 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1129 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1130 1131 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1132 1133 /* 1134 * Turn off counter expiration interrupts as well as 1135 * 'gotframe' and 'sentframe' 1136 */ 1137 bus_space_write_4(t, br, BE_BRI_IMASK, 1138 BE_BR_IMASK_GOTFRAME | 1139 BE_BR_IMASK_RCNTEXP | 1140 BE_BR_IMASK_ACNTEXP | 1141 BE_BR_IMASK_CCNTEXP | 1142 BE_BR_IMASK_LCNTEXP | 1143 BE_BR_IMASK_CVCNTEXP | 1144 BE_BR_IMASK_SENTFRAME | 1145 BE_BR_IMASK_NCNTEXP | 1146 BE_BR_IMASK_ECNTEXP | 1147 BE_BR_IMASK_LCCNTEXP | 1148 BE_BR_IMASK_FCNTEXP | 1149 BE_BR_IMASK_DTIMEXP); 1150 1151 /* Channel registers: */ 1152 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1153 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1154 1155 qecaddr = sc->sc_channel * qec->sc_msize; 1156 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1157 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1158 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1159 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1160 1161 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1162 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1163 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1164 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1165 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1166 1167 /* Set max packet length */ 1168 v = ETHER_MAX_LEN; 1169 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1170 v += ETHER_VLAN_ENCAP_LEN; 1171 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1172 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1173 1174 /* Enable transmitter */ 1175 bus_space_write_4(t, br, BE_BRI_TXCFG, 1176 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1177 1178 /* Enable receiver */ 1179 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1180 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1181 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1182 1183 ifp->if_flags |= IFF_RUNNING; 1184 ifp->if_flags &= ~IFF_OACTIVE; 1185 1186 be_ifmedia_upd(ifp); 1187 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1188 splx(s); 1189 } 1190 1191 void 1192 be_mcreset(sc) 1193 struct be_softc *sc; 1194 { 1195 struct ethercom *ec = &sc->sc_ethercom; 1196 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1197 bus_space_tag_t t = sc->sc_bustag; 1198 bus_space_handle_t br = sc->sc_br; 1199 u_int32_t crc; 1200 u_int16_t hash[4]; 1201 u_int8_t octet; 1202 u_int32_t v; 1203 int i, j; 1204 struct ether_multi *enm; 1205 struct ether_multistep step; 1206 1207 if (ifp->if_flags & IFF_PROMISC) { 1208 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1209 v |= BE_BR_RXCFG_PMISC; 1210 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1211 return; 1212 } 1213 1214 if (ifp->if_flags & IFF_ALLMULTI) { 1215 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1216 goto chipit; 1217 } 1218 1219 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1220 1221 ETHER_FIRST_MULTI(step, ec, enm); 1222 while (enm != NULL) { 1223 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1224 /* 1225 * We must listen to a range of multicast 1226 * addresses. For now, just accept all 1227 * multicasts, rather than trying to set only 1228 * those filter bits needed to match the range. 1229 * (At this time, the only use of address 1230 * ranges is for IP multicast routing, for 1231 * which the range is big enough to require 1232 * all bits set.) 1233 */ 1234 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1235 ifp->if_flags |= IFF_ALLMULTI; 1236 goto chipit; 1237 } 1238 1239 crc = 0xffffffff; 1240 1241 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1242 octet = enm->enm_addrlo[i]; 1243 1244 for (j = 0; j < 8; j++) { 1245 if ((crc & 1) ^ (octet & 1)) { 1246 crc >>= 1; 1247 crc ^= MC_POLY_LE; 1248 } 1249 else 1250 crc >>= 1; 1251 octet >>= 1; 1252 } 1253 } 1254 1255 crc >>= 26; 1256 hash[crc >> 4] |= 1 << (crc & 0xf); 1257 ETHER_NEXT_MULTI(step, enm); 1258 } 1259 1260 ifp->if_flags &= ~IFF_ALLMULTI; 1261 1262 chipit: 1263 /* Enable the hash filter */ 1264 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1265 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1266 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1267 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1268 1269 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1270 v &= ~BE_BR_RXCFG_PMISC; 1271 v |= BE_BR_RXCFG_HENABLE; 1272 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1273 } 1274 1275 /* 1276 * Set the tcvr to an idle state 1277 */ 1278 void 1279 be_mii_sync(sc) 1280 struct be_softc *sc; 1281 { 1282 bus_space_tag_t t = sc->sc_bustag; 1283 bus_space_handle_t tr = sc->sc_tr; 1284 int n = 32; 1285 1286 while (n--) { 1287 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1288 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1289 MGMT_PAL_OENAB); 1290 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1291 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1292 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1293 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1294 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1295 } 1296 } 1297 1298 void 1299 be_pal_gate(sc, phy) 1300 struct be_softc *sc; 1301 int phy; 1302 { 1303 bus_space_tag_t t = sc->sc_bustag; 1304 bus_space_handle_t tr = sc->sc_tr; 1305 u_int32_t v; 1306 1307 be_mii_sync(sc); 1308 1309 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1310 if (phy == BE_PHY_INTERNAL) 1311 v &= ~TCVR_PAL_SERIAL; 1312 1313 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1314 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1315 } 1316 1317 static int 1318 be_tcvr_read_bit(sc, phy) 1319 struct be_softc *sc; 1320 int phy; 1321 { 1322 bus_space_tag_t t = sc->sc_bustag; 1323 bus_space_handle_t tr = sc->sc_tr; 1324 int ret; 1325 1326 if (phy == BE_PHY_INTERNAL) { 1327 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1328 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1329 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1330 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1331 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1332 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1333 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1334 } else { 1335 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1336 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1337 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1338 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1339 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1340 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1341 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1342 } 1343 1344 return (ret); 1345 } 1346 1347 static void 1348 be_tcvr_write_bit(sc, phy, bit) 1349 struct be_softc *sc; 1350 int phy; 1351 int bit; 1352 { 1353 bus_space_tag_t t = sc->sc_bustag; 1354 bus_space_handle_t tr = sc->sc_tr; 1355 u_int32_t v; 1356 1357 if (phy == BE_PHY_INTERNAL) { 1358 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1359 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1360 } else { 1361 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1362 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1363 } 1364 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1365 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1366 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1367 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1368 } 1369 1370 static void 1371 be_mii_sendbits(sc, phy, data, nbits) 1372 struct be_softc *sc; 1373 int phy; 1374 u_int32_t data; 1375 int nbits; 1376 { 1377 int i; 1378 1379 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1380 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1381 } 1382 } 1383 1384 static int 1385 be_mii_readreg(self, phy, reg) 1386 struct device *self; 1387 int phy, reg; 1388 { 1389 struct be_softc *sc = (struct be_softc *)self; 1390 int val = 0, i; 1391 1392 /* 1393 * Read the PHY register by manually driving the MII control lines. 1394 */ 1395 be_mii_sync(sc); 1396 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1397 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1398 be_mii_sendbits(sc, phy, phy, 5); 1399 be_mii_sendbits(sc, phy, reg, 5); 1400 1401 (void) be_tcvr_read_bit(sc, phy); 1402 (void) be_tcvr_read_bit(sc, phy); 1403 1404 for (i = 15; i >= 0; i--) 1405 val |= (be_tcvr_read_bit(sc, phy) << i); 1406 1407 (void) be_tcvr_read_bit(sc, phy); 1408 (void) be_tcvr_read_bit(sc, phy); 1409 (void) be_tcvr_read_bit(sc, phy); 1410 1411 return (val); 1412 } 1413 1414 void 1415 be_mii_writereg(self, phy, reg, val) 1416 struct device *self; 1417 int phy, reg, val; 1418 { 1419 struct be_softc *sc = (struct be_softc *)self; 1420 int i; 1421 1422 /* 1423 * Write the PHY register by manually driving the MII control lines. 1424 */ 1425 be_mii_sync(sc); 1426 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1427 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1428 be_mii_sendbits(sc, phy, phy, 5); 1429 be_mii_sendbits(sc, phy, reg, 5); 1430 1431 be_tcvr_write_bit(sc, phy, 1); 1432 be_tcvr_write_bit(sc, phy, 0); 1433 1434 for (i = 15; i >= 0; i--) 1435 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1436 } 1437 1438 int 1439 be_mii_reset(sc, phy) 1440 struct be_softc *sc; 1441 int phy; 1442 { 1443 int n; 1444 1445 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1446 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1447 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1448 1449 for (n = 16; n >= 0; n--) { 1450 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1451 if ((bmcr & BMCR_RESET) == 0) 1452 break; 1453 DELAY(20); 1454 } 1455 if (n == 0) { 1456 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1457 return (EIO); 1458 } 1459 1460 return (0); 1461 } 1462 1463 void 1464 be_tick(arg) 1465 void *arg; 1466 { 1467 struct be_softc *sc = arg; 1468 int s = splnet(); 1469 1470 mii_tick(&sc->sc_mii); 1471 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1472 1473 splx(s); 1474 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1475 } 1476 1477 void 1478 be_mii_statchg(self) 1479 struct device *self; 1480 { 1481 struct be_softc *sc = (struct be_softc *)self; 1482 bus_space_tag_t t = sc->sc_bustag; 1483 bus_space_handle_t br = sc->sc_br; 1484 u_int instance; 1485 u_int32_t v; 1486 1487 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1488 #ifdef DIAGNOSTIC 1489 if (instance > 1) 1490 panic("be_mii_statchg: instance %d out of range", instance); 1491 #endif 1492 1493 /* Update duplex mode in TX configuration */ 1494 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1495 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1496 v |= BE_BR_TXCFG_FULLDPLX; 1497 else 1498 v &= ~BE_BR_TXCFG_FULLDPLX; 1499 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1500 1501 /* Change to appropriate gate in transceiver PAL */ 1502 be_pal_gate(sc, sc->sc_phys[instance]); 1503 } 1504 1505 /* 1506 * Get current media settings. 1507 */ 1508 void 1509 be_ifmedia_sts(ifp, ifmr) 1510 struct ifnet *ifp; 1511 struct ifmediareq *ifmr; 1512 { 1513 struct be_softc *sc = ifp->if_softc; 1514 1515 mii_pollstat(&sc->sc_mii); 1516 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1517 1518 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1519 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1520 return; 1521 } 1522 1523 /* 1524 * Set media options. 1525 */ 1526 int 1527 be_ifmedia_upd(ifp) 1528 struct ifnet *ifp; 1529 { 1530 struct be_softc *sc = ifp->if_softc; 1531 int error; 1532 1533 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1534 return (error); 1535 1536 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1537 } 1538 1539 /* 1540 * Service routine for our pseudo-MII internal transceiver. 1541 */ 1542 int 1543 be_intphy_service(sc, mii, cmd) 1544 struct be_softc *sc; 1545 struct mii_data *mii; 1546 int cmd; 1547 { 1548 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1549 int bmcr, bmsr; 1550 int error; 1551 1552 switch (cmd) { 1553 case MII_POLLSTAT: 1554 /* 1555 * If we're not polling our PHY instance, just return. 1556 */ 1557 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1558 return (0); 1559 1560 break; 1561 1562 case MII_MEDIACHG: 1563 1564 /* 1565 * If the media indicates a different PHY instance, 1566 * isolate ourselves. 1567 */ 1568 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1569 bmcr = be_mii_readreg((void *)sc, 1570 BE_PHY_INTERNAL, MII_BMCR); 1571 be_mii_writereg((void *)sc, 1572 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1573 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1574 sc->sc_intphy_curspeed = 0; 1575 return (0); 1576 } 1577 1578 1579 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1580 return (error); 1581 1582 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1583 1584 /* 1585 * Select the new mode and take out of isolation 1586 */ 1587 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1588 bmcr |= BMCR_S100; 1589 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1590 bmcr &= ~BMCR_S100; 1591 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1592 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1593 bmcr &= ~BMCR_S100; 1594 bmcr |= sc->sc_intphy_curspeed; 1595 } else { 1596 /* Keep isolated until link is up */ 1597 bmcr |= BMCR_ISO; 1598 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1599 } 1600 } 1601 1602 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1603 bmcr |= BMCR_FDX; 1604 else 1605 bmcr &= ~BMCR_FDX; 1606 1607 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1608 break; 1609 1610 case MII_TICK: 1611 /* 1612 * If we're not currently selected, just return. 1613 */ 1614 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1615 return (0); 1616 1617 /* Only used for automatic media selection */ 1618 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1619 return (0); 1620 1621 /* Is the interface even up? */ 1622 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1623 return (0); 1624 1625 /* 1626 * Check link status; if we don't have a link, try another 1627 * speed. We can't detect duplex mode, so half-duplex is 1628 * what we have to settle for. 1629 */ 1630 1631 /* Read twice in case the register is latched */ 1632 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1633 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1634 1635 if ((bmsr & BMSR_LINK) != 0) { 1636 /* We have a carrier */ 1637 bmcr = be_mii_readreg((void *)sc, 1638 BE_PHY_INTERNAL, MII_BMCR); 1639 1640 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1641 bmcr = be_mii_readreg((void *)sc, 1642 BE_PHY_INTERNAL, MII_BMCR); 1643 1644 sc->sc_mii_flags |= MIIF_HAVELINK; 1645 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1646 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1647 1648 bmcr &= ~BMCR_ISO; 1649 be_mii_writereg((void *)sc, 1650 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1651 1652 printf("%s: link up at %s Mbps\n", 1653 sc->sc_dev.dv_xname, 1654 (bmcr & BMCR_S100) ? "100" : "10"); 1655 } 1656 return (0); 1657 } 1658 1659 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1660 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1661 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1662 sc->sc_intphy_curspeed = 0; 1663 printf("%s: link down\n", sc->sc_dev.dv_xname); 1664 } 1665 1666 /* Only retry autonegotiation every 5 seconds. */ 1667 if (++sc->sc_mii_ticks < 5) 1668 return(0); 1669 1670 sc->sc_mii_ticks = 0; 1671 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1672 /* Just flip the fast speed bit */ 1673 bmcr ^= BMCR_S100; 1674 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1675 1676 break; 1677 1678 case MII_DOWN: 1679 /* Isolate this phy */ 1680 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1681 be_mii_writereg((void *)sc, 1682 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1683 return (0); 1684 } 1685 1686 /* Update the media status. */ 1687 be_intphy_status(sc); 1688 1689 /* Callback if something changed. */ 1690 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1691 (*mii->mii_statchg)((struct device *)sc); 1692 sc->sc_mii_active = mii->mii_media_active; 1693 } 1694 return (0); 1695 } 1696 1697 /* 1698 * Determine status of internal transceiver 1699 */ 1700 void 1701 be_intphy_status(sc) 1702 struct be_softc *sc; 1703 { 1704 struct mii_data *mii = &sc->sc_mii; 1705 int media_active, media_status; 1706 int bmcr, bmsr; 1707 1708 media_status = IFM_AVALID; 1709 media_active = 0; 1710 1711 /* 1712 * Internal transceiver; do the work here. 1713 */ 1714 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1715 1716 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1717 case (BMCR_S100 | BMCR_FDX): 1718 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1719 break; 1720 case BMCR_S100: 1721 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1722 break; 1723 case BMCR_FDX: 1724 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1725 break; 1726 case 0: 1727 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1728 break; 1729 } 1730 1731 /* Read twice in case the register is latched */ 1732 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1733 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1734 if (bmsr & BMSR_LINK) 1735 media_status |= IFM_ACTIVE; 1736 1737 mii->mii_media_status = media_status; 1738 mii->mii_media_active = media_active; 1739 } 1740
Indexes created Mon Sep 29 21:09:56 GMT 2025