be.c revision 1.52
1 /* $NetBSD: be.c,v 1.52 2007/03/04 07:54:11 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.52 2007/03/04 07:54:11 christos Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_inet.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #include <net/bpfdesc.h> 108 #endif 109 110 #include <machine/bus.h> 111 #include <machine/intr.h> 112 #include <machine/autoconf.h> 113 114 #include <dev/sbus/sbusvar.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #include <dev/sbus/qecreg.h> 120 #include <dev/sbus/qecvar.h> 121 #include <dev/sbus/bereg.h> 122 123 struct be_softc { 124 struct device sc_dev; 125 struct sbusdev sc_sd; /* sbus device */ 126 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 127 bus_dma_tag_t sc_dmatag; 128 bus_dmamap_t sc_dmamap; 129 struct ethercom sc_ethercom; 130 /*struct ifmedia sc_ifmedia; -* interface media */ 131 struct mii_data sc_mii; /* MII media control */ 132 #define sc_media sc_mii.mii_media/* shorthand */ 133 int sc_phys[2]; /* MII instance -> phy */ 134 135 struct callout sc_tick_ch; 136 137 /* 138 * Some `mii_softc' items we need to emulate MII operation 139 * for our internal transceiver. 140 */ 141 int sc_mii_inst; /* instance of internal phy */ 142 int sc_mii_active; /* currently active medium */ 143 int sc_mii_ticks; /* tick counter */ 144 int sc_mii_flags; /* phy status flags */ 145 #define MIIF_HAVELINK 0x04000000 146 int sc_intphy_curspeed; /* Established link speed */ 147 148 struct qec_softc *sc_qec; /* QEC parent */ 149 150 bus_space_handle_t sc_qr; /* QEC registers */ 151 bus_space_handle_t sc_br; /* BE registers */ 152 bus_space_handle_t sc_cr; /* channel registers */ 153 bus_space_handle_t sc_tr; /* transceiver registers */ 154 155 u_int sc_rev; 156 157 int sc_channel; /* channel number */ 158 int sc_burst; 159 160 struct qec_ring sc_rb; /* Packet Ring Buffer */ 161 162 /* MAC address */ 163 u_int8_t sc_enaddr[6]; 164 #ifdef BEDEBUG 165 int sc_debug; 166 #endif 167 }; 168 169 int bematch(struct device *, struct cfdata *, void *); 170 void beattach(struct device *, struct device *, void *); 171 172 void beinit(struct be_softc *); 173 void bestart(struct ifnet *); 174 void bestop(struct be_softc *); 175 void bewatchdog(struct ifnet *); 176 int beioctl(struct ifnet *, u_long, void *); 177 void bereset(struct be_softc *); 178 179 int beintr(void *); 180 int berint(struct be_softc *); 181 int betint(struct be_softc *); 182 int beqint(struct be_softc *, u_int32_t); 183 int beeint(struct be_softc *, u_int32_t); 184 185 static void be_read(struct be_softc *, int, int); 186 static int be_put(struct be_softc *, int, struct mbuf *); 187 static struct mbuf *be_get(struct be_softc *, int, int); 188 189 void be_pal_gate(struct be_softc *, int); 190 191 /* ifmedia callbacks */ 192 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 193 int be_ifmedia_upd(struct ifnet *); 194 195 void be_mcreset(struct be_softc *); 196 197 /* MII methods & callbacks */ 198 static int be_mii_readreg(struct device *, int, int); 199 static void be_mii_writereg(struct device *, int, int, int); 200 static void be_mii_statchg(struct device *); 201 202 /* MII helpers */ 203 static void be_mii_sync(struct be_softc *); 204 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 205 static int be_mii_reset(struct be_softc *, int); 206 static int be_tcvr_read_bit(struct be_softc *, int); 207 static void be_tcvr_write_bit(struct be_softc *, int, int); 208 209 void be_tick(void *); 210 void be_intphy_auto(struct be_softc *); 211 void be_intphy_status(struct be_softc *); 212 int be_intphy_service(struct be_softc *, struct mii_data *, int); 213 214 215 CFATTACH_DECL(be, sizeof(struct be_softc), 216 bematch, beattach, NULL, NULL); 217 218 int 219 bematch(parent, cf, aux) 220 struct device *parent; 221 struct cfdata *cf; 222 void *aux; 223 { 224 struct sbus_attach_args *sa = aux; 225 226 return (strcmp(cf->cf_name, sa->sa_name) == 0); 227 } 228 229 void 230 beattach(parent, self, aux) 231 struct device *parent, *self; 232 void *aux; 233 { 234 struct sbus_attach_args *sa = aux; 235 struct qec_softc *qec = (struct qec_softc *)parent; 236 struct be_softc *sc = (struct be_softc *)self; 237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 238 struct mii_data *mii = &sc->sc_mii; 239 struct mii_softc *child; 240 int node = sa->sa_node; 241 bus_dma_tag_t dmatag = sa->sa_dmatag; 242 bus_dma_segment_t seg; 243 bus_size_t size; 244 int instance; 245 int rseg, error; 246 u_int32_t v; 247 248 if (sa->sa_nreg < 3) { 249 printf("%s: only %d register sets\n", 250 self->dv_xname, sa->sa_nreg); 251 return; 252 } 253 254 if (bus_space_map(sa->sa_bustag, 255 (bus_addr_t)BUS_ADDR( 256 sa->sa_reg[0].oa_space, 257 sa->sa_reg[0].oa_base), 258 (bus_size_t)sa->sa_reg[0].oa_size, 259 0, &sc->sc_cr) != 0) { 260 printf("beattach: cannot map registers\n"); 261 return; 262 } 263 264 if (bus_space_map(sa->sa_bustag, 265 (bus_addr_t)BUS_ADDR( 266 sa->sa_reg[1].oa_space, 267 sa->sa_reg[1].oa_base), 268 (bus_size_t)sa->sa_reg[1].oa_size, 269 0, &sc->sc_br) != 0) { 270 printf("beattach: cannot map registers\n"); 271 return; 272 } 273 274 if (bus_space_map(sa->sa_bustag, 275 (bus_addr_t)BUS_ADDR( 276 sa->sa_reg[2].oa_space, 277 sa->sa_reg[2].oa_base), 278 (bus_size_t)sa->sa_reg[2].oa_size, 279 0, &sc->sc_tr) != 0) { 280 printf("beattach: cannot map registers\n"); 281 return; 282 } 283 284 sc->sc_bustag = sa->sa_bustag; 285 sc->sc_qec = qec; 286 sc->sc_qr = qec->sc_regs; 287 288 sc->sc_rev = prom_getpropint(node, "board-version", -1); 289 printf(" rev %x", sc->sc_rev); 290 291 bestop(sc); 292 293 sc->sc_channel = prom_getpropint(node, "channel#", -1); 294 if (sc->sc_channel == -1) 295 sc->sc_channel = 0; 296 297 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 298 if (sc->sc_burst == -1) 299 sc->sc_burst = qec->sc_burst; 300 301 /* Clamp at parent's burst sizes */ 302 sc->sc_burst &= qec->sc_burst; 303 304 /* Establish interrupt handler */ 305 if (sa->sa_nintr) 306 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 307 beintr, sc); 308 309 prom_getether(node, sc->sc_enaddr); 310 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 311 312 /* 313 * Allocate descriptor ring and buffers. 314 */ 315 316 /* for now, allocate as many bufs as there are ring descriptors */ 317 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 318 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 319 320 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 321 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 322 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 323 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 324 325 /* Get a DMA handle */ 326 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 327 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 328 printf("%s: DMA map create error %d\n", self->dv_xname, error); 329 return; 330 } 331 332 /* Allocate DMA buffer */ 333 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 334 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 335 printf("%s: DMA buffer alloc error %d\n", 336 self->dv_xname, error); 337 return; 338 } 339 340 /* Map DMA memory in CPU addressable space */ 341 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 342 &sc->sc_rb.rb_membase, 343 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 344 printf("%s: DMA buffer map error %d\n", 345 self->dv_xname, error); 346 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 347 return; 348 } 349 350 /* Load the buffer */ 351 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 352 sc->sc_rb.rb_membase, size, NULL, 353 BUS_DMA_NOWAIT)) != 0) { 354 printf("%s: DMA buffer map load error %d\n", 355 self->dv_xname, error); 356 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 357 bus_dmamem_free(dmatag, &seg, rseg); 358 return; 359 } 360 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 361 362 /* 363 * Initialize our media structures and MII info. 364 */ 365 mii->mii_ifp = ifp; 366 mii->mii_readreg = be_mii_readreg; 367 mii->mii_writereg = be_mii_writereg; 368 mii->mii_statchg = be_mii_statchg; 369 370 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 371 372 callout_init(&sc->sc_tick_ch); 373 374 /* 375 * Initialize transceiver and determine which PHY connection to use. 376 */ 377 be_mii_sync(sc); 378 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 379 380 instance = 0; 381 382 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 383 384 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 385 MII_OFFSET_ANY, 0); 386 387 child = LIST_FIRST(&mii->mii_phys); 388 if (child == NULL) { 389 /* No PHY attached */ 390 ifmedia_add(&sc->sc_media, 391 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 392 0, NULL); 393 ifmedia_set(&sc->sc_media, 394 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 395 } else { 396 /* 397 * Note: we support just one PHY on the external 398 * MII connector. 399 */ 400 #ifdef DIAGNOSTIC 401 if (LIST_NEXT(child, mii_list) != NULL) { 402 printf("%s: spurious MII device %s attached\n", 403 sc->sc_dev.dv_xname, 404 child->mii_dev.dv_xname); 405 } 406 #endif 407 if (child->mii_phy != BE_PHY_EXTERNAL || 408 child->mii_inst > 0) { 409 printf("%s: cannot accommodate MII device %s" 410 " at phy %d, instance %d\n", 411 sc->sc_dev.dv_xname, 412 child->mii_dev.dv_xname, 413 child->mii_phy, child->mii_inst); 414 } else { 415 sc->sc_phys[instance] = child->mii_phy; 416 } 417 418 /* 419 * XXX - we can really do the following ONLY if the 420 * phy indeed has the auto negotiation capability!! 421 */ 422 ifmedia_set(&sc->sc_media, 423 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 424 425 /* Mark our current media setting */ 426 be_pal_gate(sc, BE_PHY_EXTERNAL); 427 instance++; 428 } 429 430 } 431 432 if ((v & MGMT_PAL_INT_MDIO) != 0) { 433 /* 434 * The be internal phy looks vaguely like MII hardware, 435 * but not enough to be able to use the MII device 436 * layer. Hence, we have to take care of media selection 437 * ourselves. 438 */ 439 440 sc->sc_mii_inst = instance; 441 sc->sc_phys[instance] = BE_PHY_INTERNAL; 442 443 /* Use `ifm_data' to store BMCR bits */ 444 ifmedia_add(&sc->sc_media, 445 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 446 0, NULL); 447 ifmedia_add(&sc->sc_media, 448 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 449 BMCR_S100, NULL); 450 ifmedia_add(&sc->sc_media, 451 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 452 0, NULL); 453 454 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 455 self->dv_xname); 456 457 be_mii_reset(sc, BE_PHY_INTERNAL); 458 /* Only set default medium here if there's no external PHY */ 459 if (instance == 0) { 460 be_pal_gate(sc, BE_PHY_INTERNAL); 461 ifmedia_set(&sc->sc_media, 462 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 463 } else 464 be_mii_writereg((void *)sc, 465 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 466 } 467 468 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 469 ifp->if_softc = sc; 470 ifp->if_start = bestart; 471 ifp->if_ioctl = beioctl; 472 ifp->if_watchdog = bewatchdog; 473 ifp->if_flags = 474 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 475 IFQ_SET_READY(&ifp->if_snd); 476 477 /* claim 802.1q capability */ 478 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 479 480 /* Attach the interface. */ 481 if_attach(ifp); 482 ether_ifattach(ifp, sc->sc_enaddr); 483 } 484 485 486 /* 487 * Routine to copy from mbuf chain to transmit buffer in 488 * network buffer memory. 489 */ 490 static inline int 491 be_put(sc, idx, m) 492 struct be_softc *sc; 493 int idx; 494 struct mbuf *m; 495 { 496 struct mbuf *n; 497 int len, tlen = 0, boff = 0; 498 void *bp; 499 500 bp = (char *)sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 501 502 for (; m; m = n) { 503 len = m->m_len; 504 if (len == 0) { 505 MFREE(m, n); 506 continue; 507 } 508 memcpy((char *)bp + boff, mtod(m, void *), len); 509 boff += len; 510 tlen += len; 511 MFREE(m, n); 512 } 513 return (tlen); 514 } 515 516 /* 517 * Pull data off an interface. 518 * Len is the length of data, with local net header stripped. 519 * We copy the data into mbufs. When full cluster sized units are present, 520 * we copy into clusters. 521 */ 522 static inline struct mbuf * 523 be_get(sc, idx, totlen) 524 struct be_softc *sc; 525 int idx, totlen; 526 { 527 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 528 struct mbuf *m; 529 struct mbuf *top, **mp; 530 int len, pad, boff = 0; 531 void *bp; 532 533 bp = (char *)sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 534 535 MGETHDR(m, M_DONTWAIT, MT_DATA); 536 if (m == NULL) 537 return (NULL); 538 m->m_pkthdr.rcvif = ifp; 539 m->m_pkthdr.len = totlen; 540 541 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 542 m->m_data += pad; 543 len = MHLEN - pad; 544 top = NULL; 545 mp = ⊤ 546 547 while (totlen > 0) { 548 if (top) { 549 MGET(m, M_DONTWAIT, MT_DATA); 550 if (m == NULL) { 551 m_freem(top); 552 return (NULL); 553 } 554 len = MLEN; 555 } 556 if (top && totlen >= MINCLSIZE) { 557 MCLGET(m, M_DONTWAIT); 558 if (m->m_flags & M_EXT) 559 len = MCLBYTES; 560 } 561 m->m_len = len = min(totlen, len); 562 memcpy(mtod(m, void *), (char *)bp + boff, len); 563 boff += len; 564 totlen -= len; 565 *mp = m; 566 mp = &m->m_next; 567 } 568 569 return (top); 570 } 571 572 /* 573 * Pass a packet to the higher levels. 574 */ 575 static inline void 576 be_read(sc, idx, len) 577 struct be_softc *sc; 578 int idx, len; 579 { 580 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 581 struct mbuf *m; 582 583 if (len <= sizeof(struct ether_header) || 584 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 585 #ifdef BEDEBUG 586 if (sc->sc_debug) 587 printf("%s: invalid packet size %d; dropping\n", 588 ifp->if_xname, len); 589 #endif 590 ifp->if_ierrors++; 591 return; 592 } 593 594 /* 595 * Pull packet off interface. 596 */ 597 m = be_get(sc, idx, len); 598 if (m == NULL) { 599 ifp->if_ierrors++; 600 return; 601 } 602 ifp->if_ipackets++; 603 604 #if NBPFILTER > 0 605 /* 606 * Check if there's a BPF listener on this interface. 607 * If so, hand off the raw packet to BPF. 608 */ 609 if (ifp->if_bpf) 610 bpf_mtap(ifp->if_bpf, m); 611 #endif 612 /* Pass the packet up. */ 613 (*ifp->if_input)(ifp, m); 614 } 615 616 /* 617 * Start output on interface. 618 * We make two assumptions here: 619 * 1) that the current priority is set to splnet _before_ this code 620 * is called *and* is returned to the appropriate priority after 621 * return 622 * 2) that the IFF_OACTIVE flag is checked before this code is called 623 * (i.e. that the output part of the interface is idle) 624 */ 625 void 626 bestart(ifp) 627 struct ifnet *ifp; 628 { 629 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 630 struct qec_xd *txd = sc->sc_rb.rb_txd; 631 struct mbuf *m; 632 unsigned int bix, len; 633 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 634 635 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 636 return; 637 638 bix = sc->sc_rb.rb_tdhead; 639 640 for (;;) { 641 IFQ_DEQUEUE(&ifp->if_snd, m); 642 if (m == 0) 643 break; 644 645 #if NBPFILTER > 0 646 /* 647 * If BPF is listening on this interface, let it see the 648 * packet before we commit it to the wire. 649 */ 650 if (ifp->if_bpf) 651 bpf_mtap(ifp->if_bpf, m); 652 #endif 653 654 /* 655 * Copy the mbuf chain into the transmit buffer. 656 */ 657 len = be_put(sc, bix, m); 658 659 /* 660 * Initialize transmit registers and start transmission 661 */ 662 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 663 (len & QEC_XD_LENGTH); 664 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 665 BE_CR_CTRL_TWAKEUP); 666 667 if (++bix == QEC_XD_RING_MAXSIZE) 668 bix = 0; 669 670 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 671 ifp->if_flags |= IFF_OACTIVE; 672 break; 673 } 674 } 675 676 sc->sc_rb.rb_tdhead = bix; 677 } 678 679 void 680 bestop(sc) 681 struct be_softc *sc; 682 { 683 int n; 684 bus_space_tag_t t = sc->sc_bustag; 685 bus_space_handle_t br = sc->sc_br; 686 687 callout_stop(&sc->sc_tick_ch); 688 689 /* Down the MII. */ 690 mii_down(&sc->sc_mii); 691 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 692 693 /* Stop the transmitter */ 694 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 695 for (n = 32; n > 0; n--) { 696 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 697 break; 698 DELAY(20); 699 } 700 701 /* Stop the receiver */ 702 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 703 for (n = 32; n > 0; n--) { 704 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 705 break; 706 DELAY(20); 707 } 708 } 709 710 /* 711 * Reset interface. 712 */ 713 void 714 bereset(sc) 715 struct be_softc *sc; 716 { 717 int s; 718 719 s = splnet(); 720 bestop(sc); 721 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 722 beinit(sc); 723 splx(s); 724 } 725 726 void 727 bewatchdog(ifp) 728 struct ifnet *ifp; 729 { 730 struct be_softc *sc = ifp->if_softc; 731 732 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 733 ++sc->sc_ethercom.ec_if.if_oerrors; 734 735 bereset(sc); 736 } 737 738 int 739 beintr(v) 740 void *v; 741 { 742 struct be_softc *sc = (struct be_softc *)v; 743 bus_space_tag_t t = sc->sc_bustag; 744 u_int32_t whyq, whyb, whyc; 745 int r = 0; 746 747 /* Read QEC status, channel status and BE status */ 748 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 749 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 750 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 751 752 if (whyq & QEC_STAT_BM) 753 r |= beeint(sc, whyb); 754 755 if (whyq & QEC_STAT_ER) 756 r |= beqint(sc, whyc); 757 758 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 759 r |= betint(sc); 760 761 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 762 r |= berint(sc); 763 764 return (r); 765 } 766 767 /* 768 * QEC Interrupt. 769 */ 770 int 771 beqint(sc, why) 772 struct be_softc *sc; 773 u_int32_t why; 774 { 775 int r = 0, rst = 0; 776 777 if (why & BE_CR_STAT_TXIRQ) 778 r |= 1; 779 if (why & BE_CR_STAT_RXIRQ) 780 r |= 1; 781 782 if (why & BE_CR_STAT_BERROR) { 783 r |= 1; 784 rst = 1; 785 printf("%s: bigmac error\n", sc->sc_dev.dv_xname); 786 } 787 788 if (why & BE_CR_STAT_TXDERR) { 789 r |= 1; 790 rst = 1; 791 printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname); 792 } 793 794 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 795 r |= 1; 796 rst = 1; 797 printf("%s: tx DMA error ( ", sc->sc_dev.dv_xname); 798 if (why & BE_CR_STAT_TXLERR) 799 printf("Late "); 800 if (why & BE_CR_STAT_TXPERR) 801 printf("Parity "); 802 if (why & BE_CR_STAT_TXSERR) 803 printf("Generic "); 804 printf(")\n"); 805 } 806 807 if (why & BE_CR_STAT_RXDROP) { 808 r |= 1; 809 rst = 1; 810 printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname); 811 } 812 813 if (why & BE_CR_STAT_RXSMALL) { 814 r |= 1; 815 rst = 1; 816 printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname); 817 } 818 819 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 820 r |= 1; 821 rst = 1; 822 printf("%s: rx DMA error ( ", sc->sc_dev.dv_xname); 823 if (why & BE_CR_STAT_RXLERR) 824 printf("Late "); 825 if (why & BE_CR_STAT_RXPERR) 826 printf("Parity "); 827 if (why & BE_CR_STAT_RXSERR) 828 printf("Generic "); 829 printf(")\n"); 830 } 831 832 if (!r) { 833 rst = 1; 834 printf("%s: unexpected error interrupt %08x\n", 835 sc->sc_dev.dv_xname, why); 836 } 837 838 if (rst) { 839 printf("%s: resetting\n", sc->sc_dev.dv_xname); 840 bereset(sc); 841 } 842 843 return (r); 844 } 845 846 /* 847 * Error interrupt. 848 */ 849 int 850 beeint(sc, why) 851 struct be_softc *sc; 852 u_int32_t why; 853 { 854 int r = 0, rst = 0; 855 856 if (why & BE_BR_STAT_RFIFOVF) { 857 r |= 1; 858 rst = 1; 859 printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname); 860 } 861 if (why & BE_BR_STAT_TFIFO_UND) { 862 r |= 1; 863 rst = 1; 864 printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname); 865 } 866 if (why & BE_BR_STAT_MAXPKTERR) { 867 r |= 1; 868 rst = 1; 869 printf("%s: max packet size error\n", sc->sc_dev.dv_xname); 870 } 871 872 if (!r) { 873 rst = 1; 874 printf("%s: unexpected error interrupt %08x\n", 875 sc->sc_dev.dv_xname, why); 876 } 877 878 if (rst) { 879 printf("%s: resetting\n", sc->sc_dev.dv_xname); 880 bereset(sc); 881 } 882 883 return (r); 884 } 885 886 /* 887 * Transmit interrupt. 888 */ 889 int 890 betint(sc) 891 struct be_softc *sc; 892 { 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 bus_space_tag_t t = sc->sc_bustag; 895 bus_space_handle_t br = sc->sc_br; 896 unsigned int bix, txflags; 897 898 /* 899 * Unload collision counters 900 */ 901 ifp->if_collisions += 902 bus_space_read_4(t, br, BE_BRI_NCCNT) + 903 bus_space_read_4(t, br, BE_BRI_FCCNT) + 904 bus_space_read_4(t, br, BE_BRI_EXCNT) + 905 bus_space_read_4(t, br, BE_BRI_LTCNT); 906 907 /* 908 * the clear the hardware counters 909 */ 910 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 911 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 912 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 913 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 914 915 bix = sc->sc_rb.rb_tdtail; 916 917 for (;;) { 918 if (sc->sc_rb.rb_td_nbusy <= 0) 919 break; 920 921 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 922 923 if (txflags & QEC_XD_OWN) 924 break; 925 926 ifp->if_flags &= ~IFF_OACTIVE; 927 ifp->if_opackets++; 928 929 if (++bix == QEC_XD_RING_MAXSIZE) 930 bix = 0; 931 932 --sc->sc_rb.rb_td_nbusy; 933 } 934 935 sc->sc_rb.rb_tdtail = bix; 936 937 bestart(ifp); 938 939 if (sc->sc_rb.rb_td_nbusy == 0) 940 ifp->if_timer = 0; 941 942 return (1); 943 } 944 945 /* 946 * Receive interrupt. 947 */ 948 int 949 berint(sc) 950 struct be_softc *sc; 951 { 952 struct qec_xd *xd = sc->sc_rb.rb_rxd; 953 unsigned int bix, len; 954 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 955 956 bix = sc->sc_rb.rb_rdtail; 957 958 /* 959 * Process all buffers with valid data. 960 */ 961 for (;;) { 962 len = xd[bix].xd_flags; 963 if (len & QEC_XD_OWN) 964 break; 965 966 len &= QEC_XD_LENGTH; 967 be_read(sc, bix, len); 968 969 /* ... */ 970 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 971 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 972 973 if (++bix == QEC_XD_RING_MAXSIZE) 974 bix = 0; 975 } 976 977 sc->sc_rb.rb_rdtail = bix; 978 979 return (1); 980 } 981 982 int 983 beioctl(ifp, cmd, data) 984 struct ifnet *ifp; 985 u_long cmd; 986 void *data; 987 { 988 struct be_softc *sc = ifp->if_softc; 989 struct ifaddr *ifa = (struct ifaddr *)data; 990 struct ifreq *ifr = (struct ifreq *)data; 991 int s, error = 0; 992 993 s = splnet(); 994 995 switch (cmd) { 996 case SIOCSIFADDR: 997 ifp->if_flags |= IFF_UP; 998 switch (ifa->ifa_addr->sa_family) { 999 #ifdef INET 1000 case AF_INET: 1001 beinit(sc); 1002 arp_ifinit(ifp, ifa); 1003 break; 1004 #endif /* INET */ 1005 default: 1006 beinit(sc); 1007 break; 1008 } 1009 break; 1010 1011 case SIOCSIFFLAGS: 1012 if ((ifp->if_flags & IFF_UP) == 0 && 1013 (ifp->if_flags & IFF_RUNNING) != 0) { 1014 /* 1015 * If interface is marked down and it is running, then 1016 * stop it. 1017 */ 1018 bestop(sc); 1019 ifp->if_flags &= ~IFF_RUNNING; 1020 } else if ((ifp->if_flags & IFF_UP) != 0 && 1021 (ifp->if_flags & IFF_RUNNING) == 0) { 1022 /* 1023 * If interface is marked up and it is stopped, then 1024 * start it. 1025 */ 1026 beinit(sc); 1027 } else { 1028 /* 1029 * Reset the interface to pick up changes in any other 1030 * flags that affect hardware registers. 1031 */ 1032 bestop(sc); 1033 beinit(sc); 1034 } 1035 #ifdef BEDEBUG 1036 if (ifp->if_flags & IFF_DEBUG) 1037 sc->sc_debug = 1; 1038 else 1039 sc->sc_debug = 0; 1040 #endif 1041 break; 1042 1043 case SIOCADDMULTI: 1044 case SIOCDELMULTI: 1045 error = (cmd == SIOCADDMULTI) ? 1046 ether_addmulti(ifr, &sc->sc_ethercom): 1047 ether_delmulti(ifr, &sc->sc_ethercom); 1048 1049 if (error == ENETRESET) { 1050 /* 1051 * Multicast list has changed; set the hardware filter 1052 * accordingly. 1053 */ 1054 if (ifp->if_flags & IFF_RUNNING) 1055 be_mcreset(sc); 1056 error = 0; 1057 } 1058 break; 1059 case SIOCGIFMEDIA: 1060 case SIOCSIFMEDIA: 1061 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1062 break; 1063 default: 1064 error = EINVAL; 1065 break; 1066 } 1067 splx(s); 1068 return (error); 1069 } 1070 1071 1072 void 1073 beinit(sc) 1074 struct be_softc *sc; 1075 { 1076 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1077 bus_space_tag_t t = sc->sc_bustag; 1078 bus_space_handle_t br = sc->sc_br; 1079 bus_space_handle_t cr = sc->sc_cr; 1080 struct qec_softc *qec = sc->sc_qec; 1081 u_int32_t v; 1082 u_int32_t qecaddr; 1083 u_int8_t *ea; 1084 int s; 1085 1086 s = splnet(); 1087 1088 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1089 1090 bestop(sc); 1091 1092 ea = sc->sc_enaddr; 1093 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1094 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1095 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1096 1097 /* Clear hash table */ 1098 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1099 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1100 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1101 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1102 1103 /* Re-initialize RX configuration */ 1104 v = BE_BR_RXCFG_FIFO; 1105 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1106 1107 be_mcreset(sc); 1108 1109 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1110 1111 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1112 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1113 1114 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1115 1116 /* 1117 * Turn off counter expiration interrupts as well as 1118 * 'gotframe' and 'sentframe' 1119 */ 1120 bus_space_write_4(t, br, BE_BRI_IMASK, 1121 BE_BR_IMASK_GOTFRAME | 1122 BE_BR_IMASK_RCNTEXP | 1123 BE_BR_IMASK_ACNTEXP | 1124 BE_BR_IMASK_CCNTEXP | 1125 BE_BR_IMASK_LCNTEXP | 1126 BE_BR_IMASK_CVCNTEXP | 1127 BE_BR_IMASK_SENTFRAME | 1128 BE_BR_IMASK_NCNTEXP | 1129 BE_BR_IMASK_ECNTEXP | 1130 BE_BR_IMASK_LCCNTEXP | 1131 BE_BR_IMASK_FCNTEXP | 1132 BE_BR_IMASK_DTIMEXP); 1133 1134 /* Channel registers: */ 1135 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1136 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1137 1138 qecaddr = sc->sc_channel * qec->sc_msize; 1139 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1140 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1141 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1142 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1143 1144 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1145 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1146 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1147 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1148 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1149 1150 /* Set max packet length */ 1151 v = ETHER_MAX_LEN; 1152 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1153 v += ETHER_VLAN_ENCAP_LEN; 1154 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1155 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1156 1157 /* Enable transmitter */ 1158 bus_space_write_4(t, br, BE_BRI_TXCFG, 1159 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1160 1161 /* Enable receiver */ 1162 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1163 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1164 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1165 1166 ifp->if_flags |= IFF_RUNNING; 1167 ifp->if_flags &= ~IFF_OACTIVE; 1168 1169 be_ifmedia_upd(ifp); 1170 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1171 splx(s); 1172 } 1173 1174 void 1175 be_mcreset(sc) 1176 struct be_softc *sc; 1177 { 1178 struct ethercom *ec = &sc->sc_ethercom; 1179 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1180 bus_space_tag_t t = sc->sc_bustag; 1181 bus_space_handle_t br = sc->sc_br; 1182 u_int32_t crc; 1183 u_int16_t hash[4]; 1184 u_int8_t octet; 1185 u_int32_t v; 1186 int i, j; 1187 struct ether_multi *enm; 1188 struct ether_multistep step; 1189 1190 if (ifp->if_flags & IFF_PROMISC) { 1191 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1192 v |= BE_BR_RXCFG_PMISC; 1193 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1194 return; 1195 } 1196 1197 if (ifp->if_flags & IFF_ALLMULTI) { 1198 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1199 goto chipit; 1200 } 1201 1202 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1203 1204 ETHER_FIRST_MULTI(step, ec, enm); 1205 while (enm != NULL) { 1206 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1207 /* 1208 * We must listen to a range of multicast 1209 * addresses. For now, just accept all 1210 * multicasts, rather than trying to set only 1211 * those filter bits needed to match the range. 1212 * (At this time, the only use of address 1213 * ranges is for IP multicast routing, for 1214 * which the range is big enough to require 1215 * all bits set.) 1216 */ 1217 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1218 ifp->if_flags |= IFF_ALLMULTI; 1219 goto chipit; 1220 } 1221 1222 crc = 0xffffffff; 1223 1224 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1225 octet = enm->enm_addrlo[i]; 1226 1227 for (j = 0; j < 8; j++) { 1228 if ((crc & 1) ^ (octet & 1)) { 1229 crc >>= 1; 1230 crc ^= MC_POLY_LE; 1231 } 1232 else 1233 crc >>= 1; 1234 octet >>= 1; 1235 } 1236 } 1237 1238 crc >>= 26; 1239 hash[crc >> 4] |= 1 << (crc & 0xf); 1240 ETHER_NEXT_MULTI(step, enm); 1241 } 1242 1243 ifp->if_flags &= ~IFF_ALLMULTI; 1244 1245 chipit: 1246 /* Enable the hash filter */ 1247 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1248 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1249 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1250 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1251 1252 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1253 v &= ~BE_BR_RXCFG_PMISC; 1254 v |= BE_BR_RXCFG_HENABLE; 1255 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1256 } 1257 1258 /* 1259 * Set the tcvr to an idle state 1260 */ 1261 void 1262 be_mii_sync(sc) 1263 struct be_softc *sc; 1264 { 1265 bus_space_tag_t t = sc->sc_bustag; 1266 bus_space_handle_t tr = sc->sc_tr; 1267 int n = 32; 1268 1269 while (n--) { 1270 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1271 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1272 MGMT_PAL_OENAB); 1273 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1274 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1275 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1276 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1277 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1278 } 1279 } 1280 1281 void 1282 be_pal_gate(sc, phy) 1283 struct be_softc *sc; 1284 int phy; 1285 { 1286 bus_space_tag_t t = sc->sc_bustag; 1287 bus_space_handle_t tr = sc->sc_tr; 1288 u_int32_t v; 1289 1290 be_mii_sync(sc); 1291 1292 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1293 if (phy == BE_PHY_INTERNAL) 1294 v &= ~TCVR_PAL_SERIAL; 1295 1296 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1297 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1298 } 1299 1300 static int 1301 be_tcvr_read_bit(sc, phy) 1302 struct be_softc *sc; 1303 int phy; 1304 { 1305 bus_space_tag_t t = sc->sc_bustag; 1306 bus_space_handle_t tr = sc->sc_tr; 1307 int ret; 1308 1309 if (phy == BE_PHY_INTERNAL) { 1310 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1311 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1312 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1313 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1314 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1315 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1316 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1317 } else { 1318 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1319 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1320 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1321 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1322 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1323 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1324 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1325 } 1326 1327 return (ret); 1328 } 1329 1330 static void 1331 be_tcvr_write_bit(sc, phy, bit) 1332 struct be_softc *sc; 1333 int phy; 1334 int bit; 1335 { 1336 bus_space_tag_t t = sc->sc_bustag; 1337 bus_space_handle_t tr = sc->sc_tr; 1338 u_int32_t v; 1339 1340 if (phy == BE_PHY_INTERNAL) { 1341 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1342 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1343 } else { 1344 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1345 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1346 } 1347 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1348 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1349 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1350 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1351 } 1352 1353 static void 1354 be_mii_sendbits(sc, phy, data, nbits) 1355 struct be_softc *sc; 1356 int phy; 1357 u_int32_t data; 1358 int nbits; 1359 { 1360 int i; 1361 1362 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1363 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1364 } 1365 } 1366 1367 static int 1368 be_mii_readreg(self, phy, reg) 1369 struct device *self; 1370 int phy, reg; 1371 { 1372 struct be_softc *sc = (struct be_softc *)self; 1373 int val = 0, i; 1374 1375 /* 1376 * Read the PHY register by manually driving the MII control lines. 1377 */ 1378 be_mii_sync(sc); 1379 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1380 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1381 be_mii_sendbits(sc, phy, phy, 5); 1382 be_mii_sendbits(sc, phy, reg, 5); 1383 1384 (void) be_tcvr_read_bit(sc, phy); 1385 (void) be_tcvr_read_bit(sc, phy); 1386 1387 for (i = 15; i >= 0; i--) 1388 val |= (be_tcvr_read_bit(sc, phy) << i); 1389 1390 (void) be_tcvr_read_bit(sc, phy); 1391 (void) be_tcvr_read_bit(sc, phy); 1392 (void) be_tcvr_read_bit(sc, phy); 1393 1394 return (val); 1395 } 1396 1397 void 1398 be_mii_writereg(self, phy, reg, val) 1399 struct device *self; 1400 int phy, reg, val; 1401 { 1402 struct be_softc *sc = (struct be_softc *)self; 1403 int i; 1404 1405 /* 1406 * Write the PHY register by manually driving the MII control lines. 1407 */ 1408 be_mii_sync(sc); 1409 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1410 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1411 be_mii_sendbits(sc, phy, phy, 5); 1412 be_mii_sendbits(sc, phy, reg, 5); 1413 1414 be_tcvr_write_bit(sc, phy, 1); 1415 be_tcvr_write_bit(sc, phy, 0); 1416 1417 for (i = 15; i >= 0; i--) 1418 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1419 } 1420 1421 int 1422 be_mii_reset(sc, phy) 1423 struct be_softc *sc; 1424 int phy; 1425 { 1426 int n; 1427 1428 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1429 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1430 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1431 1432 for (n = 16; n >= 0; n--) { 1433 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1434 if ((bmcr & BMCR_RESET) == 0) 1435 break; 1436 DELAY(20); 1437 } 1438 if (n == 0) { 1439 printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname); 1440 return (EIO); 1441 } 1442 1443 return (0); 1444 } 1445 1446 void 1447 be_tick(arg) 1448 void *arg; 1449 { 1450 struct be_softc *sc = arg; 1451 int s = splnet(); 1452 1453 mii_tick(&sc->sc_mii); 1454 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1455 1456 splx(s); 1457 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1458 } 1459 1460 void 1461 be_mii_statchg(self) 1462 struct device *self; 1463 { 1464 struct be_softc *sc = (struct be_softc *)self; 1465 bus_space_tag_t t = sc->sc_bustag; 1466 bus_space_handle_t br = sc->sc_br; 1467 u_int instance; 1468 u_int32_t v; 1469 1470 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1471 #ifdef DIAGNOSTIC 1472 if (instance > 1) 1473 panic("be_mii_statchg: instance %d out of range", instance); 1474 #endif 1475 1476 /* Update duplex mode in TX configuration */ 1477 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1478 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1479 v |= BE_BR_TXCFG_FULLDPLX; 1480 else 1481 v &= ~BE_BR_TXCFG_FULLDPLX; 1482 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1483 1484 /* Change to appropriate gate in transceiver PAL */ 1485 be_pal_gate(sc, sc->sc_phys[instance]); 1486 } 1487 1488 /* 1489 * Get current media settings. 1490 */ 1491 void 1492 be_ifmedia_sts(ifp, ifmr) 1493 struct ifnet *ifp; 1494 struct ifmediareq *ifmr; 1495 { 1496 struct be_softc *sc = ifp->if_softc; 1497 1498 mii_pollstat(&sc->sc_mii); 1499 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1500 1501 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1502 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1503 return; 1504 } 1505 1506 /* 1507 * Set media options. 1508 */ 1509 int 1510 be_ifmedia_upd(ifp) 1511 struct ifnet *ifp; 1512 { 1513 struct be_softc *sc = ifp->if_softc; 1514 int error; 1515 1516 if ((error = mii_mediachg(&sc->sc_mii)) != 0) 1517 return (error); 1518 1519 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1520 } 1521 1522 /* 1523 * Service routine for our pseudo-MII internal transceiver. 1524 */ 1525 int 1526 be_intphy_service(sc, mii, cmd) 1527 struct be_softc *sc; 1528 struct mii_data *mii; 1529 int cmd; 1530 { 1531 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1532 int bmcr, bmsr; 1533 int error; 1534 1535 switch (cmd) { 1536 case MII_POLLSTAT: 1537 /* 1538 * If we're not polling our PHY instance, just return. 1539 */ 1540 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1541 return (0); 1542 1543 break; 1544 1545 case MII_MEDIACHG: 1546 1547 /* 1548 * If the media indicates a different PHY instance, 1549 * isolate ourselves. 1550 */ 1551 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1552 bmcr = be_mii_readreg((void *)sc, 1553 BE_PHY_INTERNAL, MII_BMCR); 1554 be_mii_writereg((void *)sc, 1555 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1556 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1557 sc->sc_intphy_curspeed = 0; 1558 return (0); 1559 } 1560 1561 1562 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1563 return (error); 1564 1565 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1566 1567 /* 1568 * Select the new mode and take out of isolation 1569 */ 1570 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1571 bmcr |= BMCR_S100; 1572 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1573 bmcr &= ~BMCR_S100; 1574 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1575 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1576 bmcr &= ~BMCR_S100; 1577 bmcr |= sc->sc_intphy_curspeed; 1578 } else { 1579 /* Keep isolated until link is up */ 1580 bmcr |= BMCR_ISO; 1581 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1582 } 1583 } 1584 1585 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1586 bmcr |= BMCR_FDX; 1587 else 1588 bmcr &= ~BMCR_FDX; 1589 1590 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1591 break; 1592 1593 case MII_TICK: 1594 /* 1595 * If we're not currently selected, just return. 1596 */ 1597 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1598 return (0); 1599 1600 /* Only used for automatic media selection */ 1601 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1602 return (0); 1603 1604 /* Is the interface even up? */ 1605 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1606 return (0); 1607 1608 /* 1609 * Check link status; if we don't have a link, try another 1610 * speed. We can't detect duplex mode, so half-duplex is 1611 * what we have to settle for. 1612 */ 1613 1614 /* Read twice in case the register is latched */ 1615 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1616 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1617 1618 if ((bmsr & BMSR_LINK) != 0) { 1619 /* We have a carrier */ 1620 bmcr = be_mii_readreg((void *)sc, 1621 BE_PHY_INTERNAL, MII_BMCR); 1622 1623 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1624 bmcr = be_mii_readreg((void *)sc, 1625 BE_PHY_INTERNAL, MII_BMCR); 1626 1627 sc->sc_mii_flags |= MIIF_HAVELINK; 1628 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1629 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1630 1631 bmcr &= ~BMCR_ISO; 1632 be_mii_writereg((void *)sc, 1633 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1634 1635 printf("%s: link up at %s Mbps\n", 1636 sc->sc_dev.dv_xname, 1637 (bmcr & BMCR_S100) ? "100" : "10"); 1638 } 1639 return (0); 1640 } 1641 1642 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1643 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1644 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1645 sc->sc_intphy_curspeed = 0; 1646 printf("%s: link down\n", sc->sc_dev.dv_xname); 1647 } 1648 1649 /* Only retry autonegotiation every 5 seconds. */ 1650 if (++sc->sc_mii_ticks < 5) 1651 return(0); 1652 1653 sc->sc_mii_ticks = 0; 1654 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1655 /* Just flip the fast speed bit */ 1656 bmcr ^= BMCR_S100; 1657 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1658 1659 break; 1660 1661 case MII_DOWN: 1662 /* Isolate this phy */ 1663 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1664 be_mii_writereg((void *)sc, 1665 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1666 return (0); 1667 } 1668 1669 /* Update the media status. */ 1670 be_intphy_status(sc); 1671 1672 /* Callback if something changed. */ 1673 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1674 (*mii->mii_statchg)((struct device *)sc); 1675 sc->sc_mii_active = mii->mii_media_active; 1676 } 1677 return (0); 1678 } 1679 1680 /* 1681 * Determine status of internal transceiver 1682 */ 1683 void 1684 be_intphy_status(sc) 1685 struct be_softc *sc; 1686 { 1687 struct mii_data *mii = &sc->sc_mii; 1688 int media_active, media_status; 1689 int bmcr, bmsr; 1690 1691 media_status = IFM_AVALID; 1692 media_active = 0; 1693 1694 /* 1695 * Internal transceiver; do the work here. 1696 */ 1697 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1698 1699 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1700 case (BMCR_S100 | BMCR_FDX): 1701 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1702 break; 1703 case BMCR_S100: 1704 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1705 break; 1706 case BMCR_FDX: 1707 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1708 break; 1709 case 0: 1710 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1711 break; 1712 } 1713 1714 /* Read twice in case the register is latched */ 1715 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1716 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1717 if (bmsr & BMSR_LINK) 1718 media_status |= IFM_ACTIVE; 1719 1720 mii->mii_media_status = media_status; 1721 mii->mii_media_active = media_active; 1722 } 1723
Indexes created Tue Sep 30 11:09:46 GMT 2025