be.c revision 1.57
1 /* $NetBSD: be.c,v 1.57 2008/04/05 18:35:31 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. The name of the authors may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.57 2008/04/05 18:35:31 cegger Exp $"); 68 69 #include "opt_ddb.h" 70 #include "opt_inet.h" 71 #include "bpfilter.h" 72 #include "rnd.h" 73 74 #include <sys/param.h> 75 #include <sys/systm.h> 76 #include <sys/callout.h> 77 #include <sys/kernel.h> 78 #include <sys/errno.h> 79 #include <sys/ioctl.h> 80 #include <sys/mbuf.h> 81 #include <sys/socket.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #if NRND > 0 86 #include <sys/rnd.h> 87 #endif 88 89 #include <net/if.h> 90 #include <net/if_dl.h> 91 #include <net/if_types.h> 92 #include <net/netisr.h> 93 #include <net/if_media.h> 94 #include <net/if_ether.h> 95 96 #ifdef INET 97 #include <netinet/in.h> 98 #include <netinet/if_inarp.h> 99 #include <netinet/in_systm.h> 100 #include <netinet/in_var.h> 101 #include <netinet/ip.h> 102 #endif 103 104 105 #if NBPFILTER > 0 106 #include <net/bpf.h> 107 #include <net/bpfdesc.h> 108 #endif 109 110 #include <sys/bus.h> 111 #include <sys/intr.h> 112 #include <machine/autoconf.h> 113 114 #include <dev/sbus/sbusvar.h> 115 116 #include <dev/mii/mii.h> 117 #include <dev/mii/miivar.h> 118 119 #include <dev/sbus/qecreg.h> 120 #include <dev/sbus/qecvar.h> 121 #include <dev/sbus/bereg.h> 122 123 struct be_softc { 124 struct device sc_dev; 125 struct sbusdev sc_sd; /* sbus device */ 126 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 127 bus_dma_tag_t sc_dmatag; 128 bus_dmamap_t sc_dmamap; 129 struct ethercom sc_ethercom; 130 /*struct ifmedia sc_ifmedia; -* interface media */ 131 struct mii_data sc_mii; /* MII media control */ 132 #define sc_media sc_mii.mii_media/* shorthand */ 133 int sc_phys[2]; /* MII instance -> phy */ 134 135 struct callout sc_tick_ch; 136 137 /* 138 * Some `mii_softc' items we need to emulate MII operation 139 * for our internal transceiver. 140 */ 141 int sc_mii_inst; /* instance of internal phy */ 142 int sc_mii_active; /* currently active medium */ 143 int sc_mii_ticks; /* tick counter */ 144 int sc_mii_flags; /* phy status flags */ 145 #define MIIF_HAVELINK 0x04000000 146 int sc_intphy_curspeed; /* Established link speed */ 147 148 struct qec_softc *sc_qec; /* QEC parent */ 149 150 bus_space_handle_t sc_qr; /* QEC registers */ 151 bus_space_handle_t sc_br; /* BE registers */ 152 bus_space_handle_t sc_cr; /* channel registers */ 153 bus_space_handle_t sc_tr; /* transceiver registers */ 154 155 u_int sc_rev; 156 157 int sc_channel; /* channel number */ 158 int sc_burst; 159 160 struct qec_ring sc_rb; /* Packet Ring Buffer */ 161 162 /* MAC address */ 163 u_int8_t sc_enaddr[6]; 164 #ifdef BEDEBUG 165 int sc_debug; 166 #endif 167 }; 168 169 int bematch(struct device *, struct cfdata *, void *); 170 void beattach(struct device *, struct device *, void *); 171 172 void beinit(struct be_softc *); 173 void bestart(struct ifnet *); 174 void bestop(struct be_softc *); 175 void bewatchdog(struct ifnet *); 176 int beioctl(struct ifnet *, u_long, void *); 177 void bereset(struct be_softc *); 178 179 int beintr(void *); 180 int berint(struct be_softc *); 181 int betint(struct be_softc *); 182 int beqint(struct be_softc *, u_int32_t); 183 int beeint(struct be_softc *, u_int32_t); 184 185 static void be_read(struct be_softc *, int, int); 186 static int be_put(struct be_softc *, int, struct mbuf *); 187 static struct mbuf *be_get(struct be_softc *, int, int); 188 189 void be_pal_gate(struct be_softc *, int); 190 191 /* ifmedia callbacks */ 192 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 193 int be_ifmedia_upd(struct ifnet *); 194 195 void be_mcreset(struct be_softc *); 196 197 /* MII methods & callbacks */ 198 static int be_mii_readreg(struct device *, int, int); 199 static void be_mii_writereg(struct device *, int, int, int); 200 static void be_mii_statchg(struct device *); 201 202 /* MII helpers */ 203 static void be_mii_sync(struct be_softc *); 204 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 205 static int be_mii_reset(struct be_softc *, int); 206 static int be_tcvr_read_bit(struct be_softc *, int); 207 static void be_tcvr_write_bit(struct be_softc *, int, int); 208 209 void be_tick(void *); 210 void be_intphy_auto(struct be_softc *); 211 void be_intphy_status(struct be_softc *); 212 int be_intphy_service(struct be_softc *, struct mii_data *, int); 213 214 215 CFATTACH_DECL(be, sizeof(struct be_softc), 216 bematch, beattach, NULL, NULL); 217 218 int 219 bematch(parent, cf, aux) 220 struct device *parent; 221 struct cfdata *cf; 222 void *aux; 223 { 224 struct sbus_attach_args *sa = aux; 225 226 return (strcmp(cf->cf_name, sa->sa_name) == 0); 227 } 228 229 void 230 beattach(parent, self, aux) 231 struct device *parent, *self; 232 void *aux; 233 { 234 struct sbus_attach_args *sa = aux; 235 struct qec_softc *qec = (struct qec_softc *)parent; 236 struct be_softc *sc = (struct be_softc *)self; 237 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 238 struct mii_data *mii = &sc->sc_mii; 239 struct mii_softc *child; 240 int node = sa->sa_node; 241 bus_dma_tag_t dmatag = sa->sa_dmatag; 242 bus_dma_segment_t seg; 243 bus_size_t size; 244 int instance; 245 int rseg, error; 246 u_int32_t v; 247 248 if (sa->sa_nreg < 3) { 249 printf("%s: only %d register sets\n", 250 device_xname(self), sa->sa_nreg); 251 return; 252 } 253 254 if (bus_space_map(sa->sa_bustag, 255 (bus_addr_t)BUS_ADDR( 256 sa->sa_reg[0].oa_space, 257 sa->sa_reg[0].oa_base), 258 (bus_size_t)sa->sa_reg[0].oa_size, 259 0, &sc->sc_cr) != 0) { 260 printf("beattach: cannot map registers\n"); 261 return; 262 } 263 264 if (bus_space_map(sa->sa_bustag, 265 (bus_addr_t)BUS_ADDR( 266 sa->sa_reg[1].oa_space, 267 sa->sa_reg[1].oa_base), 268 (bus_size_t)sa->sa_reg[1].oa_size, 269 0, &sc->sc_br) != 0) { 270 printf("beattach: cannot map registers\n"); 271 return; 272 } 273 274 if (bus_space_map(sa->sa_bustag, 275 (bus_addr_t)BUS_ADDR( 276 sa->sa_reg[2].oa_space, 277 sa->sa_reg[2].oa_base), 278 (bus_size_t)sa->sa_reg[2].oa_size, 279 0, &sc->sc_tr) != 0) { 280 printf("beattach: cannot map registers\n"); 281 return; 282 } 283 284 sc->sc_bustag = sa->sa_bustag; 285 sc->sc_qec = qec; 286 sc->sc_qr = qec->sc_regs; 287 288 sc->sc_rev = prom_getpropint(node, "board-version", -1); 289 printf(" rev %x", sc->sc_rev); 290 291 bestop(sc); 292 293 sc->sc_channel = prom_getpropint(node, "channel#", -1); 294 if (sc->sc_channel == -1) 295 sc->sc_channel = 0; 296 297 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 298 if (sc->sc_burst == -1) 299 sc->sc_burst = qec->sc_burst; 300 301 /* Clamp at parent's burst sizes */ 302 sc->sc_burst &= qec->sc_burst; 303 304 /* Establish interrupt handler */ 305 if (sa->sa_nintr) 306 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 307 beintr, sc); 308 309 prom_getether(node, sc->sc_enaddr); 310 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 311 312 /* 313 * Allocate descriptor ring and buffers. 314 */ 315 316 /* for now, allocate as many bufs as there are ring descriptors */ 317 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 318 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 319 320 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 321 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 322 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 323 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 324 325 /* Get a DMA handle */ 326 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 327 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 328 aprint_error_dev(self, "DMA map create error %d\n", error); 329 return; 330 } 331 332 /* Allocate DMA buffer */ 333 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 334 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 335 aprint_error_dev(self, "DMA buffer alloc error %d\n", 336 error); 337 return; 338 } 339 340 /* Map DMA memory in CPU addressable space */ 341 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 342 &sc->sc_rb.rb_membase, 343 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 344 aprint_error_dev(self, "DMA buffer map error %d\n", 345 error); 346 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 347 return; 348 } 349 350 /* Load the buffer */ 351 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 352 sc->sc_rb.rb_membase, size, NULL, 353 BUS_DMA_NOWAIT)) != 0) { 354 aprint_error_dev(self, "DMA buffer map load error %d\n", 355 error); 356 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 357 bus_dmamem_free(dmatag, &seg, rseg); 358 return; 359 } 360 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 361 362 /* 363 * Initialize our media structures and MII info. 364 */ 365 mii->mii_ifp = ifp; 366 mii->mii_readreg = be_mii_readreg; 367 mii->mii_writereg = be_mii_writereg; 368 mii->mii_statchg = be_mii_statchg; 369 370 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 371 372 callout_init(&sc->sc_tick_ch, 0); 373 374 /* 375 * Initialize transceiver and determine which PHY connection to use. 376 */ 377 be_mii_sync(sc); 378 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 379 380 instance = 0; 381 382 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 383 384 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 385 MII_OFFSET_ANY, 0); 386 387 child = LIST_FIRST(&mii->mii_phys); 388 if (child == NULL) { 389 /* No PHY attached */ 390 ifmedia_add(&sc->sc_media, 391 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 392 0, NULL); 393 ifmedia_set(&sc->sc_media, 394 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 395 } else { 396 /* 397 * Note: we support just one PHY on the external 398 * MII connector. 399 */ 400 #ifdef DIAGNOSTIC 401 if (LIST_NEXT(child, mii_list) != NULL) { 402 aprint_error_dev(&sc->sc_dev, "spurious MII device %s attached\n", 403 device_xname(&child->mii_dev)); 404 } 405 #endif 406 if (child->mii_phy != BE_PHY_EXTERNAL || 407 child->mii_inst > 0) { 408 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s" 409 " at phy %d, instance %d\n", 410 device_xname(&child->mii_dev), 411 child->mii_phy, child->mii_inst); 412 } else { 413 sc->sc_phys[instance] = child->mii_phy; 414 } 415 416 /* 417 * XXX - we can really do the following ONLY if the 418 * phy indeed has the auto negotiation capability!! 419 */ 420 ifmedia_set(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 422 423 /* Mark our current media setting */ 424 be_pal_gate(sc, BE_PHY_EXTERNAL); 425 instance++; 426 } 427 428 } 429 430 if ((v & MGMT_PAL_INT_MDIO) != 0) { 431 /* 432 * The be internal phy looks vaguely like MII hardware, 433 * but not enough to be able to use the MII device 434 * layer. Hence, we have to take care of media selection 435 * ourselves. 436 */ 437 438 sc->sc_mii_inst = instance; 439 sc->sc_phys[instance] = BE_PHY_INTERNAL; 440 441 /* Use `ifm_data' to store BMCR bits */ 442 ifmedia_add(&sc->sc_media, 443 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 444 0, NULL); 445 ifmedia_add(&sc->sc_media, 446 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 447 BMCR_S100, NULL); 448 ifmedia_add(&sc->sc_media, 449 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 450 0, NULL); 451 452 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 453 device_xname(self)); 454 455 be_mii_reset(sc, BE_PHY_INTERNAL); 456 /* Only set default medium here if there's no external PHY */ 457 if (instance == 0) { 458 be_pal_gate(sc, BE_PHY_INTERNAL); 459 ifmedia_set(&sc->sc_media, 460 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 461 } else 462 be_mii_writereg((void *)sc, 463 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 464 } 465 466 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 467 ifp->if_softc = sc; 468 ifp->if_start = bestart; 469 ifp->if_ioctl = beioctl; 470 ifp->if_watchdog = bewatchdog; 471 ifp->if_flags = 472 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 473 IFQ_SET_READY(&ifp->if_snd); 474 475 /* claim 802.1q capability */ 476 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 477 478 /* Attach the interface. */ 479 if_attach(ifp); 480 ether_ifattach(ifp, sc->sc_enaddr); 481 } 482 483 484 /* 485 * Routine to copy from mbuf chain to transmit buffer in 486 * network buffer memory. 487 */ 488 static inline int 489 be_put(sc, idx, m) 490 struct be_softc *sc; 491 int idx; 492 struct mbuf *m; 493 { 494 struct mbuf *n; 495 int len, tlen = 0, boff = 0; 496 void *bp; 497 498 bp = (char *)sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 499 500 for (; m; m = n) { 501 len = m->m_len; 502 if (len == 0) { 503 MFREE(m, n); 504 continue; 505 } 506 memcpy((char *)bp + boff, mtod(m, void *), len); 507 boff += len; 508 tlen += len; 509 MFREE(m, n); 510 } 511 return (tlen); 512 } 513 514 /* 515 * Pull data off an interface. 516 * Len is the length of data, with local net header stripped. 517 * We copy the data into mbufs. When full cluster sized units are present, 518 * we copy into clusters. 519 */ 520 static inline struct mbuf * 521 be_get(sc, idx, totlen) 522 struct be_softc *sc; 523 int idx, totlen; 524 { 525 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 526 struct mbuf *m; 527 struct mbuf *top, **mp; 528 int len, pad, boff = 0; 529 void *bp; 530 531 bp = (char *)sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 532 533 MGETHDR(m, M_DONTWAIT, MT_DATA); 534 if (m == NULL) 535 return (NULL); 536 m->m_pkthdr.rcvif = ifp; 537 m->m_pkthdr.len = totlen; 538 539 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 540 m->m_data += pad; 541 len = MHLEN - pad; 542 top = NULL; 543 mp = ⊤ 544 545 while (totlen > 0) { 546 if (top) { 547 MGET(m, M_DONTWAIT, MT_DATA); 548 if (m == NULL) { 549 m_freem(top); 550 return (NULL); 551 } 552 len = MLEN; 553 } 554 if (top && totlen >= MINCLSIZE) { 555 MCLGET(m, M_DONTWAIT); 556 if (m->m_flags & M_EXT) 557 len = MCLBYTES; 558 } 559 m->m_len = len = min(totlen, len); 560 memcpy(mtod(m, void *), (char *)bp + boff, len); 561 boff += len; 562 totlen -= len; 563 *mp = m; 564 mp = &m->m_next; 565 } 566 567 return (top); 568 } 569 570 /* 571 * Pass a packet to the higher levels. 572 */ 573 static inline void 574 be_read(sc, idx, len) 575 struct be_softc *sc; 576 int idx, len; 577 { 578 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 579 struct mbuf *m; 580 581 if (len <= sizeof(struct ether_header) || 582 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 583 #ifdef BEDEBUG 584 if (sc->sc_debug) 585 printf("%s: invalid packet size %d; dropping\n", 586 ifp->if_xname, len); 587 #endif 588 ifp->if_ierrors++; 589 return; 590 } 591 592 /* 593 * Pull packet off interface. 594 */ 595 m = be_get(sc, idx, len); 596 if (m == NULL) { 597 ifp->if_ierrors++; 598 return; 599 } 600 ifp->if_ipackets++; 601 602 #if NBPFILTER > 0 603 /* 604 * Check if there's a BPF listener on this interface. 605 * If so, hand off the raw packet to BPF. 606 */ 607 if (ifp->if_bpf) 608 bpf_mtap(ifp->if_bpf, m); 609 #endif 610 /* Pass the packet up. */ 611 (*ifp->if_input)(ifp, m); 612 } 613 614 /* 615 * Start output on interface. 616 * We make two assumptions here: 617 * 1) that the current priority is set to splnet _before_ this code 618 * is called *and* is returned to the appropriate priority after 619 * return 620 * 2) that the IFF_OACTIVE flag is checked before this code is called 621 * (i.e. that the output part of the interface is idle) 622 */ 623 void 624 bestart(ifp) 625 struct ifnet *ifp; 626 { 627 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 628 struct qec_xd *txd = sc->sc_rb.rb_txd; 629 struct mbuf *m; 630 unsigned int bix, len; 631 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 632 633 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 634 return; 635 636 bix = sc->sc_rb.rb_tdhead; 637 638 for (;;) { 639 IFQ_DEQUEUE(&ifp->if_snd, m); 640 if (m == 0) 641 break; 642 643 #if NBPFILTER > 0 644 /* 645 * If BPF is listening on this interface, let it see the 646 * packet before we commit it to the wire. 647 */ 648 if (ifp->if_bpf) 649 bpf_mtap(ifp->if_bpf, m); 650 #endif 651 652 /* 653 * Copy the mbuf chain into the transmit buffer. 654 */ 655 len = be_put(sc, bix, m); 656 657 /* 658 * Initialize transmit registers and start transmission 659 */ 660 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 661 (len & QEC_XD_LENGTH); 662 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 663 BE_CR_CTRL_TWAKEUP); 664 665 if (++bix == QEC_XD_RING_MAXSIZE) 666 bix = 0; 667 668 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 669 ifp->if_flags |= IFF_OACTIVE; 670 break; 671 } 672 } 673 674 sc->sc_rb.rb_tdhead = bix; 675 } 676 677 void 678 bestop(sc) 679 struct be_softc *sc; 680 { 681 int n; 682 bus_space_tag_t t = sc->sc_bustag; 683 bus_space_handle_t br = sc->sc_br; 684 685 callout_stop(&sc->sc_tick_ch); 686 687 /* Down the MII. */ 688 mii_down(&sc->sc_mii); 689 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 690 691 /* Stop the transmitter */ 692 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 693 for (n = 32; n > 0; n--) { 694 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 695 break; 696 DELAY(20); 697 } 698 699 /* Stop the receiver */ 700 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 701 for (n = 32; n > 0; n--) { 702 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 703 break; 704 DELAY(20); 705 } 706 } 707 708 /* 709 * Reset interface. 710 */ 711 void 712 bereset(sc) 713 struct be_softc *sc; 714 { 715 int s; 716 717 s = splnet(); 718 bestop(sc); 719 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 720 beinit(sc); 721 splx(s); 722 } 723 724 void 725 bewatchdog(ifp) 726 struct ifnet *ifp; 727 { 728 struct be_softc *sc = ifp->if_softc; 729 730 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 731 ++sc->sc_ethercom.ec_if.if_oerrors; 732 733 bereset(sc); 734 } 735 736 int 737 beintr(v) 738 void *v; 739 { 740 struct be_softc *sc = (struct be_softc *)v; 741 bus_space_tag_t t = sc->sc_bustag; 742 u_int32_t whyq, whyb, whyc; 743 int r = 0; 744 745 /* Read QEC status, channel status and BE status */ 746 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 747 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 748 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 749 750 if (whyq & QEC_STAT_BM) 751 r |= beeint(sc, whyb); 752 753 if (whyq & QEC_STAT_ER) 754 r |= beqint(sc, whyc); 755 756 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 757 r |= betint(sc); 758 759 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 760 r |= berint(sc); 761 762 return (r); 763 } 764 765 /* 766 * QEC Interrupt. 767 */ 768 int 769 beqint(sc, why) 770 struct be_softc *sc; 771 u_int32_t why; 772 { 773 int r = 0, rst = 0; 774 775 if (why & BE_CR_STAT_TXIRQ) 776 r |= 1; 777 if (why & BE_CR_STAT_RXIRQ) 778 r |= 1; 779 780 if (why & BE_CR_STAT_BERROR) { 781 r |= 1; 782 rst = 1; 783 aprint_error_dev(&sc->sc_dev, "bigmac error\n"); 784 } 785 786 if (why & BE_CR_STAT_TXDERR) { 787 r |= 1; 788 rst = 1; 789 aprint_error_dev(&sc->sc_dev, "bogus tx descriptor\n"); 790 } 791 792 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 793 r |= 1; 794 rst = 1; 795 aprint_error_dev(&sc->sc_dev, "tx DMA error ( "); 796 if (why & BE_CR_STAT_TXLERR) 797 printf("Late "); 798 if (why & BE_CR_STAT_TXPERR) 799 printf("Parity "); 800 if (why & BE_CR_STAT_TXSERR) 801 printf("Generic "); 802 printf(")\n"); 803 } 804 805 if (why & BE_CR_STAT_RXDROP) { 806 r |= 1; 807 rst = 1; 808 aprint_error_dev(&sc->sc_dev, "out of rx descriptors\n"); 809 } 810 811 if (why & BE_CR_STAT_RXSMALL) { 812 r |= 1; 813 rst = 1; 814 aprint_error_dev(&sc->sc_dev, "rx descriptor too small\n"); 815 } 816 817 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 818 r |= 1; 819 rst = 1; 820 aprint_error_dev(&sc->sc_dev, "rx DMA error ( "); 821 if (why & BE_CR_STAT_RXLERR) 822 printf("Late "); 823 if (why & BE_CR_STAT_RXPERR) 824 printf("Parity "); 825 if (why & BE_CR_STAT_RXSERR) 826 printf("Generic "); 827 printf(")\n"); 828 } 829 830 if (!r) { 831 rst = 1; 832 aprint_error_dev(&sc->sc_dev, "unexpected error interrupt %08x\n", 833 why); 834 } 835 836 if (rst) { 837 printf("%s: resetting\n", device_xname(&sc->sc_dev)); 838 bereset(sc); 839 } 840 841 return (r); 842 } 843 844 /* 845 * Error interrupt. 846 */ 847 int 848 beeint(sc, why) 849 struct be_softc *sc; 850 u_int32_t why; 851 { 852 int r = 0, rst = 0; 853 854 if (why & BE_BR_STAT_RFIFOVF) { 855 r |= 1; 856 rst = 1; 857 aprint_error_dev(&sc->sc_dev, "receive fifo overrun\n"); 858 } 859 if (why & BE_BR_STAT_TFIFO_UND) { 860 r |= 1; 861 rst = 1; 862 aprint_error_dev(&sc->sc_dev, "transmit fifo underrun\n"); 863 } 864 if (why & BE_BR_STAT_MAXPKTERR) { 865 r |= 1; 866 rst = 1; 867 aprint_error_dev(&sc->sc_dev, "max packet size error\n"); 868 } 869 870 if (!r) { 871 rst = 1; 872 aprint_error_dev(&sc->sc_dev, "unexpected error interrupt %08x\n", 873 why); 874 } 875 876 if (rst) { 877 printf("%s: resetting\n", device_xname(&sc->sc_dev)); 878 bereset(sc); 879 } 880 881 return (r); 882 } 883 884 /* 885 * Transmit interrupt. 886 */ 887 int 888 betint(sc) 889 struct be_softc *sc; 890 { 891 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 892 bus_space_tag_t t = sc->sc_bustag; 893 bus_space_handle_t br = sc->sc_br; 894 unsigned int bix, txflags; 895 896 /* 897 * Unload collision counters 898 */ 899 ifp->if_collisions += 900 bus_space_read_4(t, br, BE_BRI_NCCNT) + 901 bus_space_read_4(t, br, BE_BRI_FCCNT) + 902 bus_space_read_4(t, br, BE_BRI_EXCNT) + 903 bus_space_read_4(t, br, BE_BRI_LTCNT); 904 905 /* 906 * the clear the hardware counters 907 */ 908 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 909 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 910 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 911 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 912 913 bix = sc->sc_rb.rb_tdtail; 914 915 for (;;) { 916 if (sc->sc_rb.rb_td_nbusy <= 0) 917 break; 918 919 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 920 921 if (txflags & QEC_XD_OWN) 922 break; 923 924 ifp->if_flags &= ~IFF_OACTIVE; 925 ifp->if_opackets++; 926 927 if (++bix == QEC_XD_RING_MAXSIZE) 928 bix = 0; 929 930 --sc->sc_rb.rb_td_nbusy; 931 } 932 933 sc->sc_rb.rb_tdtail = bix; 934 935 bestart(ifp); 936 937 if (sc->sc_rb.rb_td_nbusy == 0) 938 ifp->if_timer = 0; 939 940 return (1); 941 } 942 943 /* 944 * Receive interrupt. 945 */ 946 int 947 berint(sc) 948 struct be_softc *sc; 949 { 950 struct qec_xd *xd = sc->sc_rb.rb_rxd; 951 unsigned int bix, len; 952 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 953 954 bix = sc->sc_rb.rb_rdtail; 955 956 /* 957 * Process all buffers with valid data. 958 */ 959 for (;;) { 960 len = xd[bix].xd_flags; 961 if (len & QEC_XD_OWN) 962 break; 963 964 len &= QEC_XD_LENGTH; 965 be_read(sc, bix, len); 966 967 /* ... */ 968 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 969 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 970 971 if (++bix == QEC_XD_RING_MAXSIZE) 972 bix = 0; 973 } 974 975 sc->sc_rb.rb_rdtail = bix; 976 977 return (1); 978 } 979 980 int 981 beioctl(ifp, cmd, data) 982 struct ifnet *ifp; 983 u_long cmd; 984 void *data; 985 { 986 struct be_softc *sc = ifp->if_softc; 987 struct ifaddr *ifa = (struct ifaddr *)data; 988 struct ifreq *ifr = (struct ifreq *)data; 989 int s, error = 0; 990 991 s = splnet(); 992 993 switch (cmd) { 994 case SIOCSIFADDR: 995 ifp->if_flags |= IFF_UP; 996 switch (ifa->ifa_addr->sa_family) { 997 #ifdef INET 998 case AF_INET: 999 beinit(sc); 1000 arp_ifinit(ifp, ifa); 1001 break; 1002 #endif /* INET */ 1003 default: 1004 beinit(sc); 1005 break; 1006 } 1007 break; 1008 1009 case SIOCSIFFLAGS: 1010 if ((ifp->if_flags & IFF_UP) == 0 && 1011 (ifp->if_flags & IFF_RUNNING) != 0) { 1012 /* 1013 * If interface is marked down and it is running, then 1014 * stop it. 1015 */ 1016 bestop(sc); 1017 ifp->if_flags &= ~IFF_RUNNING; 1018 } else if ((ifp->if_flags & IFF_UP) != 0 && 1019 (ifp->if_flags & IFF_RUNNING) == 0) { 1020 /* 1021 * If interface is marked up and it is stopped, then 1022 * start it. 1023 */ 1024 beinit(sc); 1025 } else { 1026 /* 1027 * Reset the interface to pick up changes in any other 1028 * flags that affect hardware registers. 1029 */ 1030 bestop(sc); 1031 beinit(sc); 1032 } 1033 #ifdef BEDEBUG 1034 if (ifp->if_flags & IFF_DEBUG) 1035 sc->sc_debug = 1; 1036 else 1037 sc->sc_debug = 0; 1038 #endif 1039 break; 1040 1041 case SIOCADDMULTI: 1042 case SIOCDELMULTI: 1043 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1044 /* 1045 * Multicast list has changed; set the hardware filter 1046 * accordingly. 1047 */ 1048 if (ifp->if_flags & IFF_RUNNING) 1049 be_mcreset(sc); 1050 error = 0; 1051 } 1052 break; 1053 case SIOCGIFMEDIA: 1054 case SIOCSIFMEDIA: 1055 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1056 break; 1057 default: 1058 error = EINVAL; 1059 break; 1060 } 1061 splx(s); 1062 return (error); 1063 } 1064 1065 1066 void 1067 beinit(sc) 1068 struct be_softc *sc; 1069 { 1070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1071 bus_space_tag_t t = sc->sc_bustag; 1072 bus_space_handle_t br = sc->sc_br; 1073 bus_space_handle_t cr = sc->sc_cr; 1074 struct qec_softc *qec = sc->sc_qec; 1075 u_int32_t v; 1076 u_int32_t qecaddr; 1077 u_int8_t *ea; 1078 int rc, s; 1079 1080 s = splnet(); 1081 1082 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1083 1084 bestop(sc); 1085 1086 ea = sc->sc_enaddr; 1087 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1088 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1089 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1090 1091 /* Clear hash table */ 1092 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1093 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1094 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1095 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1096 1097 /* Re-initialize RX configuration */ 1098 v = BE_BR_RXCFG_FIFO; 1099 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1100 1101 be_mcreset(sc); 1102 1103 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1104 1105 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1106 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1107 1108 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1109 1110 /* 1111 * Turn off counter expiration interrupts as well as 1112 * 'gotframe' and 'sentframe' 1113 */ 1114 bus_space_write_4(t, br, BE_BRI_IMASK, 1115 BE_BR_IMASK_GOTFRAME | 1116 BE_BR_IMASK_RCNTEXP | 1117 BE_BR_IMASK_ACNTEXP | 1118 BE_BR_IMASK_CCNTEXP | 1119 BE_BR_IMASK_LCNTEXP | 1120 BE_BR_IMASK_CVCNTEXP | 1121 BE_BR_IMASK_SENTFRAME | 1122 BE_BR_IMASK_NCNTEXP | 1123 BE_BR_IMASK_ECNTEXP | 1124 BE_BR_IMASK_LCCNTEXP | 1125 BE_BR_IMASK_FCNTEXP | 1126 BE_BR_IMASK_DTIMEXP); 1127 1128 /* Channel registers: */ 1129 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1130 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1131 1132 qecaddr = sc->sc_channel * qec->sc_msize; 1133 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1134 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1135 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1136 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1137 1138 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1139 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1140 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1141 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1142 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1143 1144 /* Set max packet length */ 1145 v = ETHER_MAX_LEN; 1146 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1147 v += ETHER_VLAN_ENCAP_LEN; 1148 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1149 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1150 1151 /* Enable transmitter */ 1152 bus_space_write_4(t, br, BE_BRI_TXCFG, 1153 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1154 1155 /* Enable receiver */ 1156 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1157 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1158 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1159 1160 if ((rc = be_ifmedia_upd(ifp)) != 0) 1161 goto out; 1162 1163 ifp->if_flags |= IFF_RUNNING; 1164 ifp->if_flags &= ~IFF_OACTIVE; 1165 1166 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1167 out: 1168 splx(s); 1169 } 1170 1171 void 1172 be_mcreset(sc) 1173 struct be_softc *sc; 1174 { 1175 struct ethercom *ec = &sc->sc_ethercom; 1176 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1177 bus_space_tag_t t = sc->sc_bustag; 1178 bus_space_handle_t br = sc->sc_br; 1179 u_int32_t crc; 1180 u_int16_t hash[4]; 1181 u_int8_t octet; 1182 u_int32_t v; 1183 int i, j; 1184 struct ether_multi *enm; 1185 struct ether_multistep step; 1186 1187 if (ifp->if_flags & IFF_PROMISC) { 1188 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1189 v |= BE_BR_RXCFG_PMISC; 1190 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1191 return; 1192 } 1193 1194 if (ifp->if_flags & IFF_ALLMULTI) { 1195 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1196 goto chipit; 1197 } 1198 1199 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1200 1201 ETHER_FIRST_MULTI(step, ec, enm); 1202 while (enm != NULL) { 1203 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1204 /* 1205 * We must listen to a range of multicast 1206 * addresses. For now, just accept all 1207 * multicasts, rather than trying to set only 1208 * those filter bits needed to match the range. 1209 * (At this time, the only use of address 1210 * ranges is for IP multicast routing, for 1211 * which the range is big enough to require 1212 * all bits set.) 1213 */ 1214 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1215 ifp->if_flags |= IFF_ALLMULTI; 1216 goto chipit; 1217 } 1218 1219 crc = 0xffffffff; 1220 1221 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1222 octet = enm->enm_addrlo[i]; 1223 1224 for (j = 0; j < 8; j++) { 1225 if ((crc & 1) ^ (octet & 1)) { 1226 crc >>= 1; 1227 crc ^= MC_POLY_LE; 1228 } 1229 else 1230 crc >>= 1; 1231 octet >>= 1; 1232 } 1233 } 1234 1235 crc >>= 26; 1236 hash[crc >> 4] |= 1 << (crc & 0xf); 1237 ETHER_NEXT_MULTI(step, enm); 1238 } 1239 1240 ifp->if_flags &= ~IFF_ALLMULTI; 1241 1242 chipit: 1243 /* Enable the hash filter */ 1244 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1245 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1246 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1247 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1248 1249 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1250 v &= ~BE_BR_RXCFG_PMISC; 1251 v |= BE_BR_RXCFG_HENABLE; 1252 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1253 } 1254 1255 /* 1256 * Set the tcvr to an idle state 1257 */ 1258 void 1259 be_mii_sync(sc) 1260 struct be_softc *sc; 1261 { 1262 bus_space_tag_t t = sc->sc_bustag; 1263 bus_space_handle_t tr = sc->sc_tr; 1264 int n = 32; 1265 1266 while (n--) { 1267 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1268 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1269 MGMT_PAL_OENAB); 1270 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1271 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1272 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1273 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1274 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1275 } 1276 } 1277 1278 void 1279 be_pal_gate(sc, phy) 1280 struct be_softc *sc; 1281 int phy; 1282 { 1283 bus_space_tag_t t = sc->sc_bustag; 1284 bus_space_handle_t tr = sc->sc_tr; 1285 u_int32_t v; 1286 1287 be_mii_sync(sc); 1288 1289 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1290 if (phy == BE_PHY_INTERNAL) 1291 v &= ~TCVR_PAL_SERIAL; 1292 1293 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1294 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1295 } 1296 1297 static int 1298 be_tcvr_read_bit(sc, phy) 1299 struct be_softc *sc; 1300 int phy; 1301 { 1302 bus_space_tag_t t = sc->sc_bustag; 1303 bus_space_handle_t tr = sc->sc_tr; 1304 int ret; 1305 1306 if (phy == BE_PHY_INTERNAL) { 1307 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1308 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1309 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1310 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1311 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1312 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1313 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1314 } else { 1315 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1316 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1317 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1318 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1319 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1320 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1321 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1322 } 1323 1324 return (ret); 1325 } 1326 1327 static void 1328 be_tcvr_write_bit(sc, phy, bit) 1329 struct be_softc *sc; 1330 int phy; 1331 int bit; 1332 { 1333 bus_space_tag_t t = sc->sc_bustag; 1334 bus_space_handle_t tr = sc->sc_tr; 1335 u_int32_t v; 1336 1337 if (phy == BE_PHY_INTERNAL) { 1338 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1339 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1340 } else { 1341 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1342 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1343 } 1344 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1345 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1346 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1347 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1348 } 1349 1350 static void 1351 be_mii_sendbits(sc, phy, data, nbits) 1352 struct be_softc *sc; 1353 int phy; 1354 u_int32_t data; 1355 int nbits; 1356 { 1357 int i; 1358 1359 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1360 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1361 } 1362 } 1363 1364 static int 1365 be_mii_readreg(self, phy, reg) 1366 struct device *self; 1367 int phy, reg; 1368 { 1369 struct be_softc *sc = (struct be_softc *)self; 1370 int val = 0, i; 1371 1372 /* 1373 * Read the PHY register by manually driving the MII control lines. 1374 */ 1375 be_mii_sync(sc); 1376 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1377 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1378 be_mii_sendbits(sc, phy, phy, 5); 1379 be_mii_sendbits(sc, phy, reg, 5); 1380 1381 (void) be_tcvr_read_bit(sc, phy); 1382 (void) be_tcvr_read_bit(sc, phy); 1383 1384 for (i = 15; i >= 0; i--) 1385 val |= (be_tcvr_read_bit(sc, phy) << i); 1386 1387 (void) be_tcvr_read_bit(sc, phy); 1388 (void) be_tcvr_read_bit(sc, phy); 1389 (void) be_tcvr_read_bit(sc, phy); 1390 1391 return (val); 1392 } 1393 1394 void 1395 be_mii_writereg(self, phy, reg, val) 1396 struct device *self; 1397 int phy, reg, val; 1398 { 1399 struct be_softc *sc = (struct be_softc *)self; 1400 int i; 1401 1402 /* 1403 * Write the PHY register by manually driving the MII control lines. 1404 */ 1405 be_mii_sync(sc); 1406 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1407 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1408 be_mii_sendbits(sc, phy, phy, 5); 1409 be_mii_sendbits(sc, phy, reg, 5); 1410 1411 be_tcvr_write_bit(sc, phy, 1); 1412 be_tcvr_write_bit(sc, phy, 0); 1413 1414 for (i = 15; i >= 0; i--) 1415 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1416 } 1417 1418 int 1419 be_mii_reset(sc, phy) 1420 struct be_softc *sc; 1421 int phy; 1422 { 1423 int n; 1424 1425 be_mii_writereg((struct device *)sc, phy, MII_BMCR, 1426 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1427 be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET); 1428 1429 for (n = 16; n >= 0; n--) { 1430 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR); 1431 if ((bmcr & BMCR_RESET) == 0) 1432 break; 1433 DELAY(20); 1434 } 1435 if (n == 0) { 1436 aprint_error_dev(&sc->sc_dev, "bmcr reset failed\n"); 1437 return (EIO); 1438 } 1439 1440 return (0); 1441 } 1442 1443 void 1444 be_tick(arg) 1445 void *arg; 1446 { 1447 struct be_softc *sc = arg; 1448 int s = splnet(); 1449 1450 mii_tick(&sc->sc_mii); 1451 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1452 1453 splx(s); 1454 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1455 } 1456 1457 void 1458 be_mii_statchg(self) 1459 struct device *self; 1460 { 1461 struct be_softc *sc = (struct be_softc *)self; 1462 bus_space_tag_t t = sc->sc_bustag; 1463 bus_space_handle_t br = sc->sc_br; 1464 u_int instance; 1465 u_int32_t v; 1466 1467 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1468 #ifdef DIAGNOSTIC 1469 if (instance > 1) 1470 panic("be_mii_statchg: instance %d out of range", instance); 1471 #endif 1472 1473 /* Update duplex mode in TX configuration */ 1474 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1475 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1476 v |= BE_BR_TXCFG_FULLDPLX; 1477 else 1478 v &= ~BE_BR_TXCFG_FULLDPLX; 1479 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1480 1481 /* Change to appropriate gate in transceiver PAL */ 1482 be_pal_gate(sc, sc->sc_phys[instance]); 1483 } 1484 1485 /* 1486 * Get current media settings. 1487 */ 1488 void 1489 be_ifmedia_sts(ifp, ifmr) 1490 struct ifnet *ifp; 1491 struct ifmediareq *ifmr; 1492 { 1493 struct be_softc *sc = ifp->if_softc; 1494 1495 mii_pollstat(&sc->sc_mii); 1496 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1497 1498 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1499 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1500 return; 1501 } 1502 1503 /* 1504 * Set media options. 1505 */ 1506 int 1507 be_ifmedia_upd(ifp) 1508 struct ifnet *ifp; 1509 { 1510 struct be_softc *sc = ifp->if_softc; 1511 int error; 1512 1513 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1514 error = 0; 1515 else if (error != 0) 1516 return error; 1517 1518 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1519 } 1520 1521 /* 1522 * Service routine for our pseudo-MII internal transceiver. 1523 */ 1524 int 1525 be_intphy_service(sc, mii, cmd) 1526 struct be_softc *sc; 1527 struct mii_data *mii; 1528 int cmd; 1529 { 1530 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1531 int bmcr, bmsr; 1532 int error; 1533 1534 switch (cmd) { 1535 case MII_POLLSTAT: 1536 /* 1537 * If we're not polling our PHY instance, just return. 1538 */ 1539 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1540 return (0); 1541 1542 break; 1543 1544 case MII_MEDIACHG: 1545 1546 /* 1547 * If the media indicates a different PHY instance, 1548 * isolate ourselves. 1549 */ 1550 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1551 bmcr = be_mii_readreg((void *)sc, 1552 BE_PHY_INTERNAL, MII_BMCR); 1553 be_mii_writereg((void *)sc, 1554 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1555 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1556 sc->sc_intphy_curspeed = 0; 1557 return (0); 1558 } 1559 1560 1561 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1562 return (error); 1563 1564 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1565 1566 /* 1567 * Select the new mode and take out of isolation 1568 */ 1569 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1570 bmcr |= BMCR_S100; 1571 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1572 bmcr &= ~BMCR_S100; 1573 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1574 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1575 bmcr &= ~BMCR_S100; 1576 bmcr |= sc->sc_intphy_curspeed; 1577 } else { 1578 /* Keep isolated until link is up */ 1579 bmcr |= BMCR_ISO; 1580 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1581 } 1582 } 1583 1584 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1585 bmcr |= BMCR_FDX; 1586 else 1587 bmcr &= ~BMCR_FDX; 1588 1589 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1590 break; 1591 1592 case MII_TICK: 1593 /* 1594 * If we're not currently selected, just return. 1595 */ 1596 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1597 return (0); 1598 1599 /* Only used for automatic media selection */ 1600 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1601 return (0); 1602 1603 /* Is the interface even up? */ 1604 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1605 return (0); 1606 1607 /* 1608 * Check link status; if we don't have a link, try another 1609 * speed. We can't detect duplex mode, so half-duplex is 1610 * what we have to settle for. 1611 */ 1612 1613 /* Read twice in case the register is latched */ 1614 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1615 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1616 1617 if ((bmsr & BMSR_LINK) != 0) { 1618 /* We have a carrier */ 1619 bmcr = be_mii_readreg((void *)sc, 1620 BE_PHY_INTERNAL, MII_BMCR); 1621 1622 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1623 bmcr = be_mii_readreg((void *)sc, 1624 BE_PHY_INTERNAL, MII_BMCR); 1625 1626 sc->sc_mii_flags |= MIIF_HAVELINK; 1627 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1628 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1629 1630 bmcr &= ~BMCR_ISO; 1631 be_mii_writereg((void *)sc, 1632 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1633 1634 printf("%s: link up at %s Mbps\n", 1635 device_xname(&sc->sc_dev), 1636 (bmcr & BMCR_S100) ? "100" : "10"); 1637 } 1638 return (0); 1639 } 1640 1641 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1642 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1643 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1644 sc->sc_intphy_curspeed = 0; 1645 printf("%s: link down\n", device_xname(&sc->sc_dev)); 1646 } 1647 1648 /* Only retry autonegotiation every 5 seconds. */ 1649 if (++sc->sc_mii_ticks < 5) 1650 return(0); 1651 1652 sc->sc_mii_ticks = 0; 1653 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1654 /* Just flip the fast speed bit */ 1655 bmcr ^= BMCR_S100; 1656 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1657 1658 break; 1659 1660 case MII_DOWN: 1661 /* Isolate this phy */ 1662 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1663 be_mii_writereg((void *)sc, 1664 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1665 return (0); 1666 } 1667 1668 /* Update the media status. */ 1669 be_intphy_status(sc); 1670 1671 /* Callback if something changed. */ 1672 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1673 (*mii->mii_statchg)((struct device *)sc); 1674 sc->sc_mii_active = mii->mii_media_active; 1675 } 1676 return (0); 1677 } 1678 1679 /* 1680 * Determine status of internal transceiver 1681 */ 1682 void 1683 be_intphy_status(sc) 1684 struct be_softc *sc; 1685 { 1686 struct mii_data *mii = &sc->sc_mii; 1687 int media_active, media_status; 1688 int bmcr, bmsr; 1689 1690 media_status = IFM_AVALID; 1691 media_active = 0; 1692 1693 /* 1694 * Internal transceiver; do the work here. 1695 */ 1696 bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR); 1697 1698 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1699 case (BMCR_S100 | BMCR_FDX): 1700 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1701 break; 1702 case BMCR_S100: 1703 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1704 break; 1705 case BMCR_FDX: 1706 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1707 break; 1708 case 0: 1709 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1710 break; 1711 } 1712 1713 /* Read twice in case the register is latched */ 1714 bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)| 1715 be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR); 1716 if (bmsr & BMSR_LINK) 1717 media_status |= IFM_ACTIVE; 1718 1719 mii->mii_media_status = media_status; 1720 mii->mii_media_active = media_active; 1721 } 1722
Indexes created Tue Sep 30 11:09:46 GMT 2025