be.c revision 1.57.4.4
1 /* $NetBSD: be.c,v 1.57.4.4 2010/03/11 15:04:02 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.57.4.4 2010/03/11 15:04:02 yamt Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "rnd.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/callout.h> 69 #include <sys/kernel.h> 70 #include <sys/errno.h> 71 #include <sys/ioctl.h> 72 #include <sys/mbuf.h> 73 #include <sys/socket.h> 74 #include <sys/syslog.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #if NRND > 0 78 #include <sys/rnd.h> 79 #endif 80 81 #include <net/if.h> 82 #include <net/if_dl.h> 83 #include <net/if_types.h> 84 #include <net/netisr.h> 85 #include <net/if_media.h> 86 #include <net/if_ether.h> 87 88 #ifdef INET 89 #include <netinet/in.h> 90 #include <netinet/if_inarp.h> 91 #include <netinet/in_systm.h> 92 #include <netinet/in_var.h> 93 #include <netinet/ip.h> 94 #endif 95 96 97 #include <net/bpf.h> 98 #include <net/bpfdesc.h> 99 100 #include <sys/bus.h> 101 #include <sys/intr.h> 102 #include <machine/autoconf.h> 103 104 #include <dev/sbus/sbusvar.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/sbus/qecreg.h> 110 #include <dev/sbus/qecvar.h> 111 #include <dev/sbus/bereg.h> 112 113 struct be_softc { 114 device_t sc_dev; 115 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 116 bus_dma_tag_t sc_dmatag; 117 bus_dmamap_t sc_dmamap; 118 struct ethercom sc_ethercom; 119 /*struct ifmedia sc_ifmedia; -* interface media */ 120 struct mii_data sc_mii; /* MII media control */ 121 #define sc_media sc_mii.mii_media/* shorthand */ 122 int sc_phys[2]; /* MII instance -> phy */ 123 124 struct callout sc_tick_ch; 125 126 /* 127 * Some `mii_softc' items we need to emulate MII operation 128 * for our internal transceiver. 129 */ 130 int sc_mii_inst; /* instance of internal phy */ 131 int sc_mii_active; /* currently active medium */ 132 int sc_mii_ticks; /* tick counter */ 133 int sc_mii_flags; /* phy status flags */ 134 #define MIIF_HAVELINK 0x04000000 135 int sc_intphy_curspeed; /* Established link speed */ 136 137 struct qec_softc *sc_qec; /* QEC parent */ 138 139 bus_space_handle_t sc_qr; /* QEC registers */ 140 bus_space_handle_t sc_br; /* BE registers */ 141 bus_space_handle_t sc_cr; /* channel registers */ 142 bus_space_handle_t sc_tr; /* transceiver registers */ 143 144 u_int sc_rev; 145 146 int sc_channel; /* channel number */ 147 int sc_burst; 148 149 struct qec_ring sc_rb; /* Packet Ring Buffer */ 150 151 /* MAC address */ 152 uint8_t sc_enaddr[ETHER_ADDR_LEN]; 153 #ifdef BEDEBUG 154 int sc_debug; 155 #endif 156 }; 157 158 static int bematch(device_t, cfdata_t, void *); 159 static void beattach(device_t, device_t, void *); 160 161 static int beinit(struct ifnet *); 162 static void bestart(struct ifnet *); 163 static void bestop(struct ifnet *, int); 164 static void bewatchdog(struct ifnet *); 165 static int beioctl(struct ifnet *, u_long, void *); 166 static void bereset(struct be_softc *); 167 static void behwreset(struct be_softc *); 168 169 static int beintr(void *); 170 static int berint(struct be_softc *); 171 static int betint(struct be_softc *); 172 static int beqint(struct be_softc *, uint32_t); 173 static int beeint(struct be_softc *, uint32_t); 174 175 static void be_read(struct be_softc *, int, int); 176 static int be_put(struct be_softc *, int, struct mbuf *); 177 static struct mbuf *be_get(struct be_softc *, int, int); 178 179 static void be_pal_gate(struct be_softc *, int); 180 181 /* ifmedia callbacks */ 182 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 183 static int be_ifmedia_upd(struct ifnet *); 184 185 static void be_mcreset(struct be_softc *); 186 187 /* MII methods & callbacks */ 188 static int be_mii_readreg(device_t, int, int); 189 static void be_mii_writereg(device_t, int, int, int); 190 static void be_mii_statchg(device_t); 191 192 /* MII helpers */ 193 static void be_mii_sync(struct be_softc *); 194 static void be_mii_sendbits(struct be_softc *, int, uint32_t, int); 195 static int be_mii_reset(struct be_softc *, int); 196 static int be_tcvr_read_bit(struct be_softc *, int); 197 static void be_tcvr_write_bit(struct be_softc *, int, int); 198 199 static void be_tick(void *); 200 #if 0 201 static void be_intphy_auto(struct be_softc *); 202 #endif 203 static void be_intphy_status(struct be_softc *); 204 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 205 206 207 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 208 bematch, beattach, NULL, NULL); 209 210 int 211 bematch(device_t parent, cfdata_t cf, void *aux) 212 { 213 struct sbus_attach_args *sa = aux; 214 215 return strcmp(cf->cf_name, sa->sa_name) == 0; 216 } 217 218 void 219 beattach(device_t parent, device_t self, void *aux) 220 { 221 struct sbus_attach_args *sa = aux; 222 struct qec_softc *qec = device_private(parent); 223 struct be_softc *sc = device_private(self); 224 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 225 struct mii_data *mii = &sc->sc_mii; 226 struct mii_softc *child; 227 int node = sa->sa_node; 228 bus_dma_tag_t dmatag = sa->sa_dmatag; 229 bus_dma_segment_t seg; 230 bus_size_t size; 231 int instance; 232 int rseg, error; 233 uint32_t v; 234 235 sc->sc_dev = self; 236 237 if (sa->sa_nreg < 3) { 238 printf(": only %d register sets\n", sa->sa_nreg); 239 return; 240 } 241 242 if (bus_space_map(sa->sa_bustag, 243 (bus_addr_t)BUS_ADDR(sa->sa_reg[0].oa_space, sa->sa_reg[0].oa_base), 244 (bus_size_t)sa->sa_reg[0].oa_size, 245 0, &sc->sc_cr) != 0) { 246 printf(": cannot map registers\n"); 247 return; 248 } 249 250 if (bus_space_map(sa->sa_bustag, 251 (bus_addr_t)BUS_ADDR(sa->sa_reg[1].oa_space, sa->sa_reg[1].oa_base), 252 (bus_size_t)sa->sa_reg[1].oa_size, 253 0, &sc->sc_br) != 0) { 254 printf(": cannot map registers\n"); 255 return; 256 } 257 258 if (bus_space_map(sa->sa_bustag, 259 (bus_addr_t)BUS_ADDR(sa->sa_reg[2].oa_space, sa->sa_reg[2].oa_base), 260 (bus_size_t)sa->sa_reg[2].oa_size, 261 0, &sc->sc_tr) != 0) { 262 printf(": cannot map registers\n"); 263 return; 264 } 265 266 sc->sc_bustag = sa->sa_bustag; 267 sc->sc_qec = qec; 268 sc->sc_qr = qec->sc_regs; 269 270 sc->sc_rev = prom_getpropint(node, "board-version", -1); 271 printf(": rev %x,", sc->sc_rev); 272 273 callout_init(&sc->sc_tick_ch, 0); 274 275 sc->sc_channel = prom_getpropint(node, "channel#", -1); 276 if (sc->sc_channel == -1) 277 sc->sc_channel = 0; 278 279 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 280 if (sc->sc_burst == -1) 281 sc->sc_burst = qec->sc_burst; 282 283 /* Clamp at parent's burst sizes */ 284 sc->sc_burst &= qec->sc_burst; 285 286 /* Establish interrupt handler */ 287 if (sa->sa_nintr) 288 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 289 beintr, sc); 290 291 prom_getether(node, sc->sc_enaddr); 292 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 293 294 /* 295 * Allocate descriptor ring and buffers. 296 */ 297 298 /* for now, allocate as many bufs as there are ring descriptors */ 299 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 300 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 301 302 size = 303 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 304 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 305 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 306 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 307 308 /* Get a DMA handle */ 309 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 310 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 311 aprint_error_dev(self, "DMA map create error %d\n", error); 312 return; 313 } 314 315 /* Allocate DMA buffer */ 316 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 317 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 318 aprint_error_dev(self, "DMA buffer alloc error %d\n", error); 319 return; 320 } 321 322 /* Map DMA memory in CPU addressable space */ 323 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 324 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 325 aprint_error_dev(self, "DMA buffer map error %d\n", error); 326 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 327 return; 328 } 329 330 /* Load the buffer */ 331 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 332 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) { 333 aprint_error_dev(self, "DMA buffer map load error %d\n", error); 334 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 335 bus_dmamem_free(dmatag, &seg, rseg); 336 return; 337 } 338 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 339 340 /* 341 * Initialize our media structures and MII info. 342 */ 343 mii->mii_ifp = ifp; 344 mii->mii_readreg = be_mii_readreg; 345 mii->mii_writereg = be_mii_writereg; 346 mii->mii_statchg = be_mii_statchg; 347 348 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 349 350 /* 351 * Initialize transceiver and determine which PHY connection to use. 352 */ 353 be_mii_sync(sc); 354 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 355 356 instance = 0; 357 358 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 359 360 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 361 MII_OFFSET_ANY, 0); 362 363 child = LIST_FIRST(&mii->mii_phys); 364 if (child == NULL) { 365 /* No PHY attached */ 366 ifmedia_add(&sc->sc_media, 367 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance), 368 0, NULL); 369 ifmedia_set(&sc->sc_media, 370 IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, instance)); 371 } else { 372 /* 373 * Note: we support just one PHY on the external 374 * MII connector. 375 */ 376 #ifdef DIAGNOSTIC 377 if (LIST_NEXT(child, mii_list) != NULL) { 378 aprint_error_dev(self, 379 "spurious MII device %s attached\n", 380 device_xname(child->mii_dev)); 381 } 382 #endif 383 if (child->mii_phy != BE_PHY_EXTERNAL || 384 child->mii_inst > 0) { 385 aprint_error_dev(self, 386 "cannot accommodate MII device %s" 387 " at phy %d, instance %d\n", 388 device_xname(child->mii_dev), 389 child->mii_phy, child->mii_inst); 390 } else { 391 sc->sc_phys[instance] = child->mii_phy; 392 } 393 394 /* 395 * XXX - we can really do the following ONLY if the 396 * phy indeed has the auto negotiation capability!! 397 */ 398 ifmedia_set(&sc->sc_media, 399 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 400 401 /* Mark our current media setting */ 402 be_pal_gate(sc, BE_PHY_EXTERNAL); 403 instance++; 404 } 405 406 } 407 408 if ((v & MGMT_PAL_INT_MDIO) != 0) { 409 /* 410 * The be internal phy looks vaguely like MII hardware, 411 * but not enough to be able to use the MII device 412 * layer. Hence, we have to take care of media selection 413 * ourselves. 414 */ 415 416 sc->sc_mii_inst = instance; 417 sc->sc_phys[instance] = BE_PHY_INTERNAL; 418 419 /* Use `ifm_data' to store BMCR bits */ 420 ifmedia_add(&sc->sc_media, 421 IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, instance), 422 0, NULL); 423 ifmedia_add(&sc->sc_media, 424 IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, instance), 425 BMCR_S100, NULL); 426 ifmedia_add(&sc->sc_media, 427 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance), 428 0, NULL); 429 430 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 431 device_xname(self)); 432 433 be_mii_reset(sc, BE_PHY_INTERNAL); 434 /* Only set default medium here if there's no external PHY */ 435 if (instance == 0) { 436 be_pal_gate(sc, BE_PHY_INTERNAL); 437 ifmedia_set(&sc->sc_media, 438 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, instance)); 439 } else 440 be_mii_writereg(self, 441 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 442 } 443 444 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 445 ifp->if_softc = sc; 446 ifp->if_start = bestart; 447 ifp->if_ioctl = beioctl; 448 ifp->if_watchdog = bewatchdog; 449 ifp->if_init = beinit; 450 ifp->if_stop = bestop; 451 ifp->if_flags = 452 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 453 IFQ_SET_READY(&ifp->if_snd); 454 455 /* claim 802.1q capability */ 456 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 457 458 /* Attach the interface. */ 459 if_attach(ifp); 460 ether_ifattach(ifp, sc->sc_enaddr); 461 } 462 463 464 /* 465 * Routine to copy from mbuf chain to transmit buffer in 466 * network buffer memory. 467 */ 468 static inline int 469 be_put(struct be_softc *sc, int idx, struct mbuf *m) 470 { 471 struct mbuf *n; 472 int len, tlen = 0, boff = 0; 473 uint8_t *bp; 474 475 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 476 477 for (; m; m = n) { 478 len = m->m_len; 479 if (len == 0) { 480 MFREE(m, n); 481 continue; 482 } 483 memcpy(bp + boff, mtod(m, void *), len); 484 boff += len; 485 tlen += len; 486 MFREE(m, n); 487 } 488 return tlen; 489 } 490 491 /* 492 * Pull data off an interface. 493 * Len is the length of data, with local net header stripped. 494 * We copy the data into mbufs. When full cluster sized units are present, 495 * we copy into clusters. 496 */ 497 static inline struct mbuf * 498 be_get(struct be_softc *sc, int idx, int totlen) 499 { 500 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 501 struct mbuf *m; 502 struct mbuf *top, **mp; 503 int len, pad, boff = 0; 504 uint8_t *bp; 505 506 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 507 508 MGETHDR(m, M_DONTWAIT, MT_DATA); 509 if (m == NULL) 510 return (NULL); 511 m->m_pkthdr.rcvif = ifp; 512 m->m_pkthdr.len = totlen; 513 514 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 515 m->m_data += pad; 516 len = MHLEN - pad; 517 top = NULL; 518 mp = ⊤ 519 520 while (totlen > 0) { 521 if (top) { 522 MGET(m, M_DONTWAIT, MT_DATA); 523 if (m == NULL) { 524 m_freem(top); 525 return (NULL); 526 } 527 len = MLEN; 528 } 529 if (top && totlen >= MINCLSIZE) { 530 MCLGET(m, M_DONTWAIT); 531 if (m->m_flags & M_EXT) 532 len = MCLBYTES; 533 } 534 m->m_len = len = min(totlen, len); 535 memcpy(mtod(m, void *), bp + boff, len); 536 boff += len; 537 totlen -= len; 538 *mp = m; 539 mp = &m->m_next; 540 } 541 542 return top; 543 } 544 545 /* 546 * Pass a packet to the higher levels. 547 */ 548 static inline void 549 be_read(struct be_softc *sc, int idx, int len) 550 { 551 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 552 struct mbuf *m; 553 554 if (len <= sizeof(struct ether_header) || 555 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 556 #ifdef BEDEBUG 557 if (sc->sc_debug) 558 printf("%s: invalid packet size %d; dropping\n", 559 ifp->if_xname, len); 560 #endif 561 ifp->if_ierrors++; 562 return; 563 } 564 565 /* 566 * Pull packet off interface. 567 */ 568 m = be_get(sc, idx, len); 569 if (m == NULL) { 570 ifp->if_ierrors++; 571 return; 572 } 573 ifp->if_ipackets++; 574 575 /* 576 * Check if there's a BPF listener on this interface. 577 * If so, hand off the raw packet to BPF. 578 */ 579 if (ifp->if_bpf) 580 bpf_ops->bpf_mtap(ifp->if_bpf, m); 581 /* Pass the packet up. */ 582 (*ifp->if_input)(ifp, m); 583 } 584 585 /* 586 * Start output on interface. 587 * We make two assumptions here: 588 * 1) that the current priority is set to splnet _before_ this code 589 * is called *and* is returned to the appropriate priority after 590 * return 591 * 2) that the IFF_OACTIVE flag is checked before this code is called 592 * (i.e. that the output part of the interface is idle) 593 */ 594 void 595 bestart(struct ifnet *ifp) 596 { 597 struct be_softc *sc = ifp->if_softc; 598 struct qec_xd *txd = sc->sc_rb.rb_txd; 599 struct mbuf *m; 600 unsigned int bix, len; 601 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 602 603 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 604 return; 605 606 bix = sc->sc_rb.rb_tdhead; 607 608 for (;;) { 609 IFQ_DEQUEUE(&ifp->if_snd, m); 610 if (m == 0) 611 break; 612 613 /* 614 * If BPF is listening on this interface, let it see the 615 * packet before we commit it to the wire. 616 */ 617 if (ifp->if_bpf) 618 bpf_ops->bpf_mtap(ifp->if_bpf, m); 619 620 /* 621 * Copy the mbuf chain into the transmit buffer. 622 */ 623 len = be_put(sc, bix, m); 624 625 /* 626 * Initialize transmit registers and start transmission 627 */ 628 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 629 (len & QEC_XD_LENGTH); 630 bus_space_write_4(sc->sc_bustag, sc->sc_cr, 631 BE_CRI_CTRL, BE_CR_CTRL_TWAKEUP); 632 633 if (++bix == QEC_XD_RING_MAXSIZE) 634 bix = 0; 635 636 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 637 ifp->if_flags |= IFF_OACTIVE; 638 break; 639 } 640 } 641 642 sc->sc_rb.rb_tdhead = bix; 643 } 644 645 void 646 bestop(struct ifnet *ifp, int disable) 647 { 648 struct be_softc *sc = ifp->if_softc; 649 650 callout_stop(&sc->sc_tick_ch); 651 652 /* Down the MII. */ 653 mii_down(&sc->sc_mii); 654 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 655 656 behwreset(sc); 657 } 658 659 void 660 behwreset(struct be_softc *sc) 661 { 662 int n; 663 bus_space_tag_t t = sc->sc_bustag; 664 bus_space_handle_t br = sc->sc_br; 665 666 /* Stop the transmitter */ 667 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 668 for (n = 32; n > 0; n--) { 669 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 670 break; 671 DELAY(20); 672 } 673 674 /* Stop the receiver */ 675 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 676 for (n = 32; n > 0; n--) { 677 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 678 break; 679 DELAY(20); 680 } 681 } 682 683 /* 684 * Reset interface. 685 */ 686 void 687 bereset(struct be_softc *sc) 688 { 689 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 690 int s; 691 692 s = splnet(); 693 behwreset(sc); 694 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 695 beinit(ifp); 696 splx(s); 697 } 698 699 void 700 bewatchdog(struct ifnet *ifp) 701 { 702 struct be_softc *sc = ifp->if_softc; 703 704 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 705 ++sc->sc_ethercom.ec_if.if_oerrors; 706 707 bereset(sc); 708 } 709 710 int 711 beintr(void *arg) 712 { 713 struct be_softc *sc = arg; 714 bus_space_tag_t t = sc->sc_bustag; 715 uint32_t whyq, whyb, whyc; 716 int r = 0; 717 718 /* Read QEC status, channel status and BE status */ 719 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 720 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 721 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 722 723 if (whyq & QEC_STAT_BM) 724 r |= beeint(sc, whyb); 725 726 if (whyq & QEC_STAT_ER) 727 r |= beqint(sc, whyc); 728 729 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 730 r |= betint(sc); 731 732 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 733 r |= berint(sc); 734 735 return r; 736 } 737 738 /* 739 * QEC Interrupt. 740 */ 741 int 742 beqint(struct be_softc *sc, uint32_t why) 743 { 744 device_t self = sc->sc_dev; 745 int r = 0, rst = 0; 746 747 if (why & BE_CR_STAT_TXIRQ) 748 r |= 1; 749 if (why & BE_CR_STAT_RXIRQ) 750 r |= 1; 751 752 if (why & BE_CR_STAT_BERROR) { 753 r |= 1; 754 rst = 1; 755 aprint_error_dev(self, "bigmac error\n"); 756 } 757 758 if (why & BE_CR_STAT_TXDERR) { 759 r |= 1; 760 rst = 1; 761 aprint_error_dev(self, "bogus tx descriptor\n"); 762 } 763 764 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 765 r |= 1; 766 rst = 1; 767 aprint_error_dev(self, "tx DMA error ( "); 768 if (why & BE_CR_STAT_TXLERR) 769 printf("Late "); 770 if (why & BE_CR_STAT_TXPERR) 771 printf("Parity "); 772 if (why & BE_CR_STAT_TXSERR) 773 printf("Generic "); 774 printf(")\n"); 775 } 776 777 if (why & BE_CR_STAT_RXDROP) { 778 r |= 1; 779 rst = 1; 780 aprint_error_dev(self, "out of rx descriptors\n"); 781 } 782 783 if (why & BE_CR_STAT_RXSMALL) { 784 r |= 1; 785 rst = 1; 786 aprint_error_dev(self, "rx descriptor too small\n"); 787 } 788 789 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 790 r |= 1; 791 rst = 1; 792 aprint_error_dev(self, "rx DMA error ( "); 793 if (why & BE_CR_STAT_RXLERR) 794 printf("Late "); 795 if (why & BE_CR_STAT_RXPERR) 796 printf("Parity "); 797 if (why & BE_CR_STAT_RXSERR) 798 printf("Generic "); 799 printf(")\n"); 800 } 801 802 if (!r) { 803 rst = 1; 804 aprint_error_dev(self, "unexpected error interrupt %08x\n", 805 why); 806 } 807 808 if (rst) { 809 printf("%s: resetting\n", device_xname(self)); 810 bereset(sc); 811 } 812 813 return r; 814 } 815 816 /* 817 * Error interrupt. 818 */ 819 int 820 beeint(struct be_softc *sc, uint32_t why) 821 { 822 device_t self = sc->sc_dev; 823 int r = 0, rst = 0; 824 825 if (why & BE_BR_STAT_RFIFOVF) { 826 r |= 1; 827 rst = 1; 828 aprint_error_dev(self, "receive fifo overrun\n"); 829 } 830 if (why & BE_BR_STAT_TFIFO_UND) { 831 r |= 1; 832 rst = 1; 833 aprint_error_dev(self, "transmit fifo underrun\n"); 834 } 835 if (why & BE_BR_STAT_MAXPKTERR) { 836 r |= 1; 837 rst = 1; 838 aprint_error_dev(self, "max packet size error\n"); 839 } 840 841 if (!r) { 842 rst = 1; 843 aprint_error_dev(self, "unexpected error interrupt %08x\n", 844 why); 845 } 846 847 if (rst) { 848 printf("%s: resetting\n", device_xname(self)); 849 bereset(sc); 850 } 851 852 return r; 853 } 854 855 /* 856 * Transmit interrupt. 857 */ 858 int 859 betint(struct be_softc *sc) 860 { 861 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 862 bus_space_tag_t t = sc->sc_bustag; 863 bus_space_handle_t br = sc->sc_br; 864 unsigned int bix, txflags; 865 866 /* 867 * Unload collision counters 868 */ 869 ifp->if_collisions += 870 bus_space_read_4(t, br, BE_BRI_NCCNT) + 871 bus_space_read_4(t, br, BE_BRI_FCCNT) + 872 bus_space_read_4(t, br, BE_BRI_EXCNT) + 873 bus_space_read_4(t, br, BE_BRI_LTCNT); 874 875 /* 876 * the clear the hardware counters 877 */ 878 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 879 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 880 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 881 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 882 883 bix = sc->sc_rb.rb_tdtail; 884 885 for (;;) { 886 if (sc->sc_rb.rb_td_nbusy <= 0) 887 break; 888 889 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 890 891 if (txflags & QEC_XD_OWN) 892 break; 893 894 ifp->if_flags &= ~IFF_OACTIVE; 895 ifp->if_opackets++; 896 897 if (++bix == QEC_XD_RING_MAXSIZE) 898 bix = 0; 899 900 --sc->sc_rb.rb_td_nbusy; 901 } 902 903 sc->sc_rb.rb_tdtail = bix; 904 905 bestart(ifp); 906 907 if (sc->sc_rb.rb_td_nbusy == 0) 908 ifp->if_timer = 0; 909 910 return 1; 911 } 912 913 /* 914 * Receive interrupt. 915 */ 916 int 917 berint(struct be_softc *sc) 918 { 919 struct qec_xd *xd = sc->sc_rb.rb_rxd; 920 unsigned int bix, len; 921 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 922 923 bix = sc->sc_rb.rb_rdtail; 924 925 /* 926 * Process all buffers with valid data. 927 */ 928 for (;;) { 929 len = xd[bix].xd_flags; 930 if (len & QEC_XD_OWN) 931 break; 932 933 len &= QEC_XD_LENGTH; 934 be_read(sc, bix, len); 935 936 /* ... */ 937 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 938 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 939 940 if (++bix == QEC_XD_RING_MAXSIZE) 941 bix = 0; 942 } 943 944 sc->sc_rb.rb_rdtail = bix; 945 946 return 1; 947 } 948 949 int 950 beioctl(struct ifnet *ifp, u_long cmd, void *data) 951 { 952 struct be_softc *sc = ifp->if_softc; 953 struct ifaddr *ifa = data; 954 struct ifreq *ifr = data; 955 int s, error = 0; 956 957 s = splnet(); 958 959 switch (cmd) { 960 case SIOCINITIFADDR: 961 ifp->if_flags |= IFF_UP; 962 beinit(ifp); 963 switch (ifa->ifa_addr->sa_family) { 964 #ifdef INET 965 case AF_INET: 966 arp_ifinit(ifp, ifa); 967 break; 968 #endif /* INET */ 969 default: 970 break; 971 } 972 break; 973 974 case SIOCSIFFLAGS: 975 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 976 break; 977 /* XXX re-use ether_ioctl() */ 978 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 979 case IFF_RUNNING: 980 /* 981 * If interface is marked down and it is running, then 982 * stop it. 983 */ 984 bestop(ifp, 0); 985 ifp->if_flags &= ~IFF_RUNNING; 986 break; 987 case IFF_UP: 988 /* 989 * If interface is marked up and it is stopped, then 990 * start it. 991 */ 992 beinit(ifp); 993 break; 994 default: 995 /* 996 * Reset the interface to pick up changes in any other 997 * flags that affect hardware registers. 998 */ 999 bestop(ifp, 0); 1000 beinit(ifp); 1001 break; 1002 } 1003 #ifdef BEDEBUG 1004 if (ifp->if_flags & IFF_DEBUG) 1005 sc->sc_debug = 1; 1006 else 1007 sc->sc_debug = 0; 1008 #endif 1009 break; 1010 1011 case SIOCGIFMEDIA: 1012 case SIOCSIFMEDIA: 1013 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1014 break; 1015 default: 1016 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1017 /* 1018 * Multicast list has changed; set the hardware filter 1019 * accordingly. 1020 */ 1021 if (ifp->if_flags & IFF_RUNNING) 1022 error = beinit(ifp); 1023 else 1024 error = 0; 1025 } 1026 break; 1027 } 1028 splx(s); 1029 return error; 1030 } 1031 1032 1033 int 1034 beinit(struct ifnet *ifp) 1035 { 1036 struct be_softc *sc = ifp->if_softc; 1037 bus_space_tag_t t = sc->sc_bustag; 1038 bus_space_handle_t br = sc->sc_br; 1039 bus_space_handle_t cr = sc->sc_cr; 1040 struct qec_softc *qec = sc->sc_qec; 1041 uint32_t v; 1042 uint32_t qecaddr; 1043 uint8_t *ea; 1044 int rc, s; 1045 1046 s = splnet(); 1047 1048 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1049 1050 bestop(ifp, 1); 1051 1052 ea = sc->sc_enaddr; 1053 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1054 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1055 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1056 1057 /* Clear hash table */ 1058 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1059 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1060 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1061 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1062 1063 /* Re-initialize RX configuration */ 1064 v = BE_BR_RXCFG_FIFO; 1065 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1066 1067 be_mcreset(sc); 1068 1069 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1070 1071 bus_space_write_4(t, br, 1072 BE_BRI_XIFCFG, BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1073 1074 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1075 1076 /* 1077 * Turn off counter expiration interrupts as well as 1078 * 'gotframe' and 'sentframe' 1079 */ 1080 bus_space_write_4(t, br, BE_BRI_IMASK, 1081 BE_BR_IMASK_GOTFRAME | 1082 BE_BR_IMASK_RCNTEXP | 1083 BE_BR_IMASK_ACNTEXP | 1084 BE_BR_IMASK_CCNTEXP | 1085 BE_BR_IMASK_LCNTEXP | 1086 BE_BR_IMASK_CVCNTEXP | 1087 BE_BR_IMASK_SENTFRAME | 1088 BE_BR_IMASK_NCNTEXP | 1089 BE_BR_IMASK_ECNTEXP | 1090 BE_BR_IMASK_LCCNTEXP | 1091 BE_BR_IMASK_FCNTEXP | 1092 BE_BR_IMASK_DTIMEXP); 1093 1094 /* Channel registers: */ 1095 bus_space_write_4(t, cr, BE_CRI_RXDS, (uint32_t)sc->sc_rb.rb_rxddma); 1096 bus_space_write_4(t, cr, BE_CRI_TXDS, (uint32_t)sc->sc_rb.rb_txddma); 1097 1098 qecaddr = sc->sc_channel * qec->sc_msize; 1099 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1100 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1101 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1102 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1103 1104 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1105 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1106 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1107 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1108 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1109 1110 /* Set max packet length */ 1111 v = ETHER_MAX_LEN; 1112 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1113 v += ETHER_VLAN_ENCAP_LEN; 1114 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1115 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1116 1117 /* Enable transmitter */ 1118 bus_space_write_4(t, br, 1119 BE_BRI_TXCFG, BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1120 1121 /* Enable receiver */ 1122 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1123 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1124 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1125 1126 if ((rc = be_ifmedia_upd(ifp)) != 0) 1127 goto out; 1128 1129 ifp->if_flags |= IFF_RUNNING; 1130 ifp->if_flags &= ~IFF_OACTIVE; 1131 1132 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1133 1134 return 0; 1135 out: 1136 splx(s); 1137 return rc; 1138 } 1139 1140 void 1141 be_mcreset(struct be_softc *sc) 1142 { 1143 struct ethercom *ec = &sc->sc_ethercom; 1144 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1145 bus_space_tag_t t = sc->sc_bustag; 1146 bus_space_handle_t br = sc->sc_br; 1147 uint32_t v; 1148 uint32_t crc; 1149 uint16_t hash[4]; 1150 struct ether_multi *enm; 1151 struct ether_multistep step; 1152 1153 if (ifp->if_flags & IFF_PROMISC) { 1154 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1155 v |= BE_BR_RXCFG_PMISC; 1156 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1157 return; 1158 } 1159 1160 if (ifp->if_flags & IFF_ALLMULTI) { 1161 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1162 goto chipit; 1163 } 1164 1165 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1166 1167 ETHER_FIRST_MULTI(step, ec, enm); 1168 while (enm != NULL) { 1169 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1170 /* 1171 * We must listen to a range of multicast 1172 * addresses. For now, just accept all 1173 * multicasts, rather than trying to set only 1174 * those filter bits needed to match the range. 1175 * (At this time, the only use of address 1176 * ranges is for IP multicast routing, for 1177 * which the range is big enough to require 1178 * all bits set.) 1179 */ 1180 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1181 ifp->if_flags |= IFF_ALLMULTI; 1182 goto chipit; 1183 } 1184 1185 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1186 /* Just want the 6 most significant bits. */ 1187 crc >>= 26; 1188 1189 hash[crc >> 4] |= 1 << (crc & 0xf); 1190 ETHER_NEXT_MULTI(step, enm); 1191 } 1192 1193 ifp->if_flags &= ~IFF_ALLMULTI; 1194 1195 chipit: 1196 /* Enable the hash filter */ 1197 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1198 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1199 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1200 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1201 1202 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1203 v &= ~BE_BR_RXCFG_PMISC; 1204 v |= BE_BR_RXCFG_HENABLE; 1205 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1206 } 1207 1208 /* 1209 * Set the tcvr to an idle state 1210 */ 1211 void 1212 be_mii_sync(struct be_softc *sc) 1213 { 1214 bus_space_tag_t t = sc->sc_bustag; 1215 bus_space_handle_t tr = sc->sc_tr; 1216 int n = 32; 1217 1218 while (n--) { 1219 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1220 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB); 1221 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1222 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1223 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1224 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1225 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1226 } 1227 } 1228 1229 void 1230 be_pal_gate(struct be_softc *sc, int phy) 1231 { 1232 bus_space_tag_t t = sc->sc_bustag; 1233 bus_space_handle_t tr = sc->sc_tr; 1234 uint32_t v; 1235 1236 be_mii_sync(sc); 1237 1238 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1239 if (phy == BE_PHY_INTERNAL) 1240 v &= ~TCVR_PAL_SERIAL; 1241 1242 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1243 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1244 } 1245 1246 static int 1247 be_tcvr_read_bit(struct be_softc *sc, int phy) 1248 { 1249 bus_space_tag_t t = sc->sc_bustag; 1250 bus_space_handle_t tr = sc->sc_tr; 1251 int ret; 1252 1253 if (phy == BE_PHY_INTERNAL) { 1254 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1255 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1256 bus_space_write_4(t, tr, 1257 BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1258 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1259 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1260 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1261 } else { 1262 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1263 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1264 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1265 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1266 bus_space_write_4(t, tr, 1267 BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1268 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1269 } 1270 1271 return ret; 1272 } 1273 1274 static void 1275 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1276 { 1277 bus_space_tag_t t = sc->sc_bustag; 1278 bus_space_handle_t tr = sc->sc_tr; 1279 uint32_t v; 1280 1281 if (phy == BE_PHY_INTERNAL) { 1282 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1283 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1284 } else { 1285 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) | 1286 MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1287 } 1288 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1289 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1290 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1291 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1292 } 1293 1294 static void 1295 be_mii_sendbits(struct be_softc *sc, int phy, uint32_t data, int nbits) 1296 { 1297 int i; 1298 1299 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1300 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1301 } 1302 } 1303 1304 static int 1305 be_mii_readreg(device_t self, int phy, int reg) 1306 { 1307 struct be_softc *sc = device_private(self); 1308 int val = 0, i; 1309 1310 /* 1311 * Read the PHY register by manually driving the MII control lines. 1312 */ 1313 be_mii_sync(sc); 1314 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1315 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1316 be_mii_sendbits(sc, phy, phy, 5); 1317 be_mii_sendbits(sc, phy, reg, 5); 1318 1319 (void)be_tcvr_read_bit(sc, phy); 1320 (void)be_tcvr_read_bit(sc, phy); 1321 1322 for (i = 15; i >= 0; i--) 1323 val |= (be_tcvr_read_bit(sc, phy) << i); 1324 1325 (void)be_tcvr_read_bit(sc, phy); 1326 (void)be_tcvr_read_bit(sc, phy); 1327 (void)be_tcvr_read_bit(sc, phy); 1328 1329 return val; 1330 } 1331 1332 void 1333 be_mii_writereg(device_t self, int phy, int reg, int val) 1334 { 1335 struct be_softc *sc = device_private(self); 1336 int i; 1337 1338 /* 1339 * Write the PHY register by manually driving the MII control lines. 1340 */ 1341 be_mii_sync(sc); 1342 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1343 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1344 be_mii_sendbits(sc, phy, phy, 5); 1345 be_mii_sendbits(sc, phy, reg, 5); 1346 1347 be_tcvr_write_bit(sc, phy, 1); 1348 be_tcvr_write_bit(sc, phy, 0); 1349 1350 for (i = 15; i >= 0; i--) 1351 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1352 } 1353 1354 int 1355 be_mii_reset(struct be_softc *sc, int phy) 1356 { 1357 device_t self = sc->sc_dev; 1358 int n; 1359 1360 be_mii_writereg(self, phy, MII_BMCR, BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1361 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1362 1363 for (n = 16; n >= 0; n--) { 1364 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1365 if ((bmcr & BMCR_RESET) == 0) 1366 break; 1367 DELAY(20); 1368 } 1369 if (n == 0) { 1370 aprint_error_dev(self, "bmcr reset failed\n"); 1371 return EIO; 1372 } 1373 1374 return 0; 1375 } 1376 1377 void 1378 be_tick(void *arg) 1379 { 1380 struct be_softc *sc = arg; 1381 int s = splnet(); 1382 1383 mii_tick(&sc->sc_mii); 1384 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1385 1386 splx(s); 1387 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1388 } 1389 1390 void 1391 be_mii_statchg(device_t self) 1392 { 1393 struct be_softc *sc = device_private(self); 1394 bus_space_tag_t t = sc->sc_bustag; 1395 bus_space_handle_t br = sc->sc_br; 1396 uint instance; 1397 uint32_t v; 1398 1399 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1400 #ifdef DIAGNOSTIC 1401 if (instance > 1) 1402 panic("be_mii_statchg: instance %d out of range", instance); 1403 #endif 1404 1405 /* Update duplex mode in TX configuration */ 1406 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1407 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1408 v |= BE_BR_TXCFG_FULLDPLX; 1409 else 1410 v &= ~BE_BR_TXCFG_FULLDPLX; 1411 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1412 1413 /* Change to appropriate gate in transceiver PAL */ 1414 be_pal_gate(sc, sc->sc_phys[instance]); 1415 } 1416 1417 /* 1418 * Get current media settings. 1419 */ 1420 void 1421 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1422 { 1423 struct be_softc *sc = ifp->if_softc; 1424 1425 mii_pollstat(&sc->sc_mii); 1426 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1427 1428 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1429 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1430 } 1431 1432 /* 1433 * Set media options. 1434 */ 1435 int 1436 be_ifmedia_upd(struct ifnet *ifp) 1437 { 1438 struct be_softc *sc = ifp->if_softc; 1439 int error; 1440 1441 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1442 error = 0; 1443 else if (error != 0) 1444 return error; 1445 1446 return be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG); 1447 } 1448 1449 /* 1450 * Service routine for our pseudo-MII internal transceiver. 1451 */ 1452 int 1453 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1454 { 1455 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1456 device_t self = sc->sc_dev; 1457 int bmcr, bmsr; 1458 int error; 1459 1460 switch (cmd) { 1461 case MII_POLLSTAT: 1462 /* 1463 * If we're not polling our PHY instance, just return. 1464 */ 1465 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1466 return 0; 1467 1468 break; 1469 1470 case MII_MEDIACHG: 1471 1472 /* 1473 * If the media indicates a different PHY instance, 1474 * isolate ourselves. 1475 */ 1476 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1477 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1478 be_mii_writereg(self, 1479 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1480 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1481 sc->sc_intphy_curspeed = 0; 1482 return 0; 1483 } 1484 1485 1486 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1487 return error; 1488 1489 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1490 1491 /* 1492 * Select the new mode and take out of isolation 1493 */ 1494 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1495 bmcr |= BMCR_S100; 1496 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1497 bmcr &= ~BMCR_S100; 1498 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1499 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1500 bmcr &= ~BMCR_S100; 1501 bmcr |= sc->sc_intphy_curspeed; 1502 } else { 1503 /* Keep isolated until link is up */ 1504 bmcr |= BMCR_ISO; 1505 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1506 } 1507 } 1508 1509 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1510 bmcr |= BMCR_FDX; 1511 else 1512 bmcr &= ~BMCR_FDX; 1513 1514 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1515 break; 1516 1517 case MII_TICK: 1518 /* 1519 * If we're not currently selected, just return. 1520 */ 1521 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1522 return 0; 1523 1524 /* Only used for automatic media selection */ 1525 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1526 return 0; 1527 1528 /* Is the interface even up? */ 1529 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1530 return 0; 1531 1532 /* 1533 * Check link status; if we don't have a link, try another 1534 * speed. We can't detect duplex mode, so half-duplex is 1535 * what we have to settle for. 1536 */ 1537 1538 /* Read twice in case the register is latched */ 1539 bmsr = 1540 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1541 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1542 1543 if ((bmsr & BMSR_LINK) != 0) { 1544 /* We have a carrier */ 1545 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1546 1547 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1548 bmcr = be_mii_readreg(self, 1549 BE_PHY_INTERNAL, MII_BMCR); 1550 1551 sc->sc_mii_flags |= MIIF_HAVELINK; 1552 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1553 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1554 1555 bmcr &= ~BMCR_ISO; 1556 be_mii_writereg(self, 1557 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1558 1559 printf("%s: link up at %s Mbps\n", 1560 device_xname(self), 1561 (bmcr & BMCR_S100) ? "100" : "10"); 1562 } 1563 return 0; 1564 } 1565 1566 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1567 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1568 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1569 sc->sc_intphy_curspeed = 0; 1570 printf("%s: link down\n", device_xname(self)); 1571 } 1572 1573 /* Only retry autonegotiation every 5 seconds. */ 1574 if (++sc->sc_mii_ticks < 5) 1575 return 0; 1576 1577 sc->sc_mii_ticks = 0; 1578 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1579 /* Just flip the fast speed bit */ 1580 bmcr ^= BMCR_S100; 1581 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1582 1583 break; 1584 1585 case MII_DOWN: 1586 /* Isolate this phy */ 1587 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1588 be_mii_writereg(self, 1589 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1590 return 0; 1591 } 1592 1593 /* Update the media status. */ 1594 be_intphy_status(sc); 1595 1596 /* Callback if something changed. */ 1597 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1598 (*mii->mii_statchg)(self); 1599 sc->sc_mii_active = mii->mii_media_active; 1600 } 1601 return 0; 1602 } 1603 1604 /* 1605 * Determine status of internal transceiver 1606 */ 1607 void 1608 be_intphy_status(struct be_softc *sc) 1609 { 1610 struct mii_data *mii = &sc->sc_mii; 1611 device_t self = sc->sc_dev; 1612 int media_active, media_status; 1613 int bmcr, bmsr; 1614 1615 media_status = IFM_AVALID; 1616 media_active = 0; 1617 1618 /* 1619 * Internal transceiver; do the work here. 1620 */ 1621 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1622 1623 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1624 case (BMCR_S100 | BMCR_FDX): 1625 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1626 break; 1627 case BMCR_S100: 1628 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1629 break; 1630 case BMCR_FDX: 1631 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1632 break; 1633 case 0: 1634 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1635 break; 1636 } 1637 1638 /* Read twice in case the register is latched */ 1639 bmsr = 1640 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1641 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1642 if (bmsr & BMSR_LINK) 1643 media_status |= IFM_ACTIVE; 1644 1645 mii->mii_media_status = media_status; 1646 mii->mii_media_active = media_active; 1647 } 1648
Indexes created Sat Oct 25 10:09:55 GMT 2025