be.c revision 1.65
1 /* $NetBSD: be.c,v 1.65 2009/05/12 14:43:59 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.65 2009/05/12 14:43:59 cegger Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "bpfilter.h" 65 #include "rnd.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/callout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/if_inarp.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #endif 96 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 struct device sc_dev; 118 struct sbusdev sc_sd; /* sbus device */ 119 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 120 bus_dma_tag_t sc_dmatag; 121 bus_dmamap_t sc_dmamap; 122 struct ethercom sc_ethercom; 123 /*struct ifmedia sc_ifmedia; -* interface media */ 124 struct mii_data sc_mii; /* MII media control */ 125 #define sc_media sc_mii.mii_media/* shorthand */ 126 int sc_phys[2]; /* MII instance -> phy */ 127 128 struct callout sc_tick_ch; 129 130 /* 131 * Some `mii_softc' items we need to emulate MII operation 132 * for our internal transceiver. 133 */ 134 int sc_mii_inst; /* instance of internal phy */ 135 int sc_mii_active; /* currently active medium */ 136 int sc_mii_ticks; /* tick counter */ 137 int sc_mii_flags; /* phy status flags */ 138 #define MIIF_HAVELINK 0x04000000 139 int sc_intphy_curspeed; /* Established link speed */ 140 141 struct qec_softc *sc_qec; /* QEC parent */ 142 143 bus_space_handle_t sc_qr; /* QEC registers */ 144 bus_space_handle_t sc_br; /* BE registers */ 145 bus_space_handle_t sc_cr; /* channel registers */ 146 bus_space_handle_t sc_tr; /* transceiver registers */ 147 148 u_int sc_rev; 149 150 int sc_channel; /* channel number */ 151 int sc_burst; 152 153 struct qec_ring sc_rb; /* Packet Ring Buffer */ 154 155 /* MAC address */ 156 u_int8_t sc_enaddr[6]; 157 #ifdef BEDEBUG 158 int sc_debug; 159 #endif 160 }; 161 162 int bematch(device_t, cfdata_t, void *); 163 void beattach(device_t, device_t, void *); 164 165 void beinit(struct be_softc *); 166 void bestart(struct ifnet *); 167 void bestop(struct be_softc *); 168 void bewatchdog(struct ifnet *); 169 int beioctl(struct ifnet *, u_long, void *); 170 void bereset(struct be_softc *); 171 172 int beintr(void *); 173 int berint(struct be_softc *); 174 int betint(struct be_softc *); 175 int beqint(struct be_softc *, u_int32_t); 176 int beeint(struct be_softc *, u_int32_t); 177 178 static void be_read(struct be_softc *, int, int); 179 static int be_put(struct be_softc *, int, struct mbuf *); 180 static struct mbuf *be_get(struct be_softc *, int, int); 181 182 void be_pal_gate(struct be_softc *, int); 183 184 /* ifmedia callbacks */ 185 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186 int be_ifmedia_upd(struct ifnet *); 187 188 void be_mcreset(struct be_softc *); 189 190 /* MII methods & callbacks */ 191 static int be_mii_readreg(device_t, int, int); 192 static void be_mii_writereg(device_t, int, int, int); 193 static void be_mii_statchg(device_t); 194 195 /* MII helpers */ 196 static void be_mii_sync(struct be_softc *); 197 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 198 static int be_mii_reset(struct be_softc *, int); 199 static int be_tcvr_read_bit(struct be_softc *, int); 200 static void be_tcvr_write_bit(struct be_softc *, int, int); 201 202 void be_tick(void *); 203 void be_intphy_auto(struct be_softc *); 204 void be_intphy_status(struct be_softc *); 205 int be_intphy_service(struct be_softc *, struct mii_data *, int); 206 207 208 CFATTACH_DECL(be, sizeof(struct be_softc), 209 bematch, beattach, NULL, NULL); 210 211 int 212 bematch(device_t parent, cfdata_t cf, void *aux) 213 { 214 struct sbus_attach_args *sa = aux; 215 216 return (strcmp(cf->cf_name, sa->sa_name) == 0); 217 } 218 219 void 220 beattach(device_t parent, device_t self, void *aux) 221 { 222 struct sbus_attach_args *sa = aux; 223 struct qec_softc *qec = (struct qec_softc *)parent; 224 struct be_softc *sc = (struct be_softc *)self; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct mii_data *mii = &sc->sc_mii; 227 struct mii_softc *child; 228 int node = sa->sa_node; 229 bus_dma_tag_t dmatag = sa->sa_dmatag; 230 bus_dma_segment_t seg; 231 bus_size_t size; 232 int instance; 233 int rseg, error; 234 u_int32_t v; 235 236 if (sa->sa_nreg < 3) { 237 printf("%s: only %d register sets\n", 238 device_xname(self), sa->sa_nreg); 239 return; 240 } 241 242 if (bus_space_map(sa->sa_bustag, 243 (bus_addr_t)BUS_ADDR( 244 sa->sa_reg[0].oa_space, 245 sa->sa_reg[0].oa_base), 246 (bus_size_t)sa->sa_reg[0].oa_size, 247 0, &sc->sc_cr) != 0) { 248 printf("beattach: cannot map registers\n"); 249 return; 250 } 251 252 if (bus_space_map(sa->sa_bustag, 253 (bus_addr_t)BUS_ADDR( 254 sa->sa_reg[1].oa_space, 255 sa->sa_reg[1].oa_base), 256 (bus_size_t)sa->sa_reg[1].oa_size, 257 0, &sc->sc_br) != 0) { 258 printf("beattach: cannot map registers\n"); 259 return; 260 } 261 262 if (bus_space_map(sa->sa_bustag, 263 (bus_addr_t)BUS_ADDR( 264 sa->sa_reg[2].oa_space, 265 sa->sa_reg[2].oa_base), 266 (bus_size_t)sa->sa_reg[2].oa_size, 267 0, &sc->sc_tr) != 0) { 268 printf("beattach: cannot map registers\n"); 269 return; 270 } 271 272 sc->sc_bustag = sa->sa_bustag; 273 sc->sc_qec = qec; 274 sc->sc_qr = qec->sc_regs; 275 276 sc->sc_rev = prom_getpropint(node, "board-version", -1); 277 printf(" rev %x", sc->sc_rev); 278 279 callout_init(&sc->sc_tick_ch, 0); 280 281 bestop(sc); 282 283 sc->sc_channel = prom_getpropint(node, "channel#", -1); 284 if (sc->sc_channel == -1) 285 sc->sc_channel = 0; 286 287 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 288 if (sc->sc_burst == -1) 289 sc->sc_burst = qec->sc_burst; 290 291 /* Clamp at parent's burst sizes */ 292 sc->sc_burst &= qec->sc_burst; 293 294 /* Establish interrupt handler */ 295 if (sa->sa_nintr) 296 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 297 beintr, sc); 298 299 prom_getether(node, sc->sc_enaddr); 300 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 301 302 /* 303 * Allocate descriptor ring and buffers. 304 */ 305 306 /* for now, allocate as many bufs as there are ring descriptors */ 307 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 308 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 309 310 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 311 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 312 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 313 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 314 315 /* Get a DMA handle */ 316 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 317 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 318 aprint_error_dev(self, "DMA map create error %d\n", error); 319 return; 320 } 321 322 /* Allocate DMA buffer */ 323 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 324 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 325 aprint_error_dev(self, "DMA buffer alloc error %d\n", 326 error); 327 return; 328 } 329 330 /* Map DMA memory in CPU addressable space */ 331 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 332 &sc->sc_rb.rb_membase, 333 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 334 aprint_error_dev(self, "DMA buffer map error %d\n", 335 error); 336 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 337 return; 338 } 339 340 /* Load the buffer */ 341 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 342 sc->sc_rb.rb_membase, size, NULL, 343 BUS_DMA_NOWAIT)) != 0) { 344 aprint_error_dev(self, "DMA buffer map load error %d\n", 345 error); 346 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 347 bus_dmamem_free(dmatag, &seg, rseg); 348 return; 349 } 350 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 351 352 /* 353 * Initialize our media structures and MII info. 354 */ 355 mii->mii_ifp = ifp; 356 mii->mii_readreg = be_mii_readreg; 357 mii->mii_writereg = be_mii_writereg; 358 mii->mii_statchg = be_mii_statchg; 359 360 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 361 362 /* 363 * Initialize transceiver and determine which PHY connection to use. 364 */ 365 be_mii_sync(sc); 366 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 367 368 instance = 0; 369 370 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 371 372 mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL, 373 MII_OFFSET_ANY, 0); 374 375 child = LIST_FIRST(&mii->mii_phys); 376 if (child == NULL) { 377 /* No PHY attached */ 378 ifmedia_add(&sc->sc_media, 379 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 380 0, NULL); 381 ifmedia_set(&sc->sc_media, 382 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 383 } else { 384 /* 385 * Note: we support just one PHY on the external 386 * MII connector. 387 */ 388 #ifdef DIAGNOSTIC 389 if (LIST_NEXT(child, mii_list) != NULL) { 390 aprint_error_dev(&sc->sc_dev, "spurious MII device %s attached\n", 391 device_xname(child->mii_dev)); 392 } 393 #endif 394 if (child->mii_phy != BE_PHY_EXTERNAL || 395 child->mii_inst > 0) { 396 aprint_error_dev(&sc->sc_dev, "cannot accommodate MII device %s" 397 " at phy %d, instance %d\n", 398 device_xname(child->mii_dev), 399 child->mii_phy, child->mii_inst); 400 } else { 401 sc->sc_phys[instance] = child->mii_phy; 402 } 403 404 /* 405 * XXX - we can really do the following ONLY if the 406 * phy indeed has the auto negotiation capability!! 407 */ 408 ifmedia_set(&sc->sc_media, 409 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 410 411 /* Mark our current media setting */ 412 be_pal_gate(sc, BE_PHY_EXTERNAL); 413 instance++; 414 } 415 416 } 417 418 if ((v & MGMT_PAL_INT_MDIO) != 0) { 419 /* 420 * The be internal phy looks vaguely like MII hardware, 421 * but not enough to be able to use the MII device 422 * layer. Hence, we have to take care of media selection 423 * ourselves. 424 */ 425 426 sc->sc_mii_inst = instance; 427 sc->sc_phys[instance] = BE_PHY_INTERNAL; 428 429 /* Use `ifm_data' to store BMCR bits */ 430 ifmedia_add(&sc->sc_media, 431 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 432 0, NULL); 433 ifmedia_add(&sc->sc_media, 434 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 435 BMCR_S100, NULL); 436 ifmedia_add(&sc->sc_media, 437 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 438 0, NULL); 439 440 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 441 device_xname(self)); 442 443 be_mii_reset(sc, BE_PHY_INTERNAL); 444 /* Only set default medium here if there's no external PHY */ 445 if (instance == 0) { 446 be_pal_gate(sc, BE_PHY_INTERNAL); 447 ifmedia_set(&sc->sc_media, 448 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 449 } else 450 be_mii_writereg((void *)sc, 451 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 452 } 453 454 memcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 455 ifp->if_softc = sc; 456 ifp->if_start = bestart; 457 ifp->if_ioctl = beioctl; 458 ifp->if_watchdog = bewatchdog; 459 ifp->if_flags = 460 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 461 IFQ_SET_READY(&ifp->if_snd); 462 463 /* claim 802.1q capability */ 464 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 465 466 /* Attach the interface. */ 467 if_attach(ifp); 468 ether_ifattach(ifp, sc->sc_enaddr); 469 } 470 471 472 /* 473 * Routine to copy from mbuf chain to transmit buffer in 474 * network buffer memory. 475 */ 476 static inline int 477 be_put(struct be_softc *sc, int idx, struct mbuf *m) 478 { 479 struct mbuf *n; 480 int len, tlen = 0, boff = 0; 481 void *bp; 482 483 bp = (char *)sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 484 485 for (; m; m = n) { 486 len = m->m_len; 487 if (len == 0) { 488 MFREE(m, n); 489 continue; 490 } 491 memcpy((char *)bp + boff, mtod(m, void *), len); 492 boff += len; 493 tlen += len; 494 MFREE(m, n); 495 } 496 return (tlen); 497 } 498 499 /* 500 * Pull data off an interface. 501 * Len is the length of data, with local net header stripped. 502 * We copy the data into mbufs. When full cluster sized units are present, 503 * we copy into clusters. 504 */ 505 static inline struct mbuf * 506 be_get(struct be_softc *sc, int idx, int totlen) 507 { 508 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 509 struct mbuf *m; 510 struct mbuf *top, **mp; 511 int len, pad, boff = 0; 512 void *bp; 513 514 bp = (char *)sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 515 516 MGETHDR(m, M_DONTWAIT, MT_DATA); 517 if (m == NULL) 518 return (NULL); 519 m->m_pkthdr.rcvif = ifp; 520 m->m_pkthdr.len = totlen; 521 522 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 523 m->m_data += pad; 524 len = MHLEN - pad; 525 top = NULL; 526 mp = ⊤ 527 528 while (totlen > 0) { 529 if (top) { 530 MGET(m, M_DONTWAIT, MT_DATA); 531 if (m == NULL) { 532 m_freem(top); 533 return (NULL); 534 } 535 len = MLEN; 536 } 537 if (top && totlen >= MINCLSIZE) { 538 MCLGET(m, M_DONTWAIT); 539 if (m->m_flags & M_EXT) 540 len = MCLBYTES; 541 } 542 m->m_len = len = min(totlen, len); 543 memcpy(mtod(m, void *), (char *)bp + boff, len); 544 boff += len; 545 totlen -= len; 546 *mp = m; 547 mp = &m->m_next; 548 } 549 550 return (top); 551 } 552 553 /* 554 * Pass a packet to the higher levels. 555 */ 556 static inline void 557 be_read(struct be_softc *sc, int idx, int len) 558 { 559 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 560 struct mbuf *m; 561 562 if (len <= sizeof(struct ether_header) || 563 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 564 #ifdef BEDEBUG 565 if (sc->sc_debug) 566 printf("%s: invalid packet size %d; dropping\n", 567 ifp->if_xname, len); 568 #endif 569 ifp->if_ierrors++; 570 return; 571 } 572 573 /* 574 * Pull packet off interface. 575 */ 576 m = be_get(sc, idx, len); 577 if (m == NULL) { 578 ifp->if_ierrors++; 579 return; 580 } 581 ifp->if_ipackets++; 582 583 #if NBPFILTER > 0 584 /* 585 * Check if there's a BPF listener on this interface. 586 * If so, hand off the raw packet to BPF. 587 */ 588 if (ifp->if_bpf) 589 bpf_mtap(ifp->if_bpf, m); 590 #endif 591 /* Pass the packet up. */ 592 (*ifp->if_input)(ifp, m); 593 } 594 595 /* 596 * Start output on interface. 597 * We make two assumptions here: 598 * 1) that the current priority is set to splnet _before_ this code 599 * is called *and* is returned to the appropriate priority after 600 * return 601 * 2) that the IFF_OACTIVE flag is checked before this code is called 602 * (i.e. that the output part of the interface is idle) 603 */ 604 void 605 bestart(struct ifnet *ifp) 606 { 607 struct be_softc *sc = (struct be_softc *)ifp->if_softc; 608 struct qec_xd *txd = sc->sc_rb.rb_txd; 609 struct mbuf *m; 610 unsigned int bix, len; 611 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 612 613 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 614 return; 615 616 bix = sc->sc_rb.rb_tdhead; 617 618 for (;;) { 619 IFQ_DEQUEUE(&ifp->if_snd, m); 620 if (m == 0) 621 break; 622 623 #if NBPFILTER > 0 624 /* 625 * If BPF is listening on this interface, let it see the 626 * packet before we commit it to the wire. 627 */ 628 if (ifp->if_bpf) 629 bpf_mtap(ifp->if_bpf, m); 630 #endif 631 632 /* 633 * Copy the mbuf chain into the transmit buffer. 634 */ 635 len = be_put(sc, bix, m); 636 637 /* 638 * Initialize transmit registers and start transmission 639 */ 640 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 641 (len & QEC_XD_LENGTH); 642 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 643 BE_CR_CTRL_TWAKEUP); 644 645 if (++bix == QEC_XD_RING_MAXSIZE) 646 bix = 0; 647 648 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 649 ifp->if_flags |= IFF_OACTIVE; 650 break; 651 } 652 } 653 654 sc->sc_rb.rb_tdhead = bix; 655 } 656 657 void 658 bestop(struct be_softc *sc) 659 { 660 int n; 661 bus_space_tag_t t = sc->sc_bustag; 662 bus_space_handle_t br = sc->sc_br; 663 664 callout_stop(&sc->sc_tick_ch); 665 666 /* Down the MII. */ 667 mii_down(&sc->sc_mii); 668 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 669 670 /* Stop the transmitter */ 671 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 672 for (n = 32; n > 0; n--) { 673 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 674 break; 675 DELAY(20); 676 } 677 678 /* Stop the receiver */ 679 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 680 for (n = 32; n > 0; n--) { 681 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 682 break; 683 DELAY(20); 684 } 685 } 686 687 /* 688 * Reset interface. 689 */ 690 void 691 bereset(struct be_softc *sc) 692 { 693 int s; 694 695 s = splnet(); 696 bestop(sc); 697 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 698 beinit(sc); 699 splx(s); 700 } 701 702 void 703 bewatchdog(struct ifnet *ifp) 704 { 705 struct be_softc *sc = ifp->if_softc; 706 707 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 708 ++sc->sc_ethercom.ec_if.if_oerrors; 709 710 bereset(sc); 711 } 712 713 int 714 beintr(void *v) 715 { 716 struct be_softc *sc = (struct be_softc *)v; 717 bus_space_tag_t t = sc->sc_bustag; 718 u_int32_t whyq, whyb, whyc; 719 int r = 0; 720 721 /* Read QEC status, channel status and BE status */ 722 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 723 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 724 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 725 726 if (whyq & QEC_STAT_BM) 727 r |= beeint(sc, whyb); 728 729 if (whyq & QEC_STAT_ER) 730 r |= beqint(sc, whyc); 731 732 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 733 r |= betint(sc); 734 735 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 736 r |= berint(sc); 737 738 return (r); 739 } 740 741 /* 742 * QEC Interrupt. 743 */ 744 int 745 beqint(struct be_softc *sc, u_int32_t why) 746 { 747 int r = 0, rst = 0; 748 749 if (why & BE_CR_STAT_TXIRQ) 750 r |= 1; 751 if (why & BE_CR_STAT_RXIRQ) 752 r |= 1; 753 754 if (why & BE_CR_STAT_BERROR) { 755 r |= 1; 756 rst = 1; 757 aprint_error_dev(&sc->sc_dev, "bigmac error\n"); 758 } 759 760 if (why & BE_CR_STAT_TXDERR) { 761 r |= 1; 762 rst = 1; 763 aprint_error_dev(&sc->sc_dev, "bogus tx descriptor\n"); 764 } 765 766 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 767 r |= 1; 768 rst = 1; 769 aprint_error_dev(&sc->sc_dev, "tx DMA error ( "); 770 if (why & BE_CR_STAT_TXLERR) 771 printf("Late "); 772 if (why & BE_CR_STAT_TXPERR) 773 printf("Parity "); 774 if (why & BE_CR_STAT_TXSERR) 775 printf("Generic "); 776 printf(")\n"); 777 } 778 779 if (why & BE_CR_STAT_RXDROP) { 780 r |= 1; 781 rst = 1; 782 aprint_error_dev(&sc->sc_dev, "out of rx descriptors\n"); 783 } 784 785 if (why & BE_CR_STAT_RXSMALL) { 786 r |= 1; 787 rst = 1; 788 aprint_error_dev(&sc->sc_dev, "rx descriptor too small\n"); 789 } 790 791 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 792 r |= 1; 793 rst = 1; 794 aprint_error_dev(&sc->sc_dev, "rx DMA error ( "); 795 if (why & BE_CR_STAT_RXLERR) 796 printf("Late "); 797 if (why & BE_CR_STAT_RXPERR) 798 printf("Parity "); 799 if (why & BE_CR_STAT_RXSERR) 800 printf("Generic "); 801 printf(")\n"); 802 } 803 804 if (!r) { 805 rst = 1; 806 aprint_error_dev(&sc->sc_dev, "unexpected error interrupt %08x\n", 807 why); 808 } 809 810 if (rst) { 811 printf("%s: resetting\n", device_xname(&sc->sc_dev)); 812 bereset(sc); 813 } 814 815 return (r); 816 } 817 818 /* 819 * Error interrupt. 820 */ 821 int 822 beeint(struct be_softc *sc, u_int32_t why) 823 { 824 int r = 0, rst = 0; 825 826 if (why & BE_BR_STAT_RFIFOVF) { 827 r |= 1; 828 rst = 1; 829 aprint_error_dev(&sc->sc_dev, "receive fifo overrun\n"); 830 } 831 if (why & BE_BR_STAT_TFIFO_UND) { 832 r |= 1; 833 rst = 1; 834 aprint_error_dev(&sc->sc_dev, "transmit fifo underrun\n"); 835 } 836 if (why & BE_BR_STAT_MAXPKTERR) { 837 r |= 1; 838 rst = 1; 839 aprint_error_dev(&sc->sc_dev, "max packet size error\n"); 840 } 841 842 if (!r) { 843 rst = 1; 844 aprint_error_dev(&sc->sc_dev, "unexpected error interrupt %08x\n", 845 why); 846 } 847 848 if (rst) { 849 printf("%s: resetting\n", device_xname(&sc->sc_dev)); 850 bereset(sc); 851 } 852 853 return (r); 854 } 855 856 /* 857 * Transmit interrupt. 858 */ 859 int 860 betint(struct be_softc *sc) 861 { 862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 863 bus_space_tag_t t = sc->sc_bustag; 864 bus_space_handle_t br = sc->sc_br; 865 unsigned int bix, txflags; 866 867 /* 868 * Unload collision counters 869 */ 870 ifp->if_collisions += 871 bus_space_read_4(t, br, BE_BRI_NCCNT) + 872 bus_space_read_4(t, br, BE_BRI_FCCNT) + 873 bus_space_read_4(t, br, BE_BRI_EXCNT) + 874 bus_space_read_4(t, br, BE_BRI_LTCNT); 875 876 /* 877 * the clear the hardware counters 878 */ 879 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 880 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 881 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 882 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 883 884 bix = sc->sc_rb.rb_tdtail; 885 886 for (;;) { 887 if (sc->sc_rb.rb_td_nbusy <= 0) 888 break; 889 890 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 891 892 if (txflags & QEC_XD_OWN) 893 break; 894 895 ifp->if_flags &= ~IFF_OACTIVE; 896 ifp->if_opackets++; 897 898 if (++bix == QEC_XD_RING_MAXSIZE) 899 bix = 0; 900 901 --sc->sc_rb.rb_td_nbusy; 902 } 903 904 sc->sc_rb.rb_tdtail = bix; 905 906 bestart(ifp); 907 908 if (sc->sc_rb.rb_td_nbusy == 0) 909 ifp->if_timer = 0; 910 911 return (1); 912 } 913 914 /* 915 * Receive interrupt. 916 */ 917 int 918 berint(struct be_softc *sc) 919 { 920 struct qec_xd *xd = sc->sc_rb.rb_rxd; 921 unsigned int bix, len; 922 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 923 924 bix = sc->sc_rb.rb_rdtail; 925 926 /* 927 * Process all buffers with valid data. 928 */ 929 for (;;) { 930 len = xd[bix].xd_flags; 931 if (len & QEC_XD_OWN) 932 break; 933 934 len &= QEC_XD_LENGTH; 935 be_read(sc, bix, len); 936 937 /* ... */ 938 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 939 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 940 941 if (++bix == QEC_XD_RING_MAXSIZE) 942 bix = 0; 943 } 944 945 sc->sc_rb.rb_rdtail = bix; 946 947 return (1); 948 } 949 950 int 951 beioctl(struct ifnet *ifp, u_long cmd, void *data) 952 { 953 struct be_softc *sc = ifp->if_softc; 954 struct ifaddr *ifa = (struct ifaddr *)data; 955 struct ifreq *ifr = (struct ifreq *)data; 956 int s, error = 0; 957 958 s = splnet(); 959 960 switch (cmd) { 961 case SIOCINITIFADDR: 962 ifp->if_flags |= IFF_UP; 963 beinit(sc); 964 switch (ifa->ifa_addr->sa_family) { 965 #ifdef INET 966 case AF_INET: 967 arp_ifinit(ifp, ifa); 968 break; 969 #endif /* INET */ 970 default: 971 break; 972 } 973 break; 974 975 case SIOCSIFFLAGS: 976 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 977 break; 978 /* XXX re-use ether_ioctl() */ 979 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 980 case IFF_RUNNING: 981 /* 982 * If interface is marked down and it is running, then 983 * stop it. 984 */ 985 bestop(sc); 986 ifp->if_flags &= ~IFF_RUNNING; 987 break; 988 case IFF_UP: 989 /* 990 * If interface is marked up and it is stopped, then 991 * start it. 992 */ 993 beinit(sc); 994 break; 995 default: 996 /* 997 * Reset the interface to pick up changes in any other 998 * flags that affect hardware registers. 999 */ 1000 bestop(sc); 1001 beinit(sc); 1002 break; 1003 } 1004 #ifdef BEDEBUG 1005 if (ifp->if_flags & IFF_DEBUG) 1006 sc->sc_debug = 1; 1007 else 1008 sc->sc_debug = 0; 1009 #endif 1010 break; 1011 1012 case SIOCADDMULTI: 1013 case SIOCDELMULTI: 1014 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1015 /* 1016 * Multicast list has changed; set the hardware filter 1017 * accordingly. 1018 */ 1019 if (ifp->if_flags & IFF_RUNNING) 1020 be_mcreset(sc); 1021 error = 0; 1022 } 1023 break; 1024 case SIOCGIFMEDIA: 1025 case SIOCSIFMEDIA: 1026 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1027 break; 1028 default: 1029 error = ether_ioctl(ifp, cmd, data); 1030 break; 1031 } 1032 splx(s); 1033 return (error); 1034 } 1035 1036 1037 void 1038 beinit(struct be_softc *sc) 1039 { 1040 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1041 bus_space_tag_t t = sc->sc_bustag; 1042 bus_space_handle_t br = sc->sc_br; 1043 bus_space_handle_t cr = sc->sc_cr; 1044 struct qec_softc *qec = sc->sc_qec; 1045 u_int32_t v; 1046 u_int32_t qecaddr; 1047 u_int8_t *ea; 1048 int rc, s; 1049 1050 s = splnet(); 1051 1052 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1053 1054 bestop(sc); 1055 1056 ea = sc->sc_enaddr; 1057 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1058 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1059 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1060 1061 /* Clear hash table */ 1062 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1063 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1064 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1065 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1066 1067 /* Re-initialize RX configuration */ 1068 v = BE_BR_RXCFG_FIFO; 1069 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1070 1071 be_mcreset(sc); 1072 1073 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1074 1075 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1076 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1077 1078 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1079 1080 /* 1081 * Turn off counter expiration interrupts as well as 1082 * 'gotframe' and 'sentframe' 1083 */ 1084 bus_space_write_4(t, br, BE_BRI_IMASK, 1085 BE_BR_IMASK_GOTFRAME | 1086 BE_BR_IMASK_RCNTEXP | 1087 BE_BR_IMASK_ACNTEXP | 1088 BE_BR_IMASK_CCNTEXP | 1089 BE_BR_IMASK_LCNTEXP | 1090 BE_BR_IMASK_CVCNTEXP | 1091 BE_BR_IMASK_SENTFRAME | 1092 BE_BR_IMASK_NCNTEXP | 1093 BE_BR_IMASK_ECNTEXP | 1094 BE_BR_IMASK_LCCNTEXP | 1095 BE_BR_IMASK_FCNTEXP | 1096 BE_BR_IMASK_DTIMEXP); 1097 1098 /* Channel registers: */ 1099 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1100 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1101 1102 qecaddr = sc->sc_channel * qec->sc_msize; 1103 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1104 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1105 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1106 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1107 1108 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1109 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1110 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1111 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1112 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1113 1114 /* Set max packet length */ 1115 v = ETHER_MAX_LEN; 1116 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1117 v += ETHER_VLAN_ENCAP_LEN; 1118 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1119 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1120 1121 /* Enable transmitter */ 1122 bus_space_write_4(t, br, BE_BRI_TXCFG, 1123 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1124 1125 /* Enable receiver */ 1126 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1127 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1128 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1129 1130 if ((rc = be_ifmedia_upd(ifp)) != 0) 1131 goto out; 1132 1133 ifp->if_flags |= IFF_RUNNING; 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 1136 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1137 out: 1138 splx(s); 1139 } 1140 1141 void 1142 be_mcreset(struct be_softc *sc) 1143 { 1144 struct ethercom *ec = &sc->sc_ethercom; 1145 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1146 bus_space_tag_t t = sc->sc_bustag; 1147 bus_space_handle_t br = sc->sc_br; 1148 u_int32_t crc; 1149 u_int16_t hash[4]; 1150 u_int8_t octet; 1151 u_int32_t v; 1152 int i, j; 1153 struct ether_multi *enm; 1154 struct ether_multistep step; 1155 1156 if (ifp->if_flags & IFF_PROMISC) { 1157 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1158 v |= BE_BR_RXCFG_PMISC; 1159 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1160 return; 1161 } 1162 1163 if (ifp->if_flags & IFF_ALLMULTI) { 1164 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1165 goto chipit; 1166 } 1167 1168 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1169 1170 ETHER_FIRST_MULTI(step, ec, enm); 1171 while (enm != NULL) { 1172 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1173 /* 1174 * We must listen to a range of multicast 1175 * addresses. For now, just accept all 1176 * multicasts, rather than trying to set only 1177 * those filter bits needed to match the range. 1178 * (At this time, the only use of address 1179 * ranges is for IP multicast routing, for 1180 * which the range is big enough to require 1181 * all bits set.) 1182 */ 1183 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1184 ifp->if_flags |= IFF_ALLMULTI; 1185 goto chipit; 1186 } 1187 1188 crc = 0xffffffff; 1189 1190 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1191 octet = enm->enm_addrlo[i]; 1192 1193 for (j = 0; j < 8; j++) { 1194 if ((crc & 1) ^ (octet & 1)) { 1195 crc >>= 1; 1196 crc ^= MC_POLY_LE; 1197 } 1198 else 1199 crc >>= 1; 1200 octet >>= 1; 1201 } 1202 } 1203 1204 crc >>= 26; 1205 hash[crc >> 4] |= 1 << (crc & 0xf); 1206 ETHER_NEXT_MULTI(step, enm); 1207 } 1208 1209 ifp->if_flags &= ~IFF_ALLMULTI; 1210 1211 chipit: 1212 /* Enable the hash filter */ 1213 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1214 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1215 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1216 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1217 1218 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1219 v &= ~BE_BR_RXCFG_PMISC; 1220 v |= BE_BR_RXCFG_HENABLE; 1221 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1222 } 1223 1224 /* 1225 * Set the tcvr to an idle state 1226 */ 1227 void 1228 be_mii_sync(struct be_softc *sc) 1229 { 1230 bus_space_tag_t t = sc->sc_bustag; 1231 bus_space_handle_t tr = sc->sc_tr; 1232 int n = 32; 1233 1234 while (n--) { 1235 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1236 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1237 MGMT_PAL_OENAB); 1238 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1239 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1240 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1241 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1242 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1243 } 1244 } 1245 1246 void 1247 be_pal_gate(struct be_softc *sc, int phy) 1248 { 1249 bus_space_tag_t t = sc->sc_bustag; 1250 bus_space_handle_t tr = sc->sc_tr; 1251 u_int32_t v; 1252 1253 be_mii_sync(sc); 1254 1255 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1256 if (phy == BE_PHY_INTERNAL) 1257 v &= ~TCVR_PAL_SERIAL; 1258 1259 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1260 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1261 } 1262 1263 static int 1264 be_tcvr_read_bit(struct be_softc *sc, int phy) 1265 { 1266 bus_space_tag_t t = sc->sc_bustag; 1267 bus_space_handle_t tr = sc->sc_tr; 1268 int ret; 1269 1270 if (phy == BE_PHY_INTERNAL) { 1271 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1272 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1273 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1274 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1275 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1276 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1277 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1278 } else { 1279 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1280 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1281 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1282 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1283 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1284 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1285 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1286 } 1287 1288 return (ret); 1289 } 1290 1291 static void 1292 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1293 { 1294 bus_space_tag_t t = sc->sc_bustag; 1295 bus_space_handle_t tr = sc->sc_tr; 1296 u_int32_t v; 1297 1298 if (phy == BE_PHY_INTERNAL) { 1299 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1300 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1301 } else { 1302 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1303 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1304 } 1305 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1306 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1307 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1308 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1309 } 1310 1311 static void 1312 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1313 { 1314 int i; 1315 1316 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1317 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1318 } 1319 } 1320 1321 static int 1322 be_mii_readreg(device_t self, int phy, int reg) 1323 { 1324 struct be_softc *sc = (struct be_softc *)self; 1325 int val = 0, i; 1326 1327 /* 1328 * Read the PHY register by manually driving the MII control lines. 1329 */ 1330 be_mii_sync(sc); 1331 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1332 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1333 be_mii_sendbits(sc, phy, phy, 5); 1334 be_mii_sendbits(sc, phy, reg, 5); 1335 1336 (void) be_tcvr_read_bit(sc, phy); 1337 (void) be_tcvr_read_bit(sc, phy); 1338 1339 for (i = 15; i >= 0; i--) 1340 val |= (be_tcvr_read_bit(sc, phy) << i); 1341 1342 (void) be_tcvr_read_bit(sc, phy); 1343 (void) be_tcvr_read_bit(sc, phy); 1344 (void) be_tcvr_read_bit(sc, phy); 1345 1346 return (val); 1347 } 1348 1349 void 1350 be_mii_writereg(device_t self, int phy, int reg, int val) 1351 { 1352 struct be_softc *sc = (struct be_softc *)self; 1353 int i; 1354 1355 /* 1356 * Write the PHY register by manually driving the MII control lines. 1357 */ 1358 be_mii_sync(sc); 1359 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1360 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1361 be_mii_sendbits(sc, phy, phy, 5); 1362 be_mii_sendbits(sc, phy, reg, 5); 1363 1364 be_tcvr_write_bit(sc, phy, 1); 1365 be_tcvr_write_bit(sc, phy, 0); 1366 1367 for (i = 15; i >= 0; i--) 1368 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1369 } 1370 1371 int 1372 be_mii_reset(struct be_softc *sc, int phy) 1373 { 1374 int n; 1375 1376 be_mii_writereg((device_t)sc, phy, MII_BMCR, 1377 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1378 be_mii_writereg((device_t)sc, phy, MII_BMCR, BMCR_RESET); 1379 1380 for (n = 16; n >= 0; n--) { 1381 int bmcr = be_mii_readreg((device_t)sc, phy, MII_BMCR); 1382 if ((bmcr & BMCR_RESET) == 0) 1383 break; 1384 DELAY(20); 1385 } 1386 if (n == 0) { 1387 aprint_error_dev(&sc->sc_dev, "bmcr reset failed\n"); 1388 return (EIO); 1389 } 1390 1391 return (0); 1392 } 1393 1394 void 1395 be_tick(void *arg) 1396 { 1397 struct be_softc *sc = arg; 1398 int s = splnet(); 1399 1400 mii_tick(&sc->sc_mii); 1401 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1402 1403 splx(s); 1404 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1405 } 1406 1407 void 1408 be_mii_statchg(device_t self) 1409 { 1410 struct be_softc *sc = (struct be_softc *)self; 1411 bus_space_tag_t t = sc->sc_bustag; 1412 bus_space_handle_t br = sc->sc_br; 1413 u_int instance; 1414 u_int32_t v; 1415 1416 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1417 #ifdef DIAGNOSTIC 1418 if (instance > 1) 1419 panic("be_mii_statchg: instance %d out of range", instance); 1420 #endif 1421 1422 /* Update duplex mode in TX configuration */ 1423 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1424 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1425 v |= BE_BR_TXCFG_FULLDPLX; 1426 else 1427 v &= ~BE_BR_TXCFG_FULLDPLX; 1428 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1429 1430 /* Change to appropriate gate in transceiver PAL */ 1431 be_pal_gate(sc, sc->sc_phys[instance]); 1432 } 1433 1434 /* 1435 * Get current media settings. 1436 */ 1437 void 1438 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1439 { 1440 struct be_softc *sc = ifp->if_softc; 1441 1442 mii_pollstat(&sc->sc_mii); 1443 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1444 1445 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1446 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1447 return; 1448 } 1449 1450 /* 1451 * Set media options. 1452 */ 1453 int 1454 be_ifmedia_upd(struct ifnet *ifp) 1455 { 1456 struct be_softc *sc = ifp->if_softc; 1457 int error; 1458 1459 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1460 error = 0; 1461 else if (error != 0) 1462 return error; 1463 1464 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1465 } 1466 1467 /* 1468 * Service routine for our pseudo-MII internal transceiver. 1469 */ 1470 int 1471 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1472 { 1473 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1474 int bmcr, bmsr; 1475 int error; 1476 1477 switch (cmd) { 1478 case MII_POLLSTAT: 1479 /* 1480 * If we're not polling our PHY instance, just return. 1481 */ 1482 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1483 return (0); 1484 1485 break; 1486 1487 case MII_MEDIACHG: 1488 1489 /* 1490 * If the media indicates a different PHY instance, 1491 * isolate ourselves. 1492 */ 1493 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1494 bmcr = be_mii_readreg((void *)sc, 1495 BE_PHY_INTERNAL, MII_BMCR); 1496 be_mii_writereg((void *)sc, 1497 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1498 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1499 sc->sc_intphy_curspeed = 0; 1500 return (0); 1501 } 1502 1503 1504 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1505 return (error); 1506 1507 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1508 1509 /* 1510 * Select the new mode and take out of isolation 1511 */ 1512 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1513 bmcr |= BMCR_S100; 1514 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1515 bmcr &= ~BMCR_S100; 1516 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1517 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1518 bmcr &= ~BMCR_S100; 1519 bmcr |= sc->sc_intphy_curspeed; 1520 } else { 1521 /* Keep isolated until link is up */ 1522 bmcr |= BMCR_ISO; 1523 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1524 } 1525 } 1526 1527 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1528 bmcr |= BMCR_FDX; 1529 else 1530 bmcr &= ~BMCR_FDX; 1531 1532 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1533 break; 1534 1535 case MII_TICK: 1536 /* 1537 * If we're not currently selected, just return. 1538 */ 1539 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1540 return (0); 1541 1542 /* Only used for automatic media selection */ 1543 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1544 return (0); 1545 1546 /* Is the interface even up? */ 1547 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1548 return (0); 1549 1550 /* 1551 * Check link status; if we don't have a link, try another 1552 * speed. We can't detect duplex mode, so half-duplex is 1553 * what we have to settle for. 1554 */ 1555 1556 /* Read twice in case the register is latched */ 1557 bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) | 1558 be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR); 1559 1560 if ((bmsr & BMSR_LINK) != 0) { 1561 /* We have a carrier */ 1562 bmcr = be_mii_readreg((void *)sc, 1563 BE_PHY_INTERNAL, MII_BMCR); 1564 1565 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1566 bmcr = be_mii_readreg((void *)sc, 1567 BE_PHY_INTERNAL, MII_BMCR); 1568 1569 sc->sc_mii_flags |= MIIF_HAVELINK; 1570 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1571 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1572 1573 bmcr &= ~BMCR_ISO; 1574 be_mii_writereg((void *)sc, 1575 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1576 1577 printf("%s: link up at %s Mbps\n", 1578 device_xname(&sc->sc_dev), 1579 (bmcr & BMCR_S100) ? "100" : "10"); 1580 } 1581 return (0); 1582 } 1583 1584 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1585 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1586 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1587 sc->sc_intphy_curspeed = 0; 1588 printf("%s: link down\n", device_xname(&sc->sc_dev)); 1589 } 1590 1591 /* Only retry autonegotiation every 5 seconds. */ 1592 if (++sc->sc_mii_ticks < 5) 1593 return(0); 1594 1595 sc->sc_mii_ticks = 0; 1596 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1597 /* Just flip the fast speed bit */ 1598 bmcr ^= BMCR_S100; 1599 be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1600 1601 break; 1602 1603 case MII_DOWN: 1604 /* Isolate this phy */ 1605 bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR); 1606 be_mii_writereg((void *)sc, 1607 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1608 return (0); 1609 } 1610 1611 /* Update the media status. */ 1612 be_intphy_status(sc); 1613 1614 /* Callback if something changed. */ 1615 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1616 (*mii->mii_statchg)((device_t)sc); 1617 sc->sc_mii_active = mii->mii_media_active; 1618 } 1619 return (0); 1620 } 1621 1622 /* 1623 * Determine status of internal transceiver 1624 */ 1625 void 1626 be_intphy_status(struct be_softc *sc) 1627 { 1628 struct mii_data *mii = &sc->sc_mii; 1629 int media_active, media_status; 1630 int bmcr, bmsr; 1631 1632 media_status = IFM_AVALID; 1633 media_active = 0; 1634 1635 /* 1636 * Internal transceiver; do the work here. 1637 */ 1638 bmcr = be_mii_readreg((device_t)sc, BE_PHY_INTERNAL, MII_BMCR); 1639 1640 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1641 case (BMCR_S100 | BMCR_FDX): 1642 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1643 break; 1644 case BMCR_S100: 1645 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1646 break; 1647 case BMCR_FDX: 1648 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1649 break; 1650 case 0: 1651 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1652 break; 1653 } 1654 1655 /* Read twice in case the register is latched */ 1656 bmsr = be_mii_readreg((device_t)sc, BE_PHY_INTERNAL, MII_BMSR)| 1657 be_mii_readreg((device_t)sc, BE_PHY_INTERNAL, MII_BMSR); 1658 if (bmsr & BMSR_LINK) 1659 media_status |= IFM_ACTIVE; 1660 1661 mii->mii_media_status = media_status; 1662 mii->mii_media_active = media_active; 1663 } 1664
Indexes created Tue Sep 30 11:09:46 GMT 2025