be.c revision 1.69
1 /* $NetBSD: be.c,v 1.69 2009/09/18 13:48:54 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.69 2009/09/18 13:48:54 tsutsui Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "bpfilter.h" 65 #include "rnd.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/callout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/if_inarp.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #endif 96 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 device_t sc_dev; 118 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 119 bus_dma_tag_t sc_dmatag; 120 bus_dmamap_t sc_dmamap; 121 struct ethercom sc_ethercom; 122 /*struct ifmedia sc_ifmedia; -* interface media */ 123 struct mii_data sc_mii; /* MII media control */ 124 #define sc_media sc_mii.mii_media/* shorthand */ 125 int sc_phys[2]; /* MII instance -> phy */ 126 127 struct callout sc_tick_ch; 128 129 /* 130 * Some `mii_softc' items we need to emulate MII operation 131 * for our internal transceiver. 132 */ 133 int sc_mii_inst; /* instance of internal phy */ 134 int sc_mii_active; /* currently active medium */ 135 int sc_mii_ticks; /* tick counter */ 136 int sc_mii_flags; /* phy status flags */ 137 #define MIIF_HAVELINK 0x04000000 138 int sc_intphy_curspeed; /* Established link speed */ 139 140 struct qec_softc *sc_qec; /* QEC parent */ 141 142 bus_space_handle_t sc_qr; /* QEC registers */ 143 bus_space_handle_t sc_br; /* BE registers */ 144 bus_space_handle_t sc_cr; /* channel registers */ 145 bus_space_handle_t sc_tr; /* transceiver registers */ 146 147 u_int sc_rev; 148 149 int sc_channel; /* channel number */ 150 int sc_burst; 151 152 struct qec_ring sc_rb; /* Packet Ring Buffer */ 153 154 /* MAC address */ 155 u_int8_t sc_enaddr[6]; 156 #ifdef BEDEBUG 157 int sc_debug; 158 #endif 159 }; 160 161 int bematch(device_t, cfdata_t, void *); 162 void beattach(device_t, device_t, void *); 163 164 int beinit(struct ifnet *); 165 void bestart(struct ifnet *); 166 void bestop(struct ifnet *, int); 167 void bewatchdog(struct ifnet *); 168 int beioctl(struct ifnet *, u_long, void *); 169 void bereset(struct be_softc *); 170 void behwreset(struct be_softc *); 171 172 int beintr(void *); 173 int berint(struct be_softc *); 174 int betint(struct be_softc *); 175 int beqint(struct be_softc *, u_int32_t); 176 int beeint(struct be_softc *, u_int32_t); 177 178 static void be_read(struct be_softc *, int, int); 179 static int be_put(struct be_softc *, int, struct mbuf *); 180 static struct mbuf *be_get(struct be_softc *, int, int); 181 182 void be_pal_gate(struct be_softc *, int); 183 184 /* ifmedia callbacks */ 185 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186 int be_ifmedia_upd(struct ifnet *); 187 188 void be_mcreset(struct be_softc *); 189 190 /* MII methods & callbacks */ 191 static int be_mii_readreg(device_t, int, int); 192 static void be_mii_writereg(device_t, int, int, int); 193 static void be_mii_statchg(device_t); 194 195 /* MII helpers */ 196 static void be_mii_sync(struct be_softc *); 197 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 198 static int be_mii_reset(struct be_softc *, int); 199 static int be_tcvr_read_bit(struct be_softc *, int); 200 static void be_tcvr_write_bit(struct be_softc *, int, int); 201 202 void be_tick(void *); 203 void be_intphy_auto(struct be_softc *); 204 void be_intphy_status(struct be_softc *); 205 int be_intphy_service(struct be_softc *, struct mii_data *, int); 206 207 208 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 209 bematch, beattach, NULL, NULL); 210 211 int 212 bematch(device_t parent, cfdata_t cf, void *aux) 213 { 214 struct sbus_attach_args *sa = aux; 215 216 return (strcmp(cf->cf_name, sa->sa_name) == 0); 217 } 218 219 void 220 beattach(device_t parent, device_t self, void *aux) 221 { 222 struct sbus_attach_args *sa = aux; 223 struct qec_softc *qec = device_private(parent); 224 struct be_softc *sc = device_private(self); 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct mii_data *mii = &sc->sc_mii; 227 struct mii_softc *child; 228 int node = sa->sa_node; 229 bus_dma_tag_t dmatag = sa->sa_dmatag; 230 bus_dma_segment_t seg; 231 bus_size_t size; 232 int instance; 233 int rseg, error; 234 u_int32_t v; 235 236 sc->sc_dev = self; 237 238 if (sa->sa_nreg < 3) { 239 printf("%s: only %d register sets\n", 240 device_xname(self), sa->sa_nreg); 241 return; 242 } 243 244 if (bus_space_map(sa->sa_bustag, 245 (bus_addr_t)BUS_ADDR( 246 sa->sa_reg[0].oa_space, 247 sa->sa_reg[0].oa_base), 248 (bus_size_t)sa->sa_reg[0].oa_size, 249 0, &sc->sc_cr) != 0) { 250 printf("beattach: cannot map registers\n"); 251 return; 252 } 253 254 if (bus_space_map(sa->sa_bustag, 255 (bus_addr_t)BUS_ADDR( 256 sa->sa_reg[1].oa_space, 257 sa->sa_reg[1].oa_base), 258 (bus_size_t)sa->sa_reg[1].oa_size, 259 0, &sc->sc_br) != 0) { 260 printf("beattach: cannot map registers\n"); 261 return; 262 } 263 264 if (bus_space_map(sa->sa_bustag, 265 (bus_addr_t)BUS_ADDR( 266 sa->sa_reg[2].oa_space, 267 sa->sa_reg[2].oa_base), 268 (bus_size_t)sa->sa_reg[2].oa_size, 269 0, &sc->sc_tr) != 0) { 270 printf("beattach: cannot map registers\n"); 271 return; 272 } 273 274 sc->sc_bustag = sa->sa_bustag; 275 sc->sc_qec = qec; 276 sc->sc_qr = qec->sc_regs; 277 278 sc->sc_rev = prom_getpropint(node, "board-version", -1); 279 printf(" rev %x", sc->sc_rev); 280 281 callout_init(&sc->sc_tick_ch, 0); 282 283 sc->sc_channel = prom_getpropint(node, "channel#", -1); 284 if (sc->sc_channel == -1) 285 sc->sc_channel = 0; 286 287 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 288 if (sc->sc_burst == -1) 289 sc->sc_burst = qec->sc_burst; 290 291 /* Clamp at parent's burst sizes */ 292 sc->sc_burst &= qec->sc_burst; 293 294 /* Establish interrupt handler */ 295 if (sa->sa_nintr) 296 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 297 beintr, sc); 298 299 prom_getether(node, sc->sc_enaddr); 300 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 301 302 /* 303 * Allocate descriptor ring and buffers. 304 */ 305 306 /* for now, allocate as many bufs as there are ring descriptors */ 307 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 308 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 309 310 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 311 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 312 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 313 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 314 315 /* Get a DMA handle */ 316 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 317 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 318 aprint_error_dev(self, "DMA map create error %d\n", error); 319 return; 320 } 321 322 /* Allocate DMA buffer */ 323 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 324 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 325 aprint_error_dev(self, "DMA buffer alloc error %d\n", 326 error); 327 return; 328 } 329 330 /* Map DMA memory in CPU addressable space */ 331 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 332 &sc->sc_rb.rb_membase, 333 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 334 aprint_error_dev(self, "DMA buffer map error %d\n", 335 error); 336 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 337 return; 338 } 339 340 /* Load the buffer */ 341 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 342 sc->sc_rb.rb_membase, size, NULL, 343 BUS_DMA_NOWAIT)) != 0) { 344 aprint_error_dev(self, "DMA buffer map load error %d\n", 345 error); 346 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 347 bus_dmamem_free(dmatag, &seg, rseg); 348 return; 349 } 350 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 351 352 /* 353 * Initialize our media structures and MII info. 354 */ 355 mii->mii_ifp = ifp; 356 mii->mii_readreg = be_mii_readreg; 357 mii->mii_writereg = be_mii_writereg; 358 mii->mii_statchg = be_mii_statchg; 359 360 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 361 362 /* 363 * Initialize transceiver and determine which PHY connection to use. 364 */ 365 be_mii_sync(sc); 366 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 367 368 instance = 0; 369 370 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 371 372 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 373 MII_OFFSET_ANY, 0); 374 375 child = LIST_FIRST(&mii->mii_phys); 376 if (child == NULL) { 377 /* No PHY attached */ 378 ifmedia_add(&sc->sc_media, 379 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 380 0, NULL); 381 ifmedia_set(&sc->sc_media, 382 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 383 } else { 384 /* 385 * Note: we support just one PHY on the external 386 * MII connector. 387 */ 388 #ifdef DIAGNOSTIC 389 if (LIST_NEXT(child, mii_list) != NULL) { 390 aprint_error_dev(self, 391 "spurious MII device %s attached\n", 392 device_xname(child->mii_dev)); 393 } 394 #endif 395 if (child->mii_phy != BE_PHY_EXTERNAL || 396 child->mii_inst > 0) { 397 aprint_error_dev(self, 398 "cannot accommodate MII device %s" 399 " at phy %d, instance %d\n", 400 device_xname(child->mii_dev), 401 child->mii_phy, child->mii_inst); 402 } else { 403 sc->sc_phys[instance] = child->mii_phy; 404 } 405 406 /* 407 * XXX - we can really do the following ONLY if the 408 * phy indeed has the auto negotiation capability!! 409 */ 410 ifmedia_set(&sc->sc_media, 411 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 412 413 /* Mark our current media setting */ 414 be_pal_gate(sc, BE_PHY_EXTERNAL); 415 instance++; 416 } 417 418 } 419 420 if ((v & MGMT_PAL_INT_MDIO) != 0) { 421 /* 422 * The be internal phy looks vaguely like MII hardware, 423 * but not enough to be able to use the MII device 424 * layer. Hence, we have to take care of media selection 425 * ourselves. 426 */ 427 428 sc->sc_mii_inst = instance; 429 sc->sc_phys[instance] = BE_PHY_INTERNAL; 430 431 /* Use `ifm_data' to store BMCR bits */ 432 ifmedia_add(&sc->sc_media, 433 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 434 0, NULL); 435 ifmedia_add(&sc->sc_media, 436 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 437 BMCR_S100, NULL); 438 ifmedia_add(&sc->sc_media, 439 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 440 0, NULL); 441 442 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 443 device_xname(self)); 444 445 be_mii_reset(sc, BE_PHY_INTERNAL); 446 /* Only set default medium here if there's no external PHY */ 447 if (instance == 0) { 448 be_pal_gate(sc, BE_PHY_INTERNAL); 449 ifmedia_set(&sc->sc_media, 450 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 451 } else 452 be_mii_writereg(self, 453 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 454 } 455 456 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 457 ifp->if_softc = sc; 458 ifp->if_start = bestart; 459 ifp->if_ioctl = beioctl; 460 ifp->if_watchdog = bewatchdog; 461 ifp->if_init = beinit; 462 ifp->if_stop = bestop; 463 ifp->if_flags = 464 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 465 IFQ_SET_READY(&ifp->if_snd); 466 467 /* claim 802.1q capability */ 468 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 469 470 /* Attach the interface. */ 471 if_attach(ifp); 472 ether_ifattach(ifp, sc->sc_enaddr); 473 } 474 475 476 /* 477 * Routine to copy from mbuf chain to transmit buffer in 478 * network buffer memory. 479 */ 480 static inline int 481 be_put(struct be_softc *sc, int idx, struct mbuf *m) 482 { 483 struct mbuf *n; 484 int len, tlen = 0, boff = 0; 485 void *bp; 486 487 bp = (char *)sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 488 489 for (; m; m = n) { 490 len = m->m_len; 491 if (len == 0) { 492 MFREE(m, n); 493 continue; 494 } 495 memcpy((char *)bp + boff, mtod(m, void *), len); 496 boff += len; 497 tlen += len; 498 MFREE(m, n); 499 } 500 return (tlen); 501 } 502 503 /* 504 * Pull data off an interface. 505 * Len is the length of data, with local net header stripped. 506 * We copy the data into mbufs. When full cluster sized units are present, 507 * we copy into clusters. 508 */ 509 static inline struct mbuf * 510 be_get(struct be_softc *sc, int idx, int totlen) 511 { 512 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 513 struct mbuf *m; 514 struct mbuf *top, **mp; 515 int len, pad, boff = 0; 516 void *bp; 517 518 bp = (char *)sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 519 520 MGETHDR(m, M_DONTWAIT, MT_DATA); 521 if (m == NULL) 522 return (NULL); 523 m->m_pkthdr.rcvif = ifp; 524 m->m_pkthdr.len = totlen; 525 526 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 527 m->m_data += pad; 528 len = MHLEN - pad; 529 top = NULL; 530 mp = ⊤ 531 532 while (totlen > 0) { 533 if (top) { 534 MGET(m, M_DONTWAIT, MT_DATA); 535 if (m == NULL) { 536 m_freem(top); 537 return (NULL); 538 } 539 len = MLEN; 540 } 541 if (top && totlen >= MINCLSIZE) { 542 MCLGET(m, M_DONTWAIT); 543 if (m->m_flags & M_EXT) 544 len = MCLBYTES; 545 } 546 m->m_len = len = min(totlen, len); 547 memcpy(mtod(m, void *), (char *)bp + boff, len); 548 boff += len; 549 totlen -= len; 550 *mp = m; 551 mp = &m->m_next; 552 } 553 554 return (top); 555 } 556 557 /* 558 * Pass a packet to the higher levels. 559 */ 560 static inline void 561 be_read(struct be_softc *sc, int idx, int len) 562 { 563 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 564 struct mbuf *m; 565 566 if (len <= sizeof(struct ether_header) || 567 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 568 #ifdef BEDEBUG 569 if (sc->sc_debug) 570 printf("%s: invalid packet size %d; dropping\n", 571 ifp->if_xname, len); 572 #endif 573 ifp->if_ierrors++; 574 return; 575 } 576 577 /* 578 * Pull packet off interface. 579 */ 580 m = be_get(sc, idx, len); 581 if (m == NULL) { 582 ifp->if_ierrors++; 583 return; 584 } 585 ifp->if_ipackets++; 586 587 #if NBPFILTER > 0 588 /* 589 * Check if there's a BPF listener on this interface. 590 * If so, hand off the raw packet to BPF. 591 */ 592 if (ifp->if_bpf) 593 bpf_mtap(ifp->if_bpf, m); 594 #endif 595 /* Pass the packet up. */ 596 (*ifp->if_input)(ifp, m); 597 } 598 599 /* 600 * Start output on interface. 601 * We make two assumptions here: 602 * 1) that the current priority is set to splnet _before_ this code 603 * is called *and* is returned to the appropriate priority after 604 * return 605 * 2) that the IFF_OACTIVE flag is checked before this code is called 606 * (i.e. that the output part of the interface is idle) 607 */ 608 void 609 bestart(struct ifnet *ifp) 610 { 611 struct be_softc *sc = ifp->if_softc; 612 struct qec_xd *txd = sc->sc_rb.rb_txd; 613 struct mbuf *m; 614 unsigned int bix, len; 615 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 616 617 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 618 return; 619 620 bix = sc->sc_rb.rb_tdhead; 621 622 for (;;) { 623 IFQ_DEQUEUE(&ifp->if_snd, m); 624 if (m == 0) 625 break; 626 627 #if NBPFILTER > 0 628 /* 629 * If BPF is listening on this interface, let it see the 630 * packet before we commit it to the wire. 631 */ 632 if (ifp->if_bpf) 633 bpf_mtap(ifp->if_bpf, m); 634 #endif 635 636 /* 637 * Copy the mbuf chain into the transmit buffer. 638 */ 639 len = be_put(sc, bix, m); 640 641 /* 642 * Initialize transmit registers and start transmission 643 */ 644 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 645 (len & QEC_XD_LENGTH); 646 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 647 BE_CR_CTRL_TWAKEUP); 648 649 if (++bix == QEC_XD_RING_MAXSIZE) 650 bix = 0; 651 652 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 653 ifp->if_flags |= IFF_OACTIVE; 654 break; 655 } 656 } 657 658 sc->sc_rb.rb_tdhead = bix; 659 } 660 661 void 662 bestop(struct ifnet *ifp, int disable) 663 { 664 struct be_softc *sc = ifp->if_softc; 665 666 callout_stop(&sc->sc_tick_ch); 667 668 /* Down the MII. */ 669 mii_down(&sc->sc_mii); 670 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 671 672 behwreset(sc); 673 } 674 675 void 676 behwreset(struct be_softc *sc) 677 { 678 int n; 679 bus_space_tag_t t = sc->sc_bustag; 680 bus_space_handle_t br = sc->sc_br; 681 682 /* Stop the transmitter */ 683 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 684 for (n = 32; n > 0; n--) { 685 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 686 break; 687 DELAY(20); 688 } 689 690 /* Stop the receiver */ 691 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 692 for (n = 32; n > 0; n--) { 693 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 694 break; 695 DELAY(20); 696 } 697 } 698 699 /* 700 * Reset interface. 701 */ 702 void 703 bereset(struct be_softc *sc) 704 { 705 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 706 int s; 707 708 s = splnet(); 709 behwreset(sc); 710 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 711 beinit(ifp); 712 splx(s); 713 } 714 715 void 716 bewatchdog(struct ifnet *ifp) 717 { 718 struct be_softc *sc = ifp->if_softc; 719 720 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 721 ++sc->sc_ethercom.ec_if.if_oerrors; 722 723 bereset(sc); 724 } 725 726 int 727 beintr(void *arg) 728 { 729 struct be_softc *sc = arg; 730 bus_space_tag_t t = sc->sc_bustag; 731 u_int32_t whyq, whyb, whyc; 732 int r = 0; 733 734 /* Read QEC status, channel status and BE status */ 735 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 736 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 737 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 738 739 if (whyq & QEC_STAT_BM) 740 r |= beeint(sc, whyb); 741 742 if (whyq & QEC_STAT_ER) 743 r |= beqint(sc, whyc); 744 745 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 746 r |= betint(sc); 747 748 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 749 r |= berint(sc); 750 751 return (r); 752 } 753 754 /* 755 * QEC Interrupt. 756 */ 757 int 758 beqint(struct be_softc *sc, u_int32_t why) 759 { 760 device_t self = sc->sc_dev; 761 int r = 0, rst = 0; 762 763 if (why & BE_CR_STAT_TXIRQ) 764 r |= 1; 765 if (why & BE_CR_STAT_RXIRQ) 766 r |= 1; 767 768 if (why & BE_CR_STAT_BERROR) { 769 r |= 1; 770 rst = 1; 771 aprint_error_dev(self, "bigmac error\n"); 772 } 773 774 if (why & BE_CR_STAT_TXDERR) { 775 r |= 1; 776 rst = 1; 777 aprint_error_dev(self, "bogus tx descriptor\n"); 778 } 779 780 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 781 r |= 1; 782 rst = 1; 783 aprint_error_dev(self, "tx DMA error ( "); 784 if (why & BE_CR_STAT_TXLERR) 785 printf("Late "); 786 if (why & BE_CR_STAT_TXPERR) 787 printf("Parity "); 788 if (why & BE_CR_STAT_TXSERR) 789 printf("Generic "); 790 printf(")\n"); 791 } 792 793 if (why & BE_CR_STAT_RXDROP) { 794 r |= 1; 795 rst = 1; 796 aprint_error_dev(self, "out of rx descriptors\n"); 797 } 798 799 if (why & BE_CR_STAT_RXSMALL) { 800 r |= 1; 801 rst = 1; 802 aprint_error_dev(self, "rx descriptor too small\n"); 803 } 804 805 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 806 r |= 1; 807 rst = 1; 808 aprint_error_dev(self, "rx DMA error ( "); 809 if (why & BE_CR_STAT_RXLERR) 810 printf("Late "); 811 if (why & BE_CR_STAT_RXPERR) 812 printf("Parity "); 813 if (why & BE_CR_STAT_RXSERR) 814 printf("Generic "); 815 printf(")\n"); 816 } 817 818 if (!r) { 819 rst = 1; 820 aprint_error_dev(self, "unexpected error interrupt %08x\n", 821 why); 822 } 823 824 if (rst) { 825 printf("%s: resetting\n", device_xname(self)); 826 bereset(sc); 827 } 828 829 return (r); 830 } 831 832 /* 833 * Error interrupt. 834 */ 835 int 836 beeint(struct be_softc *sc, u_int32_t why) 837 { 838 device_t self = sc->sc_dev; 839 int r = 0, rst = 0; 840 841 if (why & BE_BR_STAT_RFIFOVF) { 842 r |= 1; 843 rst = 1; 844 aprint_error_dev(self, "receive fifo overrun\n"); 845 } 846 if (why & BE_BR_STAT_TFIFO_UND) { 847 r |= 1; 848 rst = 1; 849 aprint_error_dev(self, "transmit fifo underrun\n"); 850 } 851 if (why & BE_BR_STAT_MAXPKTERR) { 852 r |= 1; 853 rst = 1; 854 aprint_error_dev(self, "max packet size error\n"); 855 } 856 857 if (!r) { 858 rst = 1; 859 aprint_error_dev(self, "unexpected error interrupt %08x\n", 860 why); 861 } 862 863 if (rst) { 864 printf("%s: resetting\n", device_xname(self)); 865 bereset(sc); 866 } 867 868 return (r); 869 } 870 871 /* 872 * Transmit interrupt. 873 */ 874 int 875 betint(struct be_softc *sc) 876 { 877 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 878 bus_space_tag_t t = sc->sc_bustag; 879 bus_space_handle_t br = sc->sc_br; 880 unsigned int bix, txflags; 881 882 /* 883 * Unload collision counters 884 */ 885 ifp->if_collisions += 886 bus_space_read_4(t, br, BE_BRI_NCCNT) + 887 bus_space_read_4(t, br, BE_BRI_FCCNT) + 888 bus_space_read_4(t, br, BE_BRI_EXCNT) + 889 bus_space_read_4(t, br, BE_BRI_LTCNT); 890 891 /* 892 * the clear the hardware counters 893 */ 894 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 895 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 896 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 897 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 898 899 bix = sc->sc_rb.rb_tdtail; 900 901 for (;;) { 902 if (sc->sc_rb.rb_td_nbusy <= 0) 903 break; 904 905 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 906 907 if (txflags & QEC_XD_OWN) 908 break; 909 910 ifp->if_flags &= ~IFF_OACTIVE; 911 ifp->if_opackets++; 912 913 if (++bix == QEC_XD_RING_MAXSIZE) 914 bix = 0; 915 916 --sc->sc_rb.rb_td_nbusy; 917 } 918 919 sc->sc_rb.rb_tdtail = bix; 920 921 bestart(ifp); 922 923 if (sc->sc_rb.rb_td_nbusy == 0) 924 ifp->if_timer = 0; 925 926 return (1); 927 } 928 929 /* 930 * Receive interrupt. 931 */ 932 int 933 berint(struct be_softc *sc) 934 { 935 struct qec_xd *xd = sc->sc_rb.rb_rxd; 936 unsigned int bix, len; 937 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 938 939 bix = sc->sc_rb.rb_rdtail; 940 941 /* 942 * Process all buffers with valid data. 943 */ 944 for (;;) { 945 len = xd[bix].xd_flags; 946 if (len & QEC_XD_OWN) 947 break; 948 949 len &= QEC_XD_LENGTH; 950 be_read(sc, bix, len); 951 952 /* ... */ 953 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 954 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 955 956 if (++bix == QEC_XD_RING_MAXSIZE) 957 bix = 0; 958 } 959 960 sc->sc_rb.rb_rdtail = bix; 961 962 return (1); 963 } 964 965 int 966 beioctl(struct ifnet *ifp, u_long cmd, void *data) 967 { 968 struct be_softc *sc = ifp->if_softc; 969 struct ifaddr *ifa = data; 970 struct ifreq *ifr = data; 971 int s, error = 0; 972 973 s = splnet(); 974 975 switch (cmd) { 976 case SIOCINITIFADDR: 977 ifp->if_flags |= IFF_UP; 978 beinit(ifp); 979 switch (ifa->ifa_addr->sa_family) { 980 #ifdef INET 981 case AF_INET: 982 arp_ifinit(ifp, ifa); 983 break; 984 #endif /* INET */ 985 default: 986 break; 987 } 988 break; 989 990 case SIOCSIFFLAGS: 991 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 992 break; 993 /* XXX re-use ether_ioctl() */ 994 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 995 case IFF_RUNNING: 996 /* 997 * If interface is marked down and it is running, then 998 * stop it. 999 */ 1000 bestop(ifp, 0); 1001 ifp->if_flags &= ~IFF_RUNNING; 1002 break; 1003 case IFF_UP: 1004 /* 1005 * If interface is marked up and it is stopped, then 1006 * start it. 1007 */ 1008 beinit(ifp); 1009 break; 1010 default: 1011 /* 1012 * Reset the interface to pick up changes in any other 1013 * flags that affect hardware registers. 1014 */ 1015 bestop(ifp, 0); 1016 beinit(ifp); 1017 break; 1018 } 1019 #ifdef BEDEBUG 1020 if (ifp->if_flags & IFF_DEBUG) 1021 sc->sc_debug = 1; 1022 else 1023 sc->sc_debug = 0; 1024 #endif 1025 break; 1026 1027 case SIOCGIFMEDIA: 1028 case SIOCSIFMEDIA: 1029 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1030 break; 1031 default: 1032 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1033 /* 1034 * Multicast list has changed; set the hardware filter 1035 * accordingly. 1036 */ 1037 if (ifp->if_flags & IFF_RUNNING) 1038 error = beinit(ifp); 1039 else 1040 error = 0; 1041 } 1042 break; 1043 } 1044 splx(s); 1045 return (error); 1046 } 1047 1048 1049 int 1050 beinit(struct ifnet *ifp) 1051 { 1052 struct be_softc *sc = ifp->if_softc; 1053 bus_space_tag_t t = sc->sc_bustag; 1054 bus_space_handle_t br = sc->sc_br; 1055 bus_space_handle_t cr = sc->sc_cr; 1056 struct qec_softc *qec = sc->sc_qec; 1057 u_int32_t v; 1058 u_int32_t qecaddr; 1059 u_int8_t *ea; 1060 int rc, s; 1061 1062 s = splnet(); 1063 1064 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1065 1066 bestop(ifp, 1); 1067 1068 ea = sc->sc_enaddr; 1069 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1070 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1071 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1072 1073 /* Clear hash table */ 1074 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1075 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1076 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1077 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1078 1079 /* Re-initialize RX configuration */ 1080 v = BE_BR_RXCFG_FIFO; 1081 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1082 1083 be_mcreset(sc); 1084 1085 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1086 1087 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1088 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1089 1090 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1091 1092 /* 1093 * Turn off counter expiration interrupts as well as 1094 * 'gotframe' and 'sentframe' 1095 */ 1096 bus_space_write_4(t, br, BE_BRI_IMASK, 1097 BE_BR_IMASK_GOTFRAME | 1098 BE_BR_IMASK_RCNTEXP | 1099 BE_BR_IMASK_ACNTEXP | 1100 BE_BR_IMASK_CCNTEXP | 1101 BE_BR_IMASK_LCNTEXP | 1102 BE_BR_IMASK_CVCNTEXP | 1103 BE_BR_IMASK_SENTFRAME | 1104 BE_BR_IMASK_NCNTEXP | 1105 BE_BR_IMASK_ECNTEXP | 1106 BE_BR_IMASK_LCCNTEXP | 1107 BE_BR_IMASK_FCNTEXP | 1108 BE_BR_IMASK_DTIMEXP); 1109 1110 /* Channel registers: */ 1111 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1112 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1113 1114 qecaddr = sc->sc_channel * qec->sc_msize; 1115 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1116 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1117 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1118 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1119 1120 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1121 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1122 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1123 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1124 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1125 1126 /* Set max packet length */ 1127 v = ETHER_MAX_LEN; 1128 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1129 v += ETHER_VLAN_ENCAP_LEN; 1130 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1131 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1132 1133 /* Enable transmitter */ 1134 bus_space_write_4(t, br, BE_BRI_TXCFG, 1135 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1136 1137 /* Enable receiver */ 1138 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1139 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1140 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1141 1142 if ((rc = be_ifmedia_upd(ifp)) != 0) 1143 goto out; 1144 1145 ifp->if_flags |= IFF_RUNNING; 1146 ifp->if_flags &= ~IFF_OACTIVE; 1147 1148 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1149 1150 return 0; 1151 out: 1152 splx(s); 1153 return rc; 1154 } 1155 1156 void 1157 be_mcreset(struct be_softc *sc) 1158 { 1159 struct ethercom *ec = &sc->sc_ethercom; 1160 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1161 bus_space_tag_t t = sc->sc_bustag; 1162 bus_space_handle_t br = sc->sc_br; 1163 u_int32_t crc; 1164 u_int16_t hash[4]; 1165 u_int8_t octet; 1166 u_int32_t v; 1167 int i, j; 1168 struct ether_multi *enm; 1169 struct ether_multistep step; 1170 1171 if (ifp->if_flags & IFF_PROMISC) { 1172 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1173 v |= BE_BR_RXCFG_PMISC; 1174 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1175 return; 1176 } 1177 1178 if (ifp->if_flags & IFF_ALLMULTI) { 1179 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1180 goto chipit; 1181 } 1182 1183 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1184 1185 ETHER_FIRST_MULTI(step, ec, enm); 1186 while (enm != NULL) { 1187 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1188 /* 1189 * We must listen to a range of multicast 1190 * addresses. For now, just accept all 1191 * multicasts, rather than trying to set only 1192 * those filter bits needed to match the range. 1193 * (At this time, the only use of address 1194 * ranges is for IP multicast routing, for 1195 * which the range is big enough to require 1196 * all bits set.) 1197 */ 1198 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1199 ifp->if_flags |= IFF_ALLMULTI; 1200 goto chipit; 1201 } 1202 1203 crc = 0xffffffff; 1204 1205 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1206 octet = enm->enm_addrlo[i]; 1207 1208 for (j = 0; j < 8; j++) { 1209 if ((crc & 1) ^ (octet & 1)) { 1210 crc >>= 1; 1211 crc ^= MC_POLY_LE; 1212 } 1213 else 1214 crc >>= 1; 1215 octet >>= 1; 1216 } 1217 } 1218 1219 crc >>= 26; 1220 hash[crc >> 4] |= 1 << (crc & 0xf); 1221 ETHER_NEXT_MULTI(step, enm); 1222 } 1223 1224 ifp->if_flags &= ~IFF_ALLMULTI; 1225 1226 chipit: 1227 /* Enable the hash filter */ 1228 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1229 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1230 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1231 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1232 1233 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1234 v &= ~BE_BR_RXCFG_PMISC; 1235 v |= BE_BR_RXCFG_HENABLE; 1236 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1237 } 1238 1239 /* 1240 * Set the tcvr to an idle state 1241 */ 1242 void 1243 be_mii_sync(struct be_softc *sc) 1244 { 1245 bus_space_tag_t t = sc->sc_bustag; 1246 bus_space_handle_t tr = sc->sc_tr; 1247 int n = 32; 1248 1249 while (n--) { 1250 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1251 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1252 MGMT_PAL_OENAB); 1253 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1254 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1255 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1256 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1257 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1258 } 1259 } 1260 1261 void 1262 be_pal_gate(struct be_softc *sc, int phy) 1263 { 1264 bus_space_tag_t t = sc->sc_bustag; 1265 bus_space_handle_t tr = sc->sc_tr; 1266 u_int32_t v; 1267 1268 be_mii_sync(sc); 1269 1270 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1271 if (phy == BE_PHY_INTERNAL) 1272 v &= ~TCVR_PAL_SERIAL; 1273 1274 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1275 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1276 } 1277 1278 static int 1279 be_tcvr_read_bit(struct be_softc *sc, int phy) 1280 { 1281 bus_space_tag_t t = sc->sc_bustag; 1282 bus_space_handle_t tr = sc->sc_tr; 1283 int ret; 1284 1285 if (phy == BE_PHY_INTERNAL) { 1286 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1287 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1288 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1289 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1290 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1291 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1292 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1293 } else { 1294 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1295 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1296 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1297 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1298 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1299 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1300 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1301 } 1302 1303 return (ret); 1304 } 1305 1306 static void 1307 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1308 { 1309 bus_space_tag_t t = sc->sc_bustag; 1310 bus_space_handle_t tr = sc->sc_tr; 1311 u_int32_t v; 1312 1313 if (phy == BE_PHY_INTERNAL) { 1314 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1315 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1316 } else { 1317 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1318 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1319 } 1320 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1321 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1322 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1323 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1324 } 1325 1326 static void 1327 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1328 { 1329 int i; 1330 1331 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1332 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1333 } 1334 } 1335 1336 static int 1337 be_mii_readreg(device_t self, int phy, int reg) 1338 { 1339 struct be_softc *sc = device_private(self); 1340 int val = 0, i; 1341 1342 /* 1343 * Read the PHY register by manually driving the MII control lines. 1344 */ 1345 be_mii_sync(sc); 1346 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1347 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1348 be_mii_sendbits(sc, phy, phy, 5); 1349 be_mii_sendbits(sc, phy, reg, 5); 1350 1351 (void) be_tcvr_read_bit(sc, phy); 1352 (void) be_tcvr_read_bit(sc, phy); 1353 1354 for (i = 15; i >= 0; i--) 1355 val |= (be_tcvr_read_bit(sc, phy) << i); 1356 1357 (void) be_tcvr_read_bit(sc, phy); 1358 (void) be_tcvr_read_bit(sc, phy); 1359 (void) be_tcvr_read_bit(sc, phy); 1360 1361 return (val); 1362 } 1363 1364 void 1365 be_mii_writereg(device_t self, int phy, int reg, int val) 1366 { 1367 struct be_softc *sc = device_private(self); 1368 int i; 1369 1370 /* 1371 * Write the PHY register by manually driving the MII control lines. 1372 */ 1373 be_mii_sync(sc); 1374 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1375 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1376 be_mii_sendbits(sc, phy, phy, 5); 1377 be_mii_sendbits(sc, phy, reg, 5); 1378 1379 be_tcvr_write_bit(sc, phy, 1); 1380 be_tcvr_write_bit(sc, phy, 0); 1381 1382 for (i = 15; i >= 0; i--) 1383 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1384 } 1385 1386 int 1387 be_mii_reset(struct be_softc *sc, int phy) 1388 { 1389 device_t self = sc->sc_dev; 1390 int n; 1391 1392 be_mii_writereg(self, phy, MII_BMCR, 1393 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1394 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1395 1396 for (n = 16; n >= 0; n--) { 1397 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1398 if ((bmcr & BMCR_RESET) == 0) 1399 break; 1400 DELAY(20); 1401 } 1402 if (n == 0) { 1403 aprint_error_dev(self, "bmcr reset failed\n"); 1404 return (EIO); 1405 } 1406 1407 return (0); 1408 } 1409 1410 void 1411 be_tick(void *arg) 1412 { 1413 struct be_softc *sc = arg; 1414 int s = splnet(); 1415 1416 mii_tick(&sc->sc_mii); 1417 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1418 1419 splx(s); 1420 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1421 } 1422 1423 void 1424 be_mii_statchg(device_t self) 1425 { 1426 struct be_softc *sc = device_private(self); 1427 bus_space_tag_t t = sc->sc_bustag; 1428 bus_space_handle_t br = sc->sc_br; 1429 u_int instance; 1430 u_int32_t v; 1431 1432 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1433 #ifdef DIAGNOSTIC 1434 if (instance > 1) 1435 panic("be_mii_statchg: instance %d out of range", instance); 1436 #endif 1437 1438 /* Update duplex mode in TX configuration */ 1439 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1440 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1441 v |= BE_BR_TXCFG_FULLDPLX; 1442 else 1443 v &= ~BE_BR_TXCFG_FULLDPLX; 1444 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1445 1446 /* Change to appropriate gate in transceiver PAL */ 1447 be_pal_gate(sc, sc->sc_phys[instance]); 1448 } 1449 1450 /* 1451 * Get current media settings. 1452 */ 1453 void 1454 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1455 { 1456 struct be_softc *sc = ifp->if_softc; 1457 1458 mii_pollstat(&sc->sc_mii); 1459 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1460 1461 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1462 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1463 return; 1464 } 1465 1466 /* 1467 * Set media options. 1468 */ 1469 int 1470 be_ifmedia_upd(struct ifnet *ifp) 1471 { 1472 struct be_softc *sc = ifp->if_softc; 1473 int error; 1474 1475 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1476 error = 0; 1477 else if (error != 0) 1478 return error; 1479 1480 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1481 } 1482 1483 /* 1484 * Service routine for our pseudo-MII internal transceiver. 1485 */ 1486 int 1487 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1488 { 1489 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1490 device_t self = sc->sc_dev; 1491 int bmcr, bmsr; 1492 int error; 1493 1494 switch (cmd) { 1495 case MII_POLLSTAT: 1496 /* 1497 * If we're not polling our PHY instance, just return. 1498 */ 1499 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1500 return (0); 1501 1502 break; 1503 1504 case MII_MEDIACHG: 1505 1506 /* 1507 * If the media indicates a different PHY instance, 1508 * isolate ourselves. 1509 */ 1510 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1511 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1512 be_mii_writereg(self, 1513 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1514 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1515 sc->sc_intphy_curspeed = 0; 1516 return (0); 1517 } 1518 1519 1520 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1521 return (error); 1522 1523 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1524 1525 /* 1526 * Select the new mode and take out of isolation 1527 */ 1528 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1529 bmcr |= BMCR_S100; 1530 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1531 bmcr &= ~BMCR_S100; 1532 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1533 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1534 bmcr &= ~BMCR_S100; 1535 bmcr |= sc->sc_intphy_curspeed; 1536 } else { 1537 /* Keep isolated until link is up */ 1538 bmcr |= BMCR_ISO; 1539 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1540 } 1541 } 1542 1543 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1544 bmcr |= BMCR_FDX; 1545 else 1546 bmcr &= ~BMCR_FDX; 1547 1548 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1549 break; 1550 1551 case MII_TICK: 1552 /* 1553 * If we're not currently selected, just return. 1554 */ 1555 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1556 return (0); 1557 1558 /* Only used for automatic media selection */ 1559 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1560 return (0); 1561 1562 /* Is the interface even up? */ 1563 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1564 return (0); 1565 1566 /* 1567 * Check link status; if we don't have a link, try another 1568 * speed. We can't detect duplex mode, so half-duplex is 1569 * what we have to settle for. 1570 */ 1571 1572 /* Read twice in case the register is latched */ 1573 bmsr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1574 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1575 1576 if ((bmsr & BMSR_LINK) != 0) { 1577 /* We have a carrier */ 1578 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1579 1580 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1581 bmcr = be_mii_readreg(self, 1582 BE_PHY_INTERNAL, MII_BMCR); 1583 1584 sc->sc_mii_flags |= MIIF_HAVELINK; 1585 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1586 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1587 1588 bmcr &= ~BMCR_ISO; 1589 be_mii_writereg(self, 1590 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1591 1592 printf("%s: link up at %s Mbps\n", 1593 device_xname(self), 1594 (bmcr & BMCR_S100) ? "100" : "10"); 1595 } 1596 return (0); 1597 } 1598 1599 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1600 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1601 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1602 sc->sc_intphy_curspeed = 0; 1603 printf("%s: link down\n", device_xname(self)); 1604 } 1605 1606 /* Only retry autonegotiation every 5 seconds. */ 1607 if (++sc->sc_mii_ticks < 5) 1608 return(0); 1609 1610 sc->sc_mii_ticks = 0; 1611 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1612 /* Just flip the fast speed bit */ 1613 bmcr ^= BMCR_S100; 1614 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1615 1616 break; 1617 1618 case MII_DOWN: 1619 /* Isolate this phy */ 1620 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1621 be_mii_writereg(self, 1622 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1623 return (0); 1624 } 1625 1626 /* Update the media status. */ 1627 be_intphy_status(sc); 1628 1629 /* Callback if something changed. */ 1630 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1631 (*mii->mii_statchg)(self); 1632 sc->sc_mii_active = mii->mii_media_active; 1633 } 1634 return (0); 1635 } 1636 1637 /* 1638 * Determine status of internal transceiver 1639 */ 1640 void 1641 be_intphy_status(struct be_softc *sc) 1642 { 1643 struct mii_data *mii = &sc->sc_mii; 1644 device_t self = sc->sc_dev; 1645 int media_active, media_status; 1646 int bmcr, bmsr; 1647 1648 media_status = IFM_AVALID; 1649 media_active = 0; 1650 1651 /* 1652 * Internal transceiver; do the work here. 1653 */ 1654 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1655 1656 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1657 case (BMCR_S100 | BMCR_FDX): 1658 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1659 break; 1660 case BMCR_S100: 1661 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1662 break; 1663 case BMCR_FDX: 1664 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1665 break; 1666 case 0: 1667 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1668 break; 1669 } 1670 1671 /* Read twice in case the register is latched */ 1672 bmsr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR)| 1673 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1674 if (bmsr & BMSR_LINK) 1675 media_status |= IFM_ACTIVE; 1676 1677 mii->mii_media_status = media_status; 1678 mii->mii_media_active = media_active; 1679 } 1680
Indexes created Tue Sep 30 07:10:03 GMT 2025