be.c revision 1.70
1 /* $NetBSD: be.c,v 1.70 2009/09/18 14:00:44 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.70 2009/09/18 14:00:44 tsutsui Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "bpfilter.h" 65 #include "rnd.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/callout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/if_inarp.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #endif 96 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 device_t sc_dev; 118 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 119 bus_dma_tag_t sc_dmatag; 120 bus_dmamap_t sc_dmamap; 121 struct ethercom sc_ethercom; 122 /*struct ifmedia sc_ifmedia; -* interface media */ 123 struct mii_data sc_mii; /* MII media control */ 124 #define sc_media sc_mii.mii_media/* shorthand */ 125 int sc_phys[2]; /* MII instance -> phy */ 126 127 struct callout sc_tick_ch; 128 129 /* 130 * Some `mii_softc' items we need to emulate MII operation 131 * for our internal transceiver. 132 */ 133 int sc_mii_inst; /* instance of internal phy */ 134 int sc_mii_active; /* currently active medium */ 135 int sc_mii_ticks; /* tick counter */ 136 int sc_mii_flags; /* phy status flags */ 137 #define MIIF_HAVELINK 0x04000000 138 int sc_intphy_curspeed; /* Established link speed */ 139 140 struct qec_softc *sc_qec; /* QEC parent */ 141 142 bus_space_handle_t sc_qr; /* QEC registers */ 143 bus_space_handle_t sc_br; /* BE registers */ 144 bus_space_handle_t sc_cr; /* channel registers */ 145 bus_space_handle_t sc_tr; /* transceiver registers */ 146 147 u_int sc_rev; 148 149 int sc_channel; /* channel number */ 150 int sc_burst; 151 152 struct qec_ring sc_rb; /* Packet Ring Buffer */ 153 154 /* MAC address */ 155 u_int8_t sc_enaddr[6]; 156 #ifdef BEDEBUG 157 int sc_debug; 158 #endif 159 }; 160 161 int bematch(device_t, cfdata_t, void *); 162 void beattach(device_t, device_t, void *); 163 164 int beinit(struct ifnet *); 165 void bestart(struct ifnet *); 166 void bestop(struct ifnet *, int); 167 void bewatchdog(struct ifnet *); 168 int beioctl(struct ifnet *, u_long, void *); 169 void bereset(struct be_softc *); 170 void behwreset(struct be_softc *); 171 172 int beintr(void *); 173 int berint(struct be_softc *); 174 int betint(struct be_softc *); 175 int beqint(struct be_softc *, u_int32_t); 176 int beeint(struct be_softc *, u_int32_t); 177 178 static void be_read(struct be_softc *, int, int); 179 static int be_put(struct be_softc *, int, struct mbuf *); 180 static struct mbuf *be_get(struct be_softc *, int, int); 181 182 void be_pal_gate(struct be_softc *, int); 183 184 /* ifmedia callbacks */ 185 void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186 int be_ifmedia_upd(struct ifnet *); 187 188 void be_mcreset(struct be_softc *); 189 190 /* MII methods & callbacks */ 191 static int be_mii_readreg(device_t, int, int); 192 static void be_mii_writereg(device_t, int, int, int); 193 static void be_mii_statchg(device_t); 194 195 /* MII helpers */ 196 static void be_mii_sync(struct be_softc *); 197 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 198 static int be_mii_reset(struct be_softc *, int); 199 static int be_tcvr_read_bit(struct be_softc *, int); 200 static void be_tcvr_write_bit(struct be_softc *, int, int); 201 202 void be_tick(void *); 203 void be_intphy_auto(struct be_softc *); 204 void be_intphy_status(struct be_softc *); 205 int be_intphy_service(struct be_softc *, struct mii_data *, int); 206 207 208 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 209 bematch, beattach, NULL, NULL); 210 211 int 212 bematch(device_t parent, cfdata_t cf, void *aux) 213 { 214 struct sbus_attach_args *sa = aux; 215 216 return (strcmp(cf->cf_name, sa->sa_name) == 0); 217 } 218 219 void 220 beattach(device_t parent, device_t self, void *aux) 221 { 222 struct sbus_attach_args *sa = aux; 223 struct qec_softc *qec = device_private(parent); 224 struct be_softc *sc = device_private(self); 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct mii_data *mii = &sc->sc_mii; 227 struct mii_softc *child; 228 int node = sa->sa_node; 229 bus_dma_tag_t dmatag = sa->sa_dmatag; 230 bus_dma_segment_t seg; 231 bus_size_t size; 232 int instance; 233 int rseg, error; 234 u_int32_t v; 235 236 sc->sc_dev = self; 237 238 if (sa->sa_nreg < 3) { 239 printf(": only %d register sets\n", sa->sa_nreg); 240 return; 241 } 242 243 if (bus_space_map(sa->sa_bustag, 244 (bus_addr_t)BUS_ADDR( 245 sa->sa_reg[0].oa_space, 246 sa->sa_reg[0].oa_base), 247 (bus_size_t)sa->sa_reg[0].oa_size, 248 0, &sc->sc_cr) != 0) { 249 printf(": cannot map registers\n"); 250 return; 251 } 252 253 if (bus_space_map(sa->sa_bustag, 254 (bus_addr_t)BUS_ADDR( 255 sa->sa_reg[1].oa_space, 256 sa->sa_reg[1].oa_base), 257 (bus_size_t)sa->sa_reg[1].oa_size, 258 0, &sc->sc_br) != 0) { 259 printf(": cannot map registers\n"); 260 return; 261 } 262 263 if (bus_space_map(sa->sa_bustag, 264 (bus_addr_t)BUS_ADDR( 265 sa->sa_reg[2].oa_space, 266 sa->sa_reg[2].oa_base), 267 (bus_size_t)sa->sa_reg[2].oa_size, 268 0, &sc->sc_tr) != 0) { 269 printf(": cannot map registers\n"); 270 return; 271 } 272 273 sc->sc_bustag = sa->sa_bustag; 274 sc->sc_qec = qec; 275 sc->sc_qr = qec->sc_regs; 276 277 sc->sc_rev = prom_getpropint(node, "board-version", -1); 278 printf(": rev %x,", sc->sc_rev); 279 280 callout_init(&sc->sc_tick_ch, 0); 281 282 sc->sc_channel = prom_getpropint(node, "channel#", -1); 283 if (sc->sc_channel == -1) 284 sc->sc_channel = 0; 285 286 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 287 if (sc->sc_burst == -1) 288 sc->sc_burst = qec->sc_burst; 289 290 /* Clamp at parent's burst sizes */ 291 sc->sc_burst &= qec->sc_burst; 292 293 /* Establish interrupt handler */ 294 if (sa->sa_nintr) 295 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 296 beintr, sc); 297 298 prom_getether(node, sc->sc_enaddr); 299 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 300 301 /* 302 * Allocate descriptor ring and buffers. 303 */ 304 305 /* for now, allocate as many bufs as there are ring descriptors */ 306 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 307 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 308 309 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 310 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 311 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 312 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 313 314 /* Get a DMA handle */ 315 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 316 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 317 aprint_error_dev(self, "DMA map create error %d\n", error); 318 return; 319 } 320 321 /* Allocate DMA buffer */ 322 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 323 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 324 aprint_error_dev(self, "DMA buffer alloc error %d\n", 325 error); 326 return; 327 } 328 329 /* Map DMA memory in CPU addressable space */ 330 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 331 &sc->sc_rb.rb_membase, 332 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 333 aprint_error_dev(self, "DMA buffer map error %d\n", 334 error); 335 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 336 return; 337 } 338 339 /* Load the buffer */ 340 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 341 sc->sc_rb.rb_membase, size, NULL, 342 BUS_DMA_NOWAIT)) != 0) { 343 aprint_error_dev(self, "DMA buffer map load error %d\n", 344 error); 345 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 346 bus_dmamem_free(dmatag, &seg, rseg); 347 return; 348 } 349 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 350 351 /* 352 * Initialize our media structures and MII info. 353 */ 354 mii->mii_ifp = ifp; 355 mii->mii_readreg = be_mii_readreg; 356 mii->mii_writereg = be_mii_writereg; 357 mii->mii_statchg = be_mii_statchg; 358 359 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 360 361 /* 362 * Initialize transceiver and determine which PHY connection to use. 363 */ 364 be_mii_sync(sc); 365 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 366 367 instance = 0; 368 369 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 370 371 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 372 MII_OFFSET_ANY, 0); 373 374 child = LIST_FIRST(&mii->mii_phys); 375 if (child == NULL) { 376 /* No PHY attached */ 377 ifmedia_add(&sc->sc_media, 378 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 379 0, NULL); 380 ifmedia_set(&sc->sc_media, 381 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 382 } else { 383 /* 384 * Note: we support just one PHY on the external 385 * MII connector. 386 */ 387 #ifdef DIAGNOSTIC 388 if (LIST_NEXT(child, mii_list) != NULL) { 389 aprint_error_dev(self, 390 "spurious MII device %s attached\n", 391 device_xname(child->mii_dev)); 392 } 393 #endif 394 if (child->mii_phy != BE_PHY_EXTERNAL || 395 child->mii_inst > 0) { 396 aprint_error_dev(self, 397 "cannot accommodate MII device %s" 398 " at phy %d, instance %d\n", 399 device_xname(child->mii_dev), 400 child->mii_phy, child->mii_inst); 401 } else { 402 sc->sc_phys[instance] = child->mii_phy; 403 } 404 405 /* 406 * XXX - we can really do the following ONLY if the 407 * phy indeed has the auto negotiation capability!! 408 */ 409 ifmedia_set(&sc->sc_media, 410 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 411 412 /* Mark our current media setting */ 413 be_pal_gate(sc, BE_PHY_EXTERNAL); 414 instance++; 415 } 416 417 } 418 419 if ((v & MGMT_PAL_INT_MDIO) != 0) { 420 /* 421 * The be internal phy looks vaguely like MII hardware, 422 * but not enough to be able to use the MII device 423 * layer. Hence, we have to take care of media selection 424 * ourselves. 425 */ 426 427 sc->sc_mii_inst = instance; 428 sc->sc_phys[instance] = BE_PHY_INTERNAL; 429 430 /* Use `ifm_data' to store BMCR bits */ 431 ifmedia_add(&sc->sc_media, 432 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 433 0, NULL); 434 ifmedia_add(&sc->sc_media, 435 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 436 BMCR_S100, NULL); 437 ifmedia_add(&sc->sc_media, 438 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 439 0, NULL); 440 441 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 442 device_xname(self)); 443 444 be_mii_reset(sc, BE_PHY_INTERNAL); 445 /* Only set default medium here if there's no external PHY */ 446 if (instance == 0) { 447 be_pal_gate(sc, BE_PHY_INTERNAL); 448 ifmedia_set(&sc->sc_media, 449 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 450 } else 451 be_mii_writereg(self, 452 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 453 } 454 455 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 456 ifp->if_softc = sc; 457 ifp->if_start = bestart; 458 ifp->if_ioctl = beioctl; 459 ifp->if_watchdog = bewatchdog; 460 ifp->if_init = beinit; 461 ifp->if_stop = bestop; 462 ifp->if_flags = 463 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 464 IFQ_SET_READY(&ifp->if_snd); 465 466 /* claim 802.1q capability */ 467 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 468 469 /* Attach the interface. */ 470 if_attach(ifp); 471 ether_ifattach(ifp, sc->sc_enaddr); 472 } 473 474 475 /* 476 * Routine to copy from mbuf chain to transmit buffer in 477 * network buffer memory. 478 */ 479 static inline int 480 be_put(struct be_softc *sc, int idx, struct mbuf *m) 481 { 482 struct mbuf *n; 483 int len, tlen = 0, boff = 0; 484 void *bp; 485 486 bp = (char *)sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 487 488 for (; m; m = n) { 489 len = m->m_len; 490 if (len == 0) { 491 MFREE(m, n); 492 continue; 493 } 494 memcpy((char *)bp + boff, mtod(m, void *), len); 495 boff += len; 496 tlen += len; 497 MFREE(m, n); 498 } 499 return (tlen); 500 } 501 502 /* 503 * Pull data off an interface. 504 * Len is the length of data, with local net header stripped. 505 * We copy the data into mbufs. When full cluster sized units are present, 506 * we copy into clusters. 507 */ 508 static inline struct mbuf * 509 be_get(struct be_softc *sc, int idx, int totlen) 510 { 511 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 512 struct mbuf *m; 513 struct mbuf *top, **mp; 514 int len, pad, boff = 0; 515 void *bp; 516 517 bp = (char *)sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 518 519 MGETHDR(m, M_DONTWAIT, MT_DATA); 520 if (m == NULL) 521 return (NULL); 522 m->m_pkthdr.rcvif = ifp; 523 m->m_pkthdr.len = totlen; 524 525 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 526 m->m_data += pad; 527 len = MHLEN - pad; 528 top = NULL; 529 mp = ⊤ 530 531 while (totlen > 0) { 532 if (top) { 533 MGET(m, M_DONTWAIT, MT_DATA); 534 if (m == NULL) { 535 m_freem(top); 536 return (NULL); 537 } 538 len = MLEN; 539 } 540 if (top && totlen >= MINCLSIZE) { 541 MCLGET(m, M_DONTWAIT); 542 if (m->m_flags & M_EXT) 543 len = MCLBYTES; 544 } 545 m->m_len = len = min(totlen, len); 546 memcpy(mtod(m, void *), (char *)bp + boff, len); 547 boff += len; 548 totlen -= len; 549 *mp = m; 550 mp = &m->m_next; 551 } 552 553 return (top); 554 } 555 556 /* 557 * Pass a packet to the higher levels. 558 */ 559 static inline void 560 be_read(struct be_softc *sc, int idx, int len) 561 { 562 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 563 struct mbuf *m; 564 565 if (len <= sizeof(struct ether_header) || 566 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 567 #ifdef BEDEBUG 568 if (sc->sc_debug) 569 printf("%s: invalid packet size %d; dropping\n", 570 ifp->if_xname, len); 571 #endif 572 ifp->if_ierrors++; 573 return; 574 } 575 576 /* 577 * Pull packet off interface. 578 */ 579 m = be_get(sc, idx, len); 580 if (m == NULL) { 581 ifp->if_ierrors++; 582 return; 583 } 584 ifp->if_ipackets++; 585 586 #if NBPFILTER > 0 587 /* 588 * Check if there's a BPF listener on this interface. 589 * If so, hand off the raw packet to BPF. 590 */ 591 if (ifp->if_bpf) 592 bpf_mtap(ifp->if_bpf, m); 593 #endif 594 /* Pass the packet up. */ 595 (*ifp->if_input)(ifp, m); 596 } 597 598 /* 599 * Start output on interface. 600 * We make two assumptions here: 601 * 1) that the current priority is set to splnet _before_ this code 602 * is called *and* is returned to the appropriate priority after 603 * return 604 * 2) that the IFF_OACTIVE flag is checked before this code is called 605 * (i.e. that the output part of the interface is idle) 606 */ 607 void 608 bestart(struct ifnet *ifp) 609 { 610 struct be_softc *sc = ifp->if_softc; 611 struct qec_xd *txd = sc->sc_rb.rb_txd; 612 struct mbuf *m; 613 unsigned int bix, len; 614 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 615 616 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 617 return; 618 619 bix = sc->sc_rb.rb_tdhead; 620 621 for (;;) { 622 IFQ_DEQUEUE(&ifp->if_snd, m); 623 if (m == 0) 624 break; 625 626 #if NBPFILTER > 0 627 /* 628 * If BPF is listening on this interface, let it see the 629 * packet before we commit it to the wire. 630 */ 631 if (ifp->if_bpf) 632 bpf_mtap(ifp->if_bpf, m); 633 #endif 634 635 /* 636 * Copy the mbuf chain into the transmit buffer. 637 */ 638 len = be_put(sc, bix, m); 639 640 /* 641 * Initialize transmit registers and start transmission 642 */ 643 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 644 (len & QEC_XD_LENGTH); 645 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 646 BE_CR_CTRL_TWAKEUP); 647 648 if (++bix == QEC_XD_RING_MAXSIZE) 649 bix = 0; 650 651 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 652 ifp->if_flags |= IFF_OACTIVE; 653 break; 654 } 655 } 656 657 sc->sc_rb.rb_tdhead = bix; 658 } 659 660 void 661 bestop(struct ifnet *ifp, int disable) 662 { 663 struct be_softc *sc = ifp->if_softc; 664 665 callout_stop(&sc->sc_tick_ch); 666 667 /* Down the MII. */ 668 mii_down(&sc->sc_mii); 669 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 670 671 behwreset(sc); 672 } 673 674 void 675 behwreset(struct be_softc *sc) 676 { 677 int n; 678 bus_space_tag_t t = sc->sc_bustag; 679 bus_space_handle_t br = sc->sc_br; 680 681 /* Stop the transmitter */ 682 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 683 for (n = 32; n > 0; n--) { 684 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 685 break; 686 DELAY(20); 687 } 688 689 /* Stop the receiver */ 690 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 691 for (n = 32; n > 0; n--) { 692 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 693 break; 694 DELAY(20); 695 } 696 } 697 698 /* 699 * Reset interface. 700 */ 701 void 702 bereset(struct be_softc *sc) 703 { 704 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 705 int s; 706 707 s = splnet(); 708 behwreset(sc); 709 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 710 beinit(ifp); 711 splx(s); 712 } 713 714 void 715 bewatchdog(struct ifnet *ifp) 716 { 717 struct be_softc *sc = ifp->if_softc; 718 719 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 720 ++sc->sc_ethercom.ec_if.if_oerrors; 721 722 bereset(sc); 723 } 724 725 int 726 beintr(void *arg) 727 { 728 struct be_softc *sc = arg; 729 bus_space_tag_t t = sc->sc_bustag; 730 u_int32_t whyq, whyb, whyc; 731 int r = 0; 732 733 /* Read QEC status, channel status and BE status */ 734 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 735 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 736 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 737 738 if (whyq & QEC_STAT_BM) 739 r |= beeint(sc, whyb); 740 741 if (whyq & QEC_STAT_ER) 742 r |= beqint(sc, whyc); 743 744 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 745 r |= betint(sc); 746 747 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 748 r |= berint(sc); 749 750 return (r); 751 } 752 753 /* 754 * QEC Interrupt. 755 */ 756 int 757 beqint(struct be_softc *sc, u_int32_t why) 758 { 759 device_t self = sc->sc_dev; 760 int r = 0, rst = 0; 761 762 if (why & BE_CR_STAT_TXIRQ) 763 r |= 1; 764 if (why & BE_CR_STAT_RXIRQ) 765 r |= 1; 766 767 if (why & BE_CR_STAT_BERROR) { 768 r |= 1; 769 rst = 1; 770 aprint_error_dev(self, "bigmac error\n"); 771 } 772 773 if (why & BE_CR_STAT_TXDERR) { 774 r |= 1; 775 rst = 1; 776 aprint_error_dev(self, "bogus tx descriptor\n"); 777 } 778 779 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 780 r |= 1; 781 rst = 1; 782 aprint_error_dev(self, "tx DMA error ( "); 783 if (why & BE_CR_STAT_TXLERR) 784 printf("Late "); 785 if (why & BE_CR_STAT_TXPERR) 786 printf("Parity "); 787 if (why & BE_CR_STAT_TXSERR) 788 printf("Generic "); 789 printf(")\n"); 790 } 791 792 if (why & BE_CR_STAT_RXDROP) { 793 r |= 1; 794 rst = 1; 795 aprint_error_dev(self, "out of rx descriptors\n"); 796 } 797 798 if (why & BE_CR_STAT_RXSMALL) { 799 r |= 1; 800 rst = 1; 801 aprint_error_dev(self, "rx descriptor too small\n"); 802 } 803 804 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 805 r |= 1; 806 rst = 1; 807 aprint_error_dev(self, "rx DMA error ( "); 808 if (why & BE_CR_STAT_RXLERR) 809 printf("Late "); 810 if (why & BE_CR_STAT_RXPERR) 811 printf("Parity "); 812 if (why & BE_CR_STAT_RXSERR) 813 printf("Generic "); 814 printf(")\n"); 815 } 816 817 if (!r) { 818 rst = 1; 819 aprint_error_dev(self, "unexpected error interrupt %08x\n", 820 why); 821 } 822 823 if (rst) { 824 printf("%s: resetting\n", device_xname(self)); 825 bereset(sc); 826 } 827 828 return (r); 829 } 830 831 /* 832 * Error interrupt. 833 */ 834 int 835 beeint(struct be_softc *sc, u_int32_t why) 836 { 837 device_t self = sc->sc_dev; 838 int r = 0, rst = 0; 839 840 if (why & BE_BR_STAT_RFIFOVF) { 841 r |= 1; 842 rst = 1; 843 aprint_error_dev(self, "receive fifo overrun\n"); 844 } 845 if (why & BE_BR_STAT_TFIFO_UND) { 846 r |= 1; 847 rst = 1; 848 aprint_error_dev(self, "transmit fifo underrun\n"); 849 } 850 if (why & BE_BR_STAT_MAXPKTERR) { 851 r |= 1; 852 rst = 1; 853 aprint_error_dev(self, "max packet size error\n"); 854 } 855 856 if (!r) { 857 rst = 1; 858 aprint_error_dev(self, "unexpected error interrupt %08x\n", 859 why); 860 } 861 862 if (rst) { 863 printf("%s: resetting\n", device_xname(self)); 864 bereset(sc); 865 } 866 867 return (r); 868 } 869 870 /* 871 * Transmit interrupt. 872 */ 873 int 874 betint(struct be_softc *sc) 875 { 876 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 877 bus_space_tag_t t = sc->sc_bustag; 878 bus_space_handle_t br = sc->sc_br; 879 unsigned int bix, txflags; 880 881 /* 882 * Unload collision counters 883 */ 884 ifp->if_collisions += 885 bus_space_read_4(t, br, BE_BRI_NCCNT) + 886 bus_space_read_4(t, br, BE_BRI_FCCNT) + 887 bus_space_read_4(t, br, BE_BRI_EXCNT) + 888 bus_space_read_4(t, br, BE_BRI_LTCNT); 889 890 /* 891 * the clear the hardware counters 892 */ 893 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 894 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 895 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 896 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 897 898 bix = sc->sc_rb.rb_tdtail; 899 900 for (;;) { 901 if (sc->sc_rb.rb_td_nbusy <= 0) 902 break; 903 904 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 905 906 if (txflags & QEC_XD_OWN) 907 break; 908 909 ifp->if_flags &= ~IFF_OACTIVE; 910 ifp->if_opackets++; 911 912 if (++bix == QEC_XD_RING_MAXSIZE) 913 bix = 0; 914 915 --sc->sc_rb.rb_td_nbusy; 916 } 917 918 sc->sc_rb.rb_tdtail = bix; 919 920 bestart(ifp); 921 922 if (sc->sc_rb.rb_td_nbusy == 0) 923 ifp->if_timer = 0; 924 925 return (1); 926 } 927 928 /* 929 * Receive interrupt. 930 */ 931 int 932 berint(struct be_softc *sc) 933 { 934 struct qec_xd *xd = sc->sc_rb.rb_rxd; 935 unsigned int bix, len; 936 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 937 938 bix = sc->sc_rb.rb_rdtail; 939 940 /* 941 * Process all buffers with valid data. 942 */ 943 for (;;) { 944 len = xd[bix].xd_flags; 945 if (len & QEC_XD_OWN) 946 break; 947 948 len &= QEC_XD_LENGTH; 949 be_read(sc, bix, len); 950 951 /* ... */ 952 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 953 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 954 955 if (++bix == QEC_XD_RING_MAXSIZE) 956 bix = 0; 957 } 958 959 sc->sc_rb.rb_rdtail = bix; 960 961 return (1); 962 } 963 964 int 965 beioctl(struct ifnet *ifp, u_long cmd, void *data) 966 { 967 struct be_softc *sc = ifp->if_softc; 968 struct ifaddr *ifa = data; 969 struct ifreq *ifr = data; 970 int s, error = 0; 971 972 s = splnet(); 973 974 switch (cmd) { 975 case SIOCINITIFADDR: 976 ifp->if_flags |= IFF_UP; 977 beinit(ifp); 978 switch (ifa->ifa_addr->sa_family) { 979 #ifdef INET 980 case AF_INET: 981 arp_ifinit(ifp, ifa); 982 break; 983 #endif /* INET */ 984 default: 985 break; 986 } 987 break; 988 989 case SIOCSIFFLAGS: 990 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 991 break; 992 /* XXX re-use ether_ioctl() */ 993 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 994 case IFF_RUNNING: 995 /* 996 * If interface is marked down and it is running, then 997 * stop it. 998 */ 999 bestop(ifp, 0); 1000 ifp->if_flags &= ~IFF_RUNNING; 1001 break; 1002 case IFF_UP: 1003 /* 1004 * If interface is marked up and it is stopped, then 1005 * start it. 1006 */ 1007 beinit(ifp); 1008 break; 1009 default: 1010 /* 1011 * Reset the interface to pick up changes in any other 1012 * flags that affect hardware registers. 1013 */ 1014 bestop(ifp, 0); 1015 beinit(ifp); 1016 break; 1017 } 1018 #ifdef BEDEBUG 1019 if (ifp->if_flags & IFF_DEBUG) 1020 sc->sc_debug = 1; 1021 else 1022 sc->sc_debug = 0; 1023 #endif 1024 break; 1025 1026 case SIOCGIFMEDIA: 1027 case SIOCSIFMEDIA: 1028 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1029 break; 1030 default: 1031 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1032 /* 1033 * Multicast list has changed; set the hardware filter 1034 * accordingly. 1035 */ 1036 if (ifp->if_flags & IFF_RUNNING) 1037 error = beinit(ifp); 1038 else 1039 error = 0; 1040 } 1041 break; 1042 } 1043 splx(s); 1044 return (error); 1045 } 1046 1047 1048 int 1049 beinit(struct ifnet *ifp) 1050 { 1051 struct be_softc *sc = ifp->if_softc; 1052 bus_space_tag_t t = sc->sc_bustag; 1053 bus_space_handle_t br = sc->sc_br; 1054 bus_space_handle_t cr = sc->sc_cr; 1055 struct qec_softc *qec = sc->sc_qec; 1056 u_int32_t v; 1057 u_int32_t qecaddr; 1058 u_int8_t *ea; 1059 int rc, s; 1060 1061 s = splnet(); 1062 1063 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1064 1065 bestop(ifp, 1); 1066 1067 ea = sc->sc_enaddr; 1068 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1069 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1070 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1071 1072 /* Clear hash table */ 1073 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1074 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1075 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1076 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1077 1078 /* Re-initialize RX configuration */ 1079 v = BE_BR_RXCFG_FIFO; 1080 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1081 1082 be_mcreset(sc); 1083 1084 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1085 1086 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1087 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1088 1089 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1090 1091 /* 1092 * Turn off counter expiration interrupts as well as 1093 * 'gotframe' and 'sentframe' 1094 */ 1095 bus_space_write_4(t, br, BE_BRI_IMASK, 1096 BE_BR_IMASK_GOTFRAME | 1097 BE_BR_IMASK_RCNTEXP | 1098 BE_BR_IMASK_ACNTEXP | 1099 BE_BR_IMASK_CCNTEXP | 1100 BE_BR_IMASK_LCNTEXP | 1101 BE_BR_IMASK_CVCNTEXP | 1102 BE_BR_IMASK_SENTFRAME | 1103 BE_BR_IMASK_NCNTEXP | 1104 BE_BR_IMASK_ECNTEXP | 1105 BE_BR_IMASK_LCCNTEXP | 1106 BE_BR_IMASK_FCNTEXP | 1107 BE_BR_IMASK_DTIMEXP); 1108 1109 /* Channel registers: */ 1110 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1111 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1112 1113 qecaddr = sc->sc_channel * qec->sc_msize; 1114 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1115 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1116 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1117 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1118 1119 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1120 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1121 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1122 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1123 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1124 1125 /* Set max packet length */ 1126 v = ETHER_MAX_LEN; 1127 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1128 v += ETHER_VLAN_ENCAP_LEN; 1129 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1130 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1131 1132 /* Enable transmitter */ 1133 bus_space_write_4(t, br, BE_BRI_TXCFG, 1134 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1135 1136 /* Enable receiver */ 1137 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1138 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1139 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1140 1141 if ((rc = be_ifmedia_upd(ifp)) != 0) 1142 goto out; 1143 1144 ifp->if_flags |= IFF_RUNNING; 1145 ifp->if_flags &= ~IFF_OACTIVE; 1146 1147 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1148 1149 return 0; 1150 out: 1151 splx(s); 1152 return rc; 1153 } 1154 1155 void 1156 be_mcreset(struct be_softc *sc) 1157 { 1158 struct ethercom *ec = &sc->sc_ethercom; 1159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1160 bus_space_tag_t t = sc->sc_bustag; 1161 bus_space_handle_t br = sc->sc_br; 1162 u_int32_t crc; 1163 u_int16_t hash[4]; 1164 u_int8_t octet; 1165 u_int32_t v; 1166 int i, j; 1167 struct ether_multi *enm; 1168 struct ether_multistep step; 1169 1170 if (ifp->if_flags & IFF_PROMISC) { 1171 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1172 v |= BE_BR_RXCFG_PMISC; 1173 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1174 return; 1175 } 1176 1177 if (ifp->if_flags & IFF_ALLMULTI) { 1178 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1179 goto chipit; 1180 } 1181 1182 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1183 1184 ETHER_FIRST_MULTI(step, ec, enm); 1185 while (enm != NULL) { 1186 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1187 /* 1188 * We must listen to a range of multicast 1189 * addresses. For now, just accept all 1190 * multicasts, rather than trying to set only 1191 * those filter bits needed to match the range. 1192 * (At this time, the only use of address 1193 * ranges is for IP multicast routing, for 1194 * which the range is big enough to require 1195 * all bits set.) 1196 */ 1197 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1198 ifp->if_flags |= IFF_ALLMULTI; 1199 goto chipit; 1200 } 1201 1202 crc = 0xffffffff; 1203 1204 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1205 octet = enm->enm_addrlo[i]; 1206 1207 for (j = 0; j < 8; j++) { 1208 if ((crc & 1) ^ (octet & 1)) { 1209 crc >>= 1; 1210 crc ^= MC_POLY_LE; 1211 } 1212 else 1213 crc >>= 1; 1214 octet >>= 1; 1215 } 1216 } 1217 1218 crc >>= 26; 1219 hash[crc >> 4] |= 1 << (crc & 0xf); 1220 ETHER_NEXT_MULTI(step, enm); 1221 } 1222 1223 ifp->if_flags &= ~IFF_ALLMULTI; 1224 1225 chipit: 1226 /* Enable the hash filter */ 1227 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1228 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1229 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1230 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1231 1232 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1233 v &= ~BE_BR_RXCFG_PMISC; 1234 v |= BE_BR_RXCFG_HENABLE; 1235 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1236 } 1237 1238 /* 1239 * Set the tcvr to an idle state 1240 */ 1241 void 1242 be_mii_sync(struct be_softc *sc) 1243 { 1244 bus_space_tag_t t = sc->sc_bustag; 1245 bus_space_handle_t tr = sc->sc_tr; 1246 int n = 32; 1247 1248 while (n--) { 1249 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1250 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1251 MGMT_PAL_OENAB); 1252 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1253 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1254 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1255 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1256 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1257 } 1258 } 1259 1260 void 1261 be_pal_gate(struct be_softc *sc, int phy) 1262 { 1263 bus_space_tag_t t = sc->sc_bustag; 1264 bus_space_handle_t tr = sc->sc_tr; 1265 u_int32_t v; 1266 1267 be_mii_sync(sc); 1268 1269 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1270 if (phy == BE_PHY_INTERNAL) 1271 v &= ~TCVR_PAL_SERIAL; 1272 1273 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1274 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1275 } 1276 1277 static int 1278 be_tcvr_read_bit(struct be_softc *sc, int phy) 1279 { 1280 bus_space_tag_t t = sc->sc_bustag; 1281 bus_space_handle_t tr = sc->sc_tr; 1282 int ret; 1283 1284 if (phy == BE_PHY_INTERNAL) { 1285 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1286 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1287 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1288 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1289 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1290 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1291 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1292 } else { 1293 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1294 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1295 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1296 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1297 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1298 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1299 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1300 } 1301 1302 return (ret); 1303 } 1304 1305 static void 1306 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1307 { 1308 bus_space_tag_t t = sc->sc_bustag; 1309 bus_space_handle_t tr = sc->sc_tr; 1310 u_int32_t v; 1311 1312 if (phy == BE_PHY_INTERNAL) { 1313 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1314 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1315 } else { 1316 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1317 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1318 } 1319 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1320 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1321 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1322 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1323 } 1324 1325 static void 1326 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1327 { 1328 int i; 1329 1330 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1331 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1332 } 1333 } 1334 1335 static int 1336 be_mii_readreg(device_t self, int phy, int reg) 1337 { 1338 struct be_softc *sc = device_private(self); 1339 int val = 0, i; 1340 1341 /* 1342 * Read the PHY register by manually driving the MII control lines. 1343 */ 1344 be_mii_sync(sc); 1345 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1346 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1347 be_mii_sendbits(sc, phy, phy, 5); 1348 be_mii_sendbits(sc, phy, reg, 5); 1349 1350 (void) be_tcvr_read_bit(sc, phy); 1351 (void) be_tcvr_read_bit(sc, phy); 1352 1353 for (i = 15; i >= 0; i--) 1354 val |= (be_tcvr_read_bit(sc, phy) << i); 1355 1356 (void) be_tcvr_read_bit(sc, phy); 1357 (void) be_tcvr_read_bit(sc, phy); 1358 (void) be_tcvr_read_bit(sc, phy); 1359 1360 return (val); 1361 } 1362 1363 void 1364 be_mii_writereg(device_t self, int phy, int reg, int val) 1365 { 1366 struct be_softc *sc = device_private(self); 1367 int i; 1368 1369 /* 1370 * Write the PHY register by manually driving the MII control lines. 1371 */ 1372 be_mii_sync(sc); 1373 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1374 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1375 be_mii_sendbits(sc, phy, phy, 5); 1376 be_mii_sendbits(sc, phy, reg, 5); 1377 1378 be_tcvr_write_bit(sc, phy, 1); 1379 be_tcvr_write_bit(sc, phy, 0); 1380 1381 for (i = 15; i >= 0; i--) 1382 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1383 } 1384 1385 int 1386 be_mii_reset(struct be_softc *sc, int phy) 1387 { 1388 device_t self = sc->sc_dev; 1389 int n; 1390 1391 be_mii_writereg(self, phy, MII_BMCR, 1392 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1393 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1394 1395 for (n = 16; n >= 0; n--) { 1396 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1397 if ((bmcr & BMCR_RESET) == 0) 1398 break; 1399 DELAY(20); 1400 } 1401 if (n == 0) { 1402 aprint_error_dev(self, "bmcr reset failed\n"); 1403 return (EIO); 1404 } 1405 1406 return (0); 1407 } 1408 1409 void 1410 be_tick(void *arg) 1411 { 1412 struct be_softc *sc = arg; 1413 int s = splnet(); 1414 1415 mii_tick(&sc->sc_mii); 1416 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1417 1418 splx(s); 1419 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1420 } 1421 1422 void 1423 be_mii_statchg(device_t self) 1424 { 1425 struct be_softc *sc = device_private(self); 1426 bus_space_tag_t t = sc->sc_bustag; 1427 bus_space_handle_t br = sc->sc_br; 1428 u_int instance; 1429 u_int32_t v; 1430 1431 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1432 #ifdef DIAGNOSTIC 1433 if (instance > 1) 1434 panic("be_mii_statchg: instance %d out of range", instance); 1435 #endif 1436 1437 /* Update duplex mode in TX configuration */ 1438 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1439 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1440 v |= BE_BR_TXCFG_FULLDPLX; 1441 else 1442 v &= ~BE_BR_TXCFG_FULLDPLX; 1443 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1444 1445 /* Change to appropriate gate in transceiver PAL */ 1446 be_pal_gate(sc, sc->sc_phys[instance]); 1447 } 1448 1449 /* 1450 * Get current media settings. 1451 */ 1452 void 1453 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1454 { 1455 struct be_softc *sc = ifp->if_softc; 1456 1457 mii_pollstat(&sc->sc_mii); 1458 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1459 1460 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1461 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1462 return; 1463 } 1464 1465 /* 1466 * Set media options. 1467 */ 1468 int 1469 be_ifmedia_upd(struct ifnet *ifp) 1470 { 1471 struct be_softc *sc = ifp->if_softc; 1472 int error; 1473 1474 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1475 error = 0; 1476 else if (error != 0) 1477 return error; 1478 1479 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1480 } 1481 1482 /* 1483 * Service routine for our pseudo-MII internal transceiver. 1484 */ 1485 int 1486 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1487 { 1488 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1489 device_t self = sc->sc_dev; 1490 int bmcr, bmsr; 1491 int error; 1492 1493 switch (cmd) { 1494 case MII_POLLSTAT: 1495 /* 1496 * If we're not polling our PHY instance, just return. 1497 */ 1498 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1499 return (0); 1500 1501 break; 1502 1503 case MII_MEDIACHG: 1504 1505 /* 1506 * If the media indicates a different PHY instance, 1507 * isolate ourselves. 1508 */ 1509 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1510 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1511 be_mii_writereg(self, 1512 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1513 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1514 sc->sc_intphy_curspeed = 0; 1515 return (0); 1516 } 1517 1518 1519 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1520 return (error); 1521 1522 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1523 1524 /* 1525 * Select the new mode and take out of isolation 1526 */ 1527 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1528 bmcr |= BMCR_S100; 1529 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1530 bmcr &= ~BMCR_S100; 1531 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1532 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1533 bmcr &= ~BMCR_S100; 1534 bmcr |= sc->sc_intphy_curspeed; 1535 } else { 1536 /* Keep isolated until link is up */ 1537 bmcr |= BMCR_ISO; 1538 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1539 } 1540 } 1541 1542 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1543 bmcr |= BMCR_FDX; 1544 else 1545 bmcr &= ~BMCR_FDX; 1546 1547 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1548 break; 1549 1550 case MII_TICK: 1551 /* 1552 * If we're not currently selected, just return. 1553 */ 1554 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1555 return (0); 1556 1557 /* Only used for automatic media selection */ 1558 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1559 return (0); 1560 1561 /* Is the interface even up? */ 1562 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1563 return (0); 1564 1565 /* 1566 * Check link status; if we don't have a link, try another 1567 * speed. We can't detect duplex mode, so half-duplex is 1568 * what we have to settle for. 1569 */ 1570 1571 /* Read twice in case the register is latched */ 1572 bmsr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1573 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1574 1575 if ((bmsr & BMSR_LINK) != 0) { 1576 /* We have a carrier */ 1577 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1578 1579 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1580 bmcr = be_mii_readreg(self, 1581 BE_PHY_INTERNAL, MII_BMCR); 1582 1583 sc->sc_mii_flags |= MIIF_HAVELINK; 1584 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1585 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1586 1587 bmcr &= ~BMCR_ISO; 1588 be_mii_writereg(self, 1589 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1590 1591 printf("%s: link up at %s Mbps\n", 1592 device_xname(self), 1593 (bmcr & BMCR_S100) ? "100" : "10"); 1594 } 1595 return (0); 1596 } 1597 1598 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1599 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1600 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1601 sc->sc_intphy_curspeed = 0; 1602 printf("%s: link down\n", device_xname(self)); 1603 } 1604 1605 /* Only retry autonegotiation every 5 seconds. */ 1606 if (++sc->sc_mii_ticks < 5) 1607 return(0); 1608 1609 sc->sc_mii_ticks = 0; 1610 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1611 /* Just flip the fast speed bit */ 1612 bmcr ^= BMCR_S100; 1613 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1614 1615 break; 1616 1617 case MII_DOWN: 1618 /* Isolate this phy */ 1619 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1620 be_mii_writereg(self, 1621 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1622 return (0); 1623 } 1624 1625 /* Update the media status. */ 1626 be_intphy_status(sc); 1627 1628 /* Callback if something changed. */ 1629 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1630 (*mii->mii_statchg)(self); 1631 sc->sc_mii_active = mii->mii_media_active; 1632 } 1633 return (0); 1634 } 1635 1636 /* 1637 * Determine status of internal transceiver 1638 */ 1639 void 1640 be_intphy_status(struct be_softc *sc) 1641 { 1642 struct mii_data *mii = &sc->sc_mii; 1643 device_t self = sc->sc_dev; 1644 int media_active, media_status; 1645 int bmcr, bmsr; 1646 1647 media_status = IFM_AVALID; 1648 media_active = 0; 1649 1650 /* 1651 * Internal transceiver; do the work here. 1652 */ 1653 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1654 1655 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1656 case (BMCR_S100 | BMCR_FDX): 1657 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1658 break; 1659 case BMCR_S100: 1660 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1661 break; 1662 case BMCR_FDX: 1663 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1664 break; 1665 case 0: 1666 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1667 break; 1668 } 1669 1670 /* Read twice in case the register is latched */ 1671 bmsr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR)| 1672 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1673 if (bmsr & BMSR_LINK) 1674 media_status |= IFM_ACTIVE; 1675 1676 mii->mii_media_status = media_status; 1677 mii->mii_media_active = media_active; 1678 } 1679
Indexes created Tue Sep 30 11:09:46 GMT 2025