be.c revision 1.72
1 /* $NetBSD: be.c,v 1.72 2009/09/18 14:14:06 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1998 Theo de Raadt and Jason L. Wright. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. The name of the authors may not be used to endorse or promote products 45 * derived from this software without specific prior written permission. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 */ 58 59 #include <sys/cdefs.h> 60 __KERNEL_RCSID(0, "$NetBSD: be.c,v 1.72 2009/09/18 14:14:06 tsutsui Exp $"); 61 62 #include "opt_ddb.h" 63 #include "opt_inet.h" 64 #include "bpfilter.h" 65 #include "rnd.h" 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/callout.h> 70 #include <sys/kernel.h> 71 #include <sys/errno.h> 72 #include <sys/ioctl.h> 73 #include <sys/mbuf.h> 74 #include <sys/socket.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #if NRND > 0 79 #include <sys/rnd.h> 80 #endif 81 82 #include <net/if.h> 83 #include <net/if_dl.h> 84 #include <net/if_types.h> 85 #include <net/netisr.h> 86 #include <net/if_media.h> 87 #include <net/if_ether.h> 88 89 #ifdef INET 90 #include <netinet/in.h> 91 #include <netinet/if_inarp.h> 92 #include <netinet/in_systm.h> 93 #include <netinet/in_var.h> 94 #include <netinet/ip.h> 95 #endif 96 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 #include <sys/bus.h> 104 #include <sys/intr.h> 105 #include <machine/autoconf.h> 106 107 #include <dev/sbus/sbusvar.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/sbus/qecreg.h> 113 #include <dev/sbus/qecvar.h> 114 #include <dev/sbus/bereg.h> 115 116 struct be_softc { 117 device_t sc_dev; 118 bus_space_tag_t sc_bustag; /* bus & DMA tags */ 119 bus_dma_tag_t sc_dmatag; 120 bus_dmamap_t sc_dmamap; 121 struct ethercom sc_ethercom; 122 /*struct ifmedia sc_ifmedia; -* interface media */ 123 struct mii_data sc_mii; /* MII media control */ 124 #define sc_media sc_mii.mii_media/* shorthand */ 125 int sc_phys[2]; /* MII instance -> phy */ 126 127 struct callout sc_tick_ch; 128 129 /* 130 * Some `mii_softc' items we need to emulate MII operation 131 * for our internal transceiver. 132 */ 133 int sc_mii_inst; /* instance of internal phy */ 134 int sc_mii_active; /* currently active medium */ 135 int sc_mii_ticks; /* tick counter */ 136 int sc_mii_flags; /* phy status flags */ 137 #define MIIF_HAVELINK 0x04000000 138 int sc_intphy_curspeed; /* Established link speed */ 139 140 struct qec_softc *sc_qec; /* QEC parent */ 141 142 bus_space_handle_t sc_qr; /* QEC registers */ 143 bus_space_handle_t sc_br; /* BE registers */ 144 bus_space_handle_t sc_cr; /* channel registers */ 145 bus_space_handle_t sc_tr; /* transceiver registers */ 146 147 u_int sc_rev; 148 149 int sc_channel; /* channel number */ 150 int sc_burst; 151 152 struct qec_ring sc_rb; /* Packet Ring Buffer */ 153 154 /* MAC address */ 155 u_int8_t sc_enaddr[6]; 156 #ifdef BEDEBUG 157 int sc_debug; 158 #endif 159 }; 160 161 static int bematch(device_t, cfdata_t, void *); 162 static void beattach(device_t, device_t, void *); 163 164 static int beinit(struct ifnet *); 165 static void bestart(struct ifnet *); 166 static void bestop(struct ifnet *, int); 167 static void bewatchdog(struct ifnet *); 168 static int beioctl(struct ifnet *, u_long, void *); 169 static void bereset(struct be_softc *); 170 static void behwreset(struct be_softc *); 171 172 static int beintr(void *); 173 static int berint(struct be_softc *); 174 static int betint(struct be_softc *); 175 static int beqint(struct be_softc *, u_int32_t); 176 static int beeint(struct be_softc *, u_int32_t); 177 178 static void be_read(struct be_softc *, int, int); 179 static int be_put(struct be_softc *, int, struct mbuf *); 180 static struct mbuf *be_get(struct be_softc *, int, int); 181 182 static void be_pal_gate(struct be_softc *, int); 183 184 /* ifmedia callbacks */ 185 static void be_ifmedia_sts(struct ifnet *, struct ifmediareq *); 186 static int be_ifmedia_upd(struct ifnet *); 187 188 static void be_mcreset(struct be_softc *); 189 190 /* MII methods & callbacks */ 191 static int be_mii_readreg(device_t, int, int); 192 static void be_mii_writereg(device_t, int, int, int); 193 static void be_mii_statchg(device_t); 194 195 /* MII helpers */ 196 static void be_mii_sync(struct be_softc *); 197 static void be_mii_sendbits(struct be_softc *, int, u_int32_t, int); 198 static int be_mii_reset(struct be_softc *, int); 199 static int be_tcvr_read_bit(struct be_softc *, int); 200 static void be_tcvr_write_bit(struct be_softc *, int, int); 201 202 static void be_tick(void *); 203 #if 0 204 static void be_intphy_auto(struct be_softc *); 205 #endif 206 static void be_intphy_status(struct be_softc *); 207 static int be_intphy_service(struct be_softc *, struct mii_data *, int); 208 209 210 CFATTACH_DECL_NEW(be, sizeof(struct be_softc), 211 bematch, beattach, NULL, NULL); 212 213 int 214 bematch(device_t parent, cfdata_t cf, void *aux) 215 { 216 struct sbus_attach_args *sa = aux; 217 218 return (strcmp(cf->cf_name, sa->sa_name) == 0); 219 } 220 221 void 222 beattach(device_t parent, device_t self, void *aux) 223 { 224 struct sbus_attach_args *sa = aux; 225 struct qec_softc *qec = device_private(parent); 226 struct be_softc *sc = device_private(self); 227 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 228 struct mii_data *mii = &sc->sc_mii; 229 struct mii_softc *child; 230 int node = sa->sa_node; 231 bus_dma_tag_t dmatag = sa->sa_dmatag; 232 bus_dma_segment_t seg; 233 bus_size_t size; 234 int instance; 235 int rseg, error; 236 u_int32_t v; 237 238 sc->sc_dev = self; 239 240 if (sa->sa_nreg < 3) { 241 printf(": only %d register sets\n", sa->sa_nreg); 242 return; 243 } 244 245 if (bus_space_map(sa->sa_bustag, 246 (bus_addr_t)BUS_ADDR( 247 sa->sa_reg[0].oa_space, 248 sa->sa_reg[0].oa_base), 249 (bus_size_t)sa->sa_reg[0].oa_size, 250 0, &sc->sc_cr) != 0) { 251 printf(": cannot map registers\n"); 252 return; 253 } 254 255 if (bus_space_map(sa->sa_bustag, 256 (bus_addr_t)BUS_ADDR( 257 sa->sa_reg[1].oa_space, 258 sa->sa_reg[1].oa_base), 259 (bus_size_t)sa->sa_reg[1].oa_size, 260 0, &sc->sc_br) != 0) { 261 printf(": cannot map registers\n"); 262 return; 263 } 264 265 if (bus_space_map(sa->sa_bustag, 266 (bus_addr_t)BUS_ADDR( 267 sa->sa_reg[2].oa_space, 268 sa->sa_reg[2].oa_base), 269 (bus_size_t)sa->sa_reg[2].oa_size, 270 0, &sc->sc_tr) != 0) { 271 printf(": cannot map registers\n"); 272 return; 273 } 274 275 sc->sc_bustag = sa->sa_bustag; 276 sc->sc_qec = qec; 277 sc->sc_qr = qec->sc_regs; 278 279 sc->sc_rev = prom_getpropint(node, "board-version", -1); 280 printf(": rev %x,", sc->sc_rev); 281 282 callout_init(&sc->sc_tick_ch, 0); 283 284 sc->sc_channel = prom_getpropint(node, "channel#", -1); 285 if (sc->sc_channel == -1) 286 sc->sc_channel = 0; 287 288 sc->sc_burst = prom_getpropint(node, "burst-sizes", -1); 289 if (sc->sc_burst == -1) 290 sc->sc_burst = qec->sc_burst; 291 292 /* Clamp at parent's burst sizes */ 293 sc->sc_burst &= qec->sc_burst; 294 295 /* Establish interrupt handler */ 296 if (sa->sa_nintr) 297 (void)bus_intr_establish(sa->sa_bustag, sa->sa_pri, IPL_NET, 298 beintr, sc); 299 300 prom_getether(node, sc->sc_enaddr); 301 printf(" address %s\n", ether_sprintf(sc->sc_enaddr)); 302 303 /* 304 * Allocate descriptor ring and buffers. 305 */ 306 307 /* for now, allocate as many bufs as there are ring descriptors */ 308 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE; 309 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE; 310 311 size = QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 312 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) + 313 sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ + 314 sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ; 315 316 /* Get a DMA handle */ 317 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 318 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 319 aprint_error_dev(self, "DMA map create error %d\n", error); 320 return; 321 } 322 323 /* Allocate DMA buffer */ 324 if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0, 325 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 326 aprint_error_dev(self, "DMA buffer alloc error %d\n", 327 error); 328 return; 329 } 330 331 /* Map DMA memory in CPU addressable space */ 332 if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size, 333 &sc->sc_rb.rb_membase, 334 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 335 aprint_error_dev(self, "DMA buffer map error %d\n", 336 error); 337 bus_dmamem_free(sa->sa_dmatag, &seg, rseg); 338 return; 339 } 340 341 /* Load the buffer */ 342 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 343 sc->sc_rb.rb_membase, size, NULL, 344 BUS_DMA_NOWAIT)) != 0) { 345 aprint_error_dev(self, "DMA buffer map load error %d\n", 346 error); 347 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size); 348 bus_dmamem_free(dmatag, &seg, rseg); 349 return; 350 } 351 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 352 353 /* 354 * Initialize our media structures and MII info. 355 */ 356 mii->mii_ifp = ifp; 357 mii->mii_readreg = be_mii_readreg; 358 mii->mii_writereg = be_mii_writereg; 359 mii->mii_statchg = be_mii_statchg; 360 361 ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts); 362 363 /* 364 * Initialize transceiver and determine which PHY connection to use. 365 */ 366 be_mii_sync(sc); 367 v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL); 368 369 instance = 0; 370 371 if ((v & MGMT_PAL_EXT_MDIO) != 0) { 372 373 mii_attach(self, mii, 0xffffffff, BE_PHY_EXTERNAL, 374 MII_OFFSET_ANY, 0); 375 376 child = LIST_FIRST(&mii->mii_phys); 377 if (child == NULL) { 378 /* No PHY attached */ 379 ifmedia_add(&sc->sc_media, 380 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance), 381 0, NULL); 382 ifmedia_set(&sc->sc_media, 383 IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance)); 384 } else { 385 /* 386 * Note: we support just one PHY on the external 387 * MII connector. 388 */ 389 #ifdef DIAGNOSTIC 390 if (LIST_NEXT(child, mii_list) != NULL) { 391 aprint_error_dev(self, 392 "spurious MII device %s attached\n", 393 device_xname(child->mii_dev)); 394 } 395 #endif 396 if (child->mii_phy != BE_PHY_EXTERNAL || 397 child->mii_inst > 0) { 398 aprint_error_dev(self, 399 "cannot accommodate MII device %s" 400 " at phy %d, instance %d\n", 401 device_xname(child->mii_dev), 402 child->mii_phy, child->mii_inst); 403 } else { 404 sc->sc_phys[instance] = child->mii_phy; 405 } 406 407 /* 408 * XXX - we can really do the following ONLY if the 409 * phy indeed has the auto negotiation capability!! 410 */ 411 ifmedia_set(&sc->sc_media, 412 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 413 414 /* Mark our current media setting */ 415 be_pal_gate(sc, BE_PHY_EXTERNAL); 416 instance++; 417 } 418 419 } 420 421 if ((v & MGMT_PAL_INT_MDIO) != 0) { 422 /* 423 * The be internal phy looks vaguely like MII hardware, 424 * but not enough to be able to use the MII device 425 * layer. Hence, we have to take care of media selection 426 * ourselves. 427 */ 428 429 sc->sc_mii_inst = instance; 430 sc->sc_phys[instance] = BE_PHY_INTERNAL; 431 432 /* Use `ifm_data' to store BMCR bits */ 433 ifmedia_add(&sc->sc_media, 434 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 435 0, NULL); 436 ifmedia_add(&sc->sc_media, 437 IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance), 438 BMCR_S100, NULL); 439 ifmedia_add(&sc->sc_media, 440 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 441 0, NULL); 442 443 printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n", 444 device_xname(self)); 445 446 be_mii_reset(sc, BE_PHY_INTERNAL); 447 /* Only set default medium here if there's no external PHY */ 448 if (instance == 0) { 449 be_pal_gate(sc, BE_PHY_INTERNAL); 450 ifmedia_set(&sc->sc_media, 451 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance)); 452 } else 453 be_mii_writereg(self, 454 BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO); 455 } 456 457 memcpy(ifp->if_xname, device_xname(self), IFNAMSIZ); 458 ifp->if_softc = sc; 459 ifp->if_start = bestart; 460 ifp->if_ioctl = beioctl; 461 ifp->if_watchdog = bewatchdog; 462 ifp->if_init = beinit; 463 ifp->if_stop = bestop; 464 ifp->if_flags = 465 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 466 IFQ_SET_READY(&ifp->if_snd); 467 468 /* claim 802.1q capability */ 469 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 470 471 /* Attach the interface. */ 472 if_attach(ifp); 473 ether_ifattach(ifp, sc->sc_enaddr); 474 } 475 476 477 /* 478 * Routine to copy from mbuf chain to transmit buffer in 479 * network buffer memory. 480 */ 481 static inline int 482 be_put(struct be_softc *sc, int idx, struct mbuf *m) 483 { 484 struct mbuf *n; 485 int len, tlen = 0, boff = 0; 486 void *bp; 487 488 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ; 489 490 for (; m; m = n) { 491 len = m->m_len; 492 if (len == 0) { 493 MFREE(m, n); 494 continue; 495 } 496 memcpy((char *)bp + boff, mtod(m, void *), len); 497 boff += len; 498 tlen += len; 499 MFREE(m, n); 500 } 501 return (tlen); 502 } 503 504 /* 505 * Pull data off an interface. 506 * Len is the length of data, with local net header stripped. 507 * We copy the data into mbufs. When full cluster sized units are present, 508 * we copy into clusters. 509 */ 510 static inline struct mbuf * 511 be_get(struct be_softc *sc, int idx, int totlen) 512 { 513 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 514 struct mbuf *m; 515 struct mbuf *top, **mp; 516 int len, pad, boff = 0; 517 void *bp; 518 519 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ; 520 521 MGETHDR(m, M_DONTWAIT, MT_DATA); 522 if (m == NULL) 523 return (NULL); 524 m->m_pkthdr.rcvif = ifp; 525 m->m_pkthdr.len = totlen; 526 527 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 528 m->m_data += pad; 529 len = MHLEN - pad; 530 top = NULL; 531 mp = ⊤ 532 533 while (totlen > 0) { 534 if (top) { 535 MGET(m, M_DONTWAIT, MT_DATA); 536 if (m == NULL) { 537 m_freem(top); 538 return (NULL); 539 } 540 len = MLEN; 541 } 542 if (top && totlen >= MINCLSIZE) { 543 MCLGET(m, M_DONTWAIT); 544 if (m->m_flags & M_EXT) 545 len = MCLBYTES; 546 } 547 m->m_len = len = min(totlen, len); 548 memcpy(mtod(m, void *), (char *)bp + boff, len); 549 boff += len; 550 totlen -= len; 551 *mp = m; 552 mp = &m->m_next; 553 } 554 555 return (top); 556 } 557 558 /* 559 * Pass a packet to the higher levels. 560 */ 561 static inline void 562 be_read(struct be_softc *sc, int idx, int len) 563 { 564 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 565 struct mbuf *m; 566 567 if (len <= sizeof(struct ether_header) || 568 len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 569 #ifdef BEDEBUG 570 if (sc->sc_debug) 571 printf("%s: invalid packet size %d; dropping\n", 572 ifp->if_xname, len); 573 #endif 574 ifp->if_ierrors++; 575 return; 576 } 577 578 /* 579 * Pull packet off interface. 580 */ 581 m = be_get(sc, idx, len); 582 if (m == NULL) { 583 ifp->if_ierrors++; 584 return; 585 } 586 ifp->if_ipackets++; 587 588 #if NBPFILTER > 0 589 /* 590 * Check if there's a BPF listener on this interface. 591 * If so, hand off the raw packet to BPF. 592 */ 593 if (ifp->if_bpf) 594 bpf_mtap(ifp->if_bpf, m); 595 #endif 596 /* Pass the packet up. */ 597 (*ifp->if_input)(ifp, m); 598 } 599 600 /* 601 * Start output on interface. 602 * We make two assumptions here: 603 * 1) that the current priority is set to splnet _before_ this code 604 * is called *and* is returned to the appropriate priority after 605 * return 606 * 2) that the IFF_OACTIVE flag is checked before this code is called 607 * (i.e. that the output part of the interface is idle) 608 */ 609 void 610 bestart(struct ifnet *ifp) 611 { 612 struct be_softc *sc = ifp->if_softc; 613 struct qec_xd *txd = sc->sc_rb.rb_txd; 614 struct mbuf *m; 615 unsigned int bix, len; 616 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 617 618 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 619 return; 620 621 bix = sc->sc_rb.rb_tdhead; 622 623 for (;;) { 624 IFQ_DEQUEUE(&ifp->if_snd, m); 625 if (m == 0) 626 break; 627 628 #if NBPFILTER > 0 629 /* 630 * If BPF is listening on this interface, let it see the 631 * packet before we commit it to the wire. 632 */ 633 if (ifp->if_bpf) 634 bpf_mtap(ifp->if_bpf, m); 635 #endif 636 637 /* 638 * Copy the mbuf chain into the transmit buffer. 639 */ 640 len = be_put(sc, bix, m); 641 642 /* 643 * Initialize transmit registers and start transmission 644 */ 645 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP | 646 (len & QEC_XD_LENGTH); 647 bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL, 648 BE_CR_CTRL_TWAKEUP); 649 650 if (++bix == QEC_XD_RING_MAXSIZE) 651 bix = 0; 652 653 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 654 ifp->if_flags |= IFF_OACTIVE; 655 break; 656 } 657 } 658 659 sc->sc_rb.rb_tdhead = bix; 660 } 661 662 void 663 bestop(struct ifnet *ifp, int disable) 664 { 665 struct be_softc *sc = ifp->if_softc; 666 667 callout_stop(&sc->sc_tick_ch); 668 669 /* Down the MII. */ 670 mii_down(&sc->sc_mii); 671 (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN); 672 673 behwreset(sc); 674 } 675 676 void 677 behwreset(struct be_softc *sc) 678 { 679 int n; 680 bus_space_tag_t t = sc->sc_bustag; 681 bus_space_handle_t br = sc->sc_br; 682 683 /* Stop the transmitter */ 684 bus_space_write_4(t, br, BE_BRI_TXCFG, 0); 685 for (n = 32; n > 0; n--) { 686 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0) 687 break; 688 DELAY(20); 689 } 690 691 /* Stop the receiver */ 692 bus_space_write_4(t, br, BE_BRI_RXCFG, 0); 693 for (n = 32; n > 0; n--) { 694 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0) 695 break; 696 DELAY(20); 697 } 698 } 699 700 /* 701 * Reset interface. 702 */ 703 void 704 bereset(struct be_softc *sc) 705 { 706 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 707 int s; 708 709 s = splnet(); 710 behwreset(sc); 711 if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP) != 0) 712 beinit(ifp); 713 splx(s); 714 } 715 716 void 717 bewatchdog(struct ifnet *ifp) 718 { 719 struct be_softc *sc = ifp->if_softc; 720 721 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 722 ++sc->sc_ethercom.ec_if.if_oerrors; 723 724 bereset(sc); 725 } 726 727 int 728 beintr(void *arg) 729 { 730 struct be_softc *sc = arg; 731 bus_space_tag_t t = sc->sc_bustag; 732 u_int32_t whyq, whyb, whyc; 733 int r = 0; 734 735 /* Read QEC status, channel status and BE status */ 736 whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT); 737 whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT); 738 whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT); 739 740 if (whyq & QEC_STAT_BM) 741 r |= beeint(sc, whyb); 742 743 if (whyq & QEC_STAT_ER) 744 r |= beqint(sc, whyc); 745 746 if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ) 747 r |= betint(sc); 748 749 if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ) 750 r |= berint(sc); 751 752 return (r); 753 } 754 755 /* 756 * QEC Interrupt. 757 */ 758 int 759 beqint(struct be_softc *sc, u_int32_t why) 760 { 761 device_t self = sc->sc_dev; 762 int r = 0, rst = 0; 763 764 if (why & BE_CR_STAT_TXIRQ) 765 r |= 1; 766 if (why & BE_CR_STAT_RXIRQ) 767 r |= 1; 768 769 if (why & BE_CR_STAT_BERROR) { 770 r |= 1; 771 rst = 1; 772 aprint_error_dev(self, "bigmac error\n"); 773 } 774 775 if (why & BE_CR_STAT_TXDERR) { 776 r |= 1; 777 rst = 1; 778 aprint_error_dev(self, "bogus tx descriptor\n"); 779 } 780 781 if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) { 782 r |= 1; 783 rst = 1; 784 aprint_error_dev(self, "tx DMA error ( "); 785 if (why & BE_CR_STAT_TXLERR) 786 printf("Late "); 787 if (why & BE_CR_STAT_TXPERR) 788 printf("Parity "); 789 if (why & BE_CR_STAT_TXSERR) 790 printf("Generic "); 791 printf(")\n"); 792 } 793 794 if (why & BE_CR_STAT_RXDROP) { 795 r |= 1; 796 rst = 1; 797 aprint_error_dev(self, "out of rx descriptors\n"); 798 } 799 800 if (why & BE_CR_STAT_RXSMALL) { 801 r |= 1; 802 rst = 1; 803 aprint_error_dev(self, "rx descriptor too small\n"); 804 } 805 806 if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) { 807 r |= 1; 808 rst = 1; 809 aprint_error_dev(self, "rx DMA error ( "); 810 if (why & BE_CR_STAT_RXLERR) 811 printf("Late "); 812 if (why & BE_CR_STAT_RXPERR) 813 printf("Parity "); 814 if (why & BE_CR_STAT_RXSERR) 815 printf("Generic "); 816 printf(")\n"); 817 } 818 819 if (!r) { 820 rst = 1; 821 aprint_error_dev(self, "unexpected error interrupt %08x\n", 822 why); 823 } 824 825 if (rst) { 826 printf("%s: resetting\n", device_xname(self)); 827 bereset(sc); 828 } 829 830 return (r); 831 } 832 833 /* 834 * Error interrupt. 835 */ 836 int 837 beeint(struct be_softc *sc, u_int32_t why) 838 { 839 device_t self = sc->sc_dev; 840 int r = 0, rst = 0; 841 842 if (why & BE_BR_STAT_RFIFOVF) { 843 r |= 1; 844 rst = 1; 845 aprint_error_dev(self, "receive fifo overrun\n"); 846 } 847 if (why & BE_BR_STAT_TFIFO_UND) { 848 r |= 1; 849 rst = 1; 850 aprint_error_dev(self, "transmit fifo underrun\n"); 851 } 852 if (why & BE_BR_STAT_MAXPKTERR) { 853 r |= 1; 854 rst = 1; 855 aprint_error_dev(self, "max packet size error\n"); 856 } 857 858 if (!r) { 859 rst = 1; 860 aprint_error_dev(self, "unexpected error interrupt %08x\n", 861 why); 862 } 863 864 if (rst) { 865 printf("%s: resetting\n", device_xname(self)); 866 bereset(sc); 867 } 868 869 return (r); 870 } 871 872 /* 873 * Transmit interrupt. 874 */ 875 int 876 betint(struct be_softc *sc) 877 { 878 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 879 bus_space_tag_t t = sc->sc_bustag; 880 bus_space_handle_t br = sc->sc_br; 881 unsigned int bix, txflags; 882 883 /* 884 * Unload collision counters 885 */ 886 ifp->if_collisions += 887 bus_space_read_4(t, br, BE_BRI_NCCNT) + 888 bus_space_read_4(t, br, BE_BRI_FCCNT) + 889 bus_space_read_4(t, br, BE_BRI_EXCNT) + 890 bus_space_read_4(t, br, BE_BRI_LTCNT); 891 892 /* 893 * the clear the hardware counters 894 */ 895 bus_space_write_4(t, br, BE_BRI_NCCNT, 0); 896 bus_space_write_4(t, br, BE_BRI_FCCNT, 0); 897 bus_space_write_4(t, br, BE_BRI_EXCNT, 0); 898 bus_space_write_4(t, br, BE_BRI_LTCNT, 0); 899 900 bix = sc->sc_rb.rb_tdtail; 901 902 for (;;) { 903 if (sc->sc_rb.rb_td_nbusy <= 0) 904 break; 905 906 txflags = sc->sc_rb.rb_txd[bix].xd_flags; 907 908 if (txflags & QEC_XD_OWN) 909 break; 910 911 ifp->if_flags &= ~IFF_OACTIVE; 912 ifp->if_opackets++; 913 914 if (++bix == QEC_XD_RING_MAXSIZE) 915 bix = 0; 916 917 --sc->sc_rb.rb_td_nbusy; 918 } 919 920 sc->sc_rb.rb_tdtail = bix; 921 922 bestart(ifp); 923 924 if (sc->sc_rb.rb_td_nbusy == 0) 925 ifp->if_timer = 0; 926 927 return (1); 928 } 929 930 /* 931 * Receive interrupt. 932 */ 933 int 934 berint(struct be_softc *sc) 935 { 936 struct qec_xd *xd = sc->sc_rb.rb_rxd; 937 unsigned int bix, len; 938 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 939 940 bix = sc->sc_rb.rb_rdtail; 941 942 /* 943 * Process all buffers with valid data. 944 */ 945 for (;;) { 946 len = xd[bix].xd_flags; 947 if (len & QEC_XD_OWN) 948 break; 949 950 len &= QEC_XD_LENGTH; 951 be_read(sc, bix, len); 952 953 /* ... */ 954 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags = 955 QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH); 956 957 if (++bix == QEC_XD_RING_MAXSIZE) 958 bix = 0; 959 } 960 961 sc->sc_rb.rb_rdtail = bix; 962 963 return (1); 964 } 965 966 int 967 beioctl(struct ifnet *ifp, u_long cmd, void *data) 968 { 969 struct be_softc *sc = ifp->if_softc; 970 struct ifaddr *ifa = data; 971 struct ifreq *ifr = data; 972 int s, error = 0; 973 974 s = splnet(); 975 976 switch (cmd) { 977 case SIOCINITIFADDR: 978 ifp->if_flags |= IFF_UP; 979 beinit(ifp); 980 switch (ifa->ifa_addr->sa_family) { 981 #ifdef INET 982 case AF_INET: 983 arp_ifinit(ifp, ifa); 984 break; 985 #endif /* INET */ 986 default: 987 break; 988 } 989 break; 990 991 case SIOCSIFFLAGS: 992 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 993 break; 994 /* XXX re-use ether_ioctl() */ 995 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 996 case IFF_RUNNING: 997 /* 998 * If interface is marked down and it is running, then 999 * stop it. 1000 */ 1001 bestop(ifp, 0); 1002 ifp->if_flags &= ~IFF_RUNNING; 1003 break; 1004 case IFF_UP: 1005 /* 1006 * If interface is marked up and it is stopped, then 1007 * start it. 1008 */ 1009 beinit(ifp); 1010 break; 1011 default: 1012 /* 1013 * Reset the interface to pick up changes in any other 1014 * flags that affect hardware registers. 1015 */ 1016 bestop(ifp, 0); 1017 beinit(ifp); 1018 break; 1019 } 1020 #ifdef BEDEBUG 1021 if (ifp->if_flags & IFF_DEBUG) 1022 sc->sc_debug = 1; 1023 else 1024 sc->sc_debug = 0; 1025 #endif 1026 break; 1027 1028 case SIOCGIFMEDIA: 1029 case SIOCSIFMEDIA: 1030 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1031 break; 1032 default: 1033 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1034 /* 1035 * Multicast list has changed; set the hardware filter 1036 * accordingly. 1037 */ 1038 if (ifp->if_flags & IFF_RUNNING) 1039 error = beinit(ifp); 1040 else 1041 error = 0; 1042 } 1043 break; 1044 } 1045 splx(s); 1046 return (error); 1047 } 1048 1049 1050 int 1051 beinit(struct ifnet *ifp) 1052 { 1053 struct be_softc *sc = ifp->if_softc; 1054 bus_space_tag_t t = sc->sc_bustag; 1055 bus_space_handle_t br = sc->sc_br; 1056 bus_space_handle_t cr = sc->sc_cr; 1057 struct qec_softc *qec = sc->sc_qec; 1058 u_int32_t v; 1059 u_int32_t qecaddr; 1060 u_int8_t *ea; 1061 int rc, s; 1062 1063 s = splnet(); 1064 1065 qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ); 1066 1067 bestop(ifp, 1); 1068 1069 ea = sc->sc_enaddr; 1070 bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]); 1071 bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]); 1072 bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]); 1073 1074 /* Clear hash table */ 1075 bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0); 1076 bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0); 1077 bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0); 1078 bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0); 1079 1080 /* Re-initialize RX configuration */ 1081 v = BE_BR_RXCFG_FIFO; 1082 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1083 1084 be_mcreset(sc); 1085 1086 bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd); 1087 1088 bus_space_write_4(t, br, BE_BRI_XIFCFG, 1089 BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV); 1090 1091 bus_space_write_4(t, br, BE_BRI_JSIZE, 4); 1092 1093 /* 1094 * Turn off counter expiration interrupts as well as 1095 * 'gotframe' and 'sentframe' 1096 */ 1097 bus_space_write_4(t, br, BE_BRI_IMASK, 1098 BE_BR_IMASK_GOTFRAME | 1099 BE_BR_IMASK_RCNTEXP | 1100 BE_BR_IMASK_ACNTEXP | 1101 BE_BR_IMASK_CCNTEXP | 1102 BE_BR_IMASK_LCNTEXP | 1103 BE_BR_IMASK_CVCNTEXP | 1104 BE_BR_IMASK_SENTFRAME | 1105 BE_BR_IMASK_NCNTEXP | 1106 BE_BR_IMASK_ECNTEXP | 1107 BE_BR_IMASK_LCCNTEXP | 1108 BE_BR_IMASK_FCNTEXP | 1109 BE_BR_IMASK_DTIMEXP); 1110 1111 /* Channel registers: */ 1112 bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma); 1113 bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma); 1114 1115 qecaddr = sc->sc_channel * qec->sc_msize; 1116 bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr); 1117 bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr); 1118 bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize); 1119 bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize); 1120 1121 bus_space_write_4(t, cr, BE_CRI_RIMASK, 0); 1122 bus_space_write_4(t, cr, BE_CRI_TIMASK, 0); 1123 bus_space_write_4(t, cr, BE_CRI_QMASK, 0); 1124 bus_space_write_4(t, cr, BE_CRI_BMASK, 0); 1125 bus_space_write_4(t, cr, BE_CRI_CCNT, 0); 1126 1127 /* Set max packet length */ 1128 v = ETHER_MAX_LEN; 1129 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1130 v += ETHER_VLAN_ENCAP_LEN; 1131 bus_space_write_4(t, br, BE_BRI_RXMAX, v); 1132 bus_space_write_4(t, br, BE_BRI_TXMAX, v); 1133 1134 /* Enable transmitter */ 1135 bus_space_write_4(t, br, BE_BRI_TXCFG, 1136 BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE); 1137 1138 /* Enable receiver */ 1139 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1140 v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE; 1141 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1142 1143 if ((rc = be_ifmedia_upd(ifp)) != 0) 1144 goto out; 1145 1146 ifp->if_flags |= IFF_RUNNING; 1147 ifp->if_flags &= ~IFF_OACTIVE; 1148 1149 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1150 1151 return 0; 1152 out: 1153 splx(s); 1154 return rc; 1155 } 1156 1157 void 1158 be_mcreset(struct be_softc *sc) 1159 { 1160 struct ethercom *ec = &sc->sc_ethercom; 1161 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1162 bus_space_tag_t t = sc->sc_bustag; 1163 bus_space_handle_t br = sc->sc_br; 1164 u_int32_t crc; 1165 u_int16_t hash[4]; 1166 u_int8_t octet; 1167 u_int32_t v; 1168 int i, j; 1169 struct ether_multi *enm; 1170 struct ether_multistep step; 1171 1172 if (ifp->if_flags & IFF_PROMISC) { 1173 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1174 v |= BE_BR_RXCFG_PMISC; 1175 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1176 return; 1177 } 1178 1179 if (ifp->if_flags & IFF_ALLMULTI) { 1180 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1181 goto chipit; 1182 } 1183 1184 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1185 1186 ETHER_FIRST_MULTI(step, ec, enm); 1187 while (enm != NULL) { 1188 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1189 /* 1190 * We must listen to a range of multicast 1191 * addresses. For now, just accept all 1192 * multicasts, rather than trying to set only 1193 * those filter bits needed to match the range. 1194 * (At this time, the only use of address 1195 * ranges is for IP multicast routing, for 1196 * which the range is big enough to require 1197 * all bits set.) 1198 */ 1199 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1200 ifp->if_flags |= IFF_ALLMULTI; 1201 goto chipit; 1202 } 1203 1204 crc = 0xffffffff; 1205 1206 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1207 octet = enm->enm_addrlo[i]; 1208 1209 for (j = 0; j < 8; j++) { 1210 if ((crc & 1) ^ (octet & 1)) { 1211 crc >>= 1; 1212 crc ^= MC_POLY_LE; 1213 } 1214 else 1215 crc >>= 1; 1216 octet >>= 1; 1217 } 1218 } 1219 1220 crc >>= 26; 1221 hash[crc >> 4] |= 1 << (crc & 0xf); 1222 ETHER_NEXT_MULTI(step, enm); 1223 } 1224 1225 ifp->if_flags &= ~IFF_ALLMULTI; 1226 1227 chipit: 1228 /* Enable the hash filter */ 1229 bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]); 1230 bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]); 1231 bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]); 1232 bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]); 1233 1234 v = bus_space_read_4(t, br, BE_BRI_RXCFG); 1235 v &= ~BE_BR_RXCFG_PMISC; 1236 v |= BE_BR_RXCFG_HENABLE; 1237 bus_space_write_4(t, br, BE_BRI_RXCFG, v); 1238 } 1239 1240 /* 1241 * Set the tcvr to an idle state 1242 */ 1243 void 1244 be_mii_sync(struct be_softc *sc) 1245 { 1246 bus_space_tag_t t = sc->sc_bustag; 1247 bus_space_handle_t tr = sc->sc_tr; 1248 int n = 32; 1249 1250 while (n--) { 1251 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1252 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1253 MGMT_PAL_OENAB); 1254 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1255 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1256 MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | 1257 MGMT_PAL_OENAB | MGMT_PAL_DCLOCK); 1258 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1259 } 1260 } 1261 1262 void 1263 be_pal_gate(struct be_softc *sc, int phy) 1264 { 1265 bus_space_tag_t t = sc->sc_bustag; 1266 bus_space_handle_t tr = sc->sc_tr; 1267 u_int32_t v; 1268 1269 be_mii_sync(sc); 1270 1271 v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE); 1272 if (phy == BE_PHY_INTERNAL) 1273 v &= ~TCVR_PAL_SERIAL; 1274 1275 bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v); 1276 (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL); 1277 } 1278 1279 static int 1280 be_tcvr_read_bit(struct be_softc *sc, int phy) 1281 { 1282 bus_space_tag_t t = sc->sc_bustag; 1283 bus_space_handle_t tr = sc->sc_tr; 1284 int ret; 1285 1286 if (phy == BE_PHY_INTERNAL) { 1287 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO); 1288 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1289 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1290 MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK); 1291 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1292 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1293 MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT; 1294 } else { 1295 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO); 1296 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1297 ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) & 1298 MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT; 1299 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, 1300 MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK); 1301 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1302 } 1303 1304 return (ret); 1305 } 1306 1307 static void 1308 be_tcvr_write_bit(struct be_softc *sc, int phy, int bit) 1309 { 1310 bus_space_tag_t t = sc->sc_bustag; 1311 bus_space_handle_t tr = sc->sc_tr; 1312 u_int32_t v; 1313 1314 if (phy == BE_PHY_INTERNAL) { 1315 v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) | 1316 MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO; 1317 } else { 1318 v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT) 1319 | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO; 1320 } 1321 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v); 1322 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1323 bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK); 1324 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL); 1325 } 1326 1327 static void 1328 be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits) 1329 { 1330 int i; 1331 1332 for (i = 1 << (nbits - 1); i != 0; i >>= 1) { 1333 be_tcvr_write_bit(sc, phy, (data & i) != 0); 1334 } 1335 } 1336 1337 static int 1338 be_mii_readreg(device_t self, int phy, int reg) 1339 { 1340 struct be_softc *sc = device_private(self); 1341 int val = 0, i; 1342 1343 /* 1344 * Read the PHY register by manually driving the MII control lines. 1345 */ 1346 be_mii_sync(sc); 1347 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1348 be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2); 1349 be_mii_sendbits(sc, phy, phy, 5); 1350 be_mii_sendbits(sc, phy, reg, 5); 1351 1352 (void) be_tcvr_read_bit(sc, phy); 1353 (void) be_tcvr_read_bit(sc, phy); 1354 1355 for (i = 15; i >= 0; i--) 1356 val |= (be_tcvr_read_bit(sc, phy) << i); 1357 1358 (void) be_tcvr_read_bit(sc, phy); 1359 (void) be_tcvr_read_bit(sc, phy); 1360 (void) be_tcvr_read_bit(sc, phy); 1361 1362 return (val); 1363 } 1364 1365 void 1366 be_mii_writereg(device_t self, int phy, int reg, int val) 1367 { 1368 struct be_softc *sc = device_private(self); 1369 int i; 1370 1371 /* 1372 * Write the PHY register by manually driving the MII control lines. 1373 */ 1374 be_mii_sync(sc); 1375 be_mii_sendbits(sc, phy, MII_COMMAND_START, 2); 1376 be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2); 1377 be_mii_sendbits(sc, phy, phy, 5); 1378 be_mii_sendbits(sc, phy, reg, 5); 1379 1380 be_tcvr_write_bit(sc, phy, 1); 1381 be_tcvr_write_bit(sc, phy, 0); 1382 1383 for (i = 15; i >= 0; i--) 1384 be_tcvr_write_bit(sc, phy, (val >> i) & 1); 1385 } 1386 1387 int 1388 be_mii_reset(struct be_softc *sc, int phy) 1389 { 1390 device_t self = sc->sc_dev; 1391 int n; 1392 1393 be_mii_writereg(self, phy, MII_BMCR, 1394 BMCR_LOOP | BMCR_PDOWN | BMCR_ISO); 1395 be_mii_writereg(self, phy, MII_BMCR, BMCR_RESET); 1396 1397 for (n = 16; n >= 0; n--) { 1398 int bmcr = be_mii_readreg(self, phy, MII_BMCR); 1399 if ((bmcr & BMCR_RESET) == 0) 1400 break; 1401 DELAY(20); 1402 } 1403 if (n == 0) { 1404 aprint_error_dev(self, "bmcr reset failed\n"); 1405 return (EIO); 1406 } 1407 1408 return (0); 1409 } 1410 1411 void 1412 be_tick(void *arg) 1413 { 1414 struct be_softc *sc = arg; 1415 int s = splnet(); 1416 1417 mii_tick(&sc->sc_mii); 1418 (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK); 1419 1420 splx(s); 1421 callout_reset(&sc->sc_tick_ch, hz, be_tick, sc); 1422 } 1423 1424 void 1425 be_mii_statchg(device_t self) 1426 { 1427 struct be_softc *sc = device_private(self); 1428 bus_space_tag_t t = sc->sc_bustag; 1429 bus_space_handle_t br = sc->sc_br; 1430 u_int instance; 1431 u_int32_t v; 1432 1433 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1434 #ifdef DIAGNOSTIC 1435 if (instance > 1) 1436 panic("be_mii_statchg: instance %d out of range", instance); 1437 #endif 1438 1439 /* Update duplex mode in TX configuration */ 1440 v = bus_space_read_4(t, br, BE_BRI_TXCFG); 1441 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1442 v |= BE_BR_TXCFG_FULLDPLX; 1443 else 1444 v &= ~BE_BR_TXCFG_FULLDPLX; 1445 bus_space_write_4(t, br, BE_BRI_TXCFG, v); 1446 1447 /* Change to appropriate gate in transceiver PAL */ 1448 be_pal_gate(sc, sc->sc_phys[instance]); 1449 } 1450 1451 /* 1452 * Get current media settings. 1453 */ 1454 void 1455 be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1456 { 1457 struct be_softc *sc = ifp->if_softc; 1458 1459 mii_pollstat(&sc->sc_mii); 1460 (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT); 1461 1462 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1463 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1464 return; 1465 } 1466 1467 /* 1468 * Set media options. 1469 */ 1470 int 1471 be_ifmedia_upd(struct ifnet *ifp) 1472 { 1473 struct be_softc *sc = ifp->if_softc; 1474 int error; 1475 1476 if ((error = mii_mediachg(&sc->sc_mii)) == ENXIO) 1477 error = 0; 1478 else if (error != 0) 1479 return error; 1480 1481 return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG)); 1482 } 1483 1484 /* 1485 * Service routine for our pseudo-MII internal transceiver. 1486 */ 1487 int 1488 be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd) 1489 { 1490 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 1491 device_t self = sc->sc_dev; 1492 int bmcr, bmsr; 1493 int error; 1494 1495 switch (cmd) { 1496 case MII_POLLSTAT: 1497 /* 1498 * If we're not polling our PHY instance, just return. 1499 */ 1500 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1501 return (0); 1502 1503 break; 1504 1505 case MII_MEDIACHG: 1506 1507 /* 1508 * If the media indicates a different PHY instance, 1509 * isolate ourselves. 1510 */ 1511 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) { 1512 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1513 be_mii_writereg(self, 1514 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1515 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1516 sc->sc_intphy_curspeed = 0; 1517 return (0); 1518 } 1519 1520 1521 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0) 1522 return (error); 1523 1524 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1525 1526 /* 1527 * Select the new mode and take out of isolation 1528 */ 1529 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX) 1530 bmcr |= BMCR_S100; 1531 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T) 1532 bmcr &= ~BMCR_S100; 1533 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 1534 if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) { 1535 bmcr &= ~BMCR_S100; 1536 bmcr |= sc->sc_intphy_curspeed; 1537 } else { 1538 /* Keep isolated until link is up */ 1539 bmcr |= BMCR_ISO; 1540 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1541 } 1542 } 1543 1544 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0) 1545 bmcr |= BMCR_FDX; 1546 else 1547 bmcr &= ~BMCR_FDX; 1548 1549 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1550 break; 1551 1552 case MII_TICK: 1553 /* 1554 * If we're not currently selected, just return. 1555 */ 1556 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) 1557 return (0); 1558 1559 /* Only used for automatic media selection */ 1560 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) 1561 return (0); 1562 1563 /* Is the interface even up? */ 1564 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 1565 return (0); 1566 1567 /* 1568 * Check link status; if we don't have a link, try another 1569 * speed. We can't detect duplex mode, so half-duplex is 1570 * what we have to settle for. 1571 */ 1572 1573 /* Read twice in case the register is latched */ 1574 bmsr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR) | 1575 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1576 1577 if ((bmsr & BMSR_LINK) != 0) { 1578 /* We have a carrier */ 1579 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1580 1581 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) { 1582 bmcr = be_mii_readreg(self, 1583 BE_PHY_INTERNAL, MII_BMCR); 1584 1585 sc->sc_mii_flags |= MIIF_HAVELINK; 1586 sc->sc_intphy_curspeed = (bmcr & BMCR_S100); 1587 sc->sc_mii_flags &= ~MIIF_DOINGAUTO; 1588 1589 bmcr &= ~BMCR_ISO; 1590 be_mii_writereg(self, 1591 BE_PHY_INTERNAL, MII_BMCR, bmcr); 1592 1593 printf("%s: link up at %s Mbps\n", 1594 device_xname(self), 1595 (bmcr & BMCR_S100) ? "100" : "10"); 1596 } 1597 return (0); 1598 } 1599 1600 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) { 1601 sc->sc_mii_flags |= MIIF_DOINGAUTO; 1602 sc->sc_mii_flags &= ~MIIF_HAVELINK; 1603 sc->sc_intphy_curspeed = 0; 1604 printf("%s: link down\n", device_xname(self)); 1605 } 1606 1607 /* Only retry autonegotiation every 5 seconds. */ 1608 if (++sc->sc_mii_ticks < 5) 1609 return(0); 1610 1611 sc->sc_mii_ticks = 0; 1612 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1613 /* Just flip the fast speed bit */ 1614 bmcr ^= BMCR_S100; 1615 be_mii_writereg(self, BE_PHY_INTERNAL, MII_BMCR, bmcr); 1616 1617 break; 1618 1619 case MII_DOWN: 1620 /* Isolate this phy */ 1621 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1622 be_mii_writereg(self, 1623 BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO); 1624 return (0); 1625 } 1626 1627 /* Update the media status. */ 1628 be_intphy_status(sc); 1629 1630 /* Callback if something changed. */ 1631 if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) { 1632 (*mii->mii_statchg)(self); 1633 sc->sc_mii_active = mii->mii_media_active; 1634 } 1635 return (0); 1636 } 1637 1638 /* 1639 * Determine status of internal transceiver 1640 */ 1641 void 1642 be_intphy_status(struct be_softc *sc) 1643 { 1644 struct mii_data *mii = &sc->sc_mii; 1645 device_t self = sc->sc_dev; 1646 int media_active, media_status; 1647 int bmcr, bmsr; 1648 1649 media_status = IFM_AVALID; 1650 media_active = 0; 1651 1652 /* 1653 * Internal transceiver; do the work here. 1654 */ 1655 bmcr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMCR); 1656 1657 switch (bmcr & (BMCR_S100 | BMCR_FDX)) { 1658 case (BMCR_S100 | BMCR_FDX): 1659 media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1660 break; 1661 case BMCR_S100: 1662 media_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1663 break; 1664 case BMCR_FDX: 1665 media_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1666 break; 1667 case 0: 1668 media_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1669 break; 1670 } 1671 1672 /* Read twice in case the register is latched */ 1673 bmsr = be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR)| 1674 be_mii_readreg(self, BE_PHY_INTERNAL, MII_BMSR); 1675 if (bmsr & BMSR_LINK) 1676 media_status |= IFM_ACTIVE; 1677 1678 mii->mii_media_status = media_status; 1679 mii->mii_media_active = media_active; 1680 } 1681
Indexes created Tue Sep 30 07:10:03 GMT 2025